283 lines · c
1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * AMCC SoC PPC4xx Crypto Driver4 *5 * Copyright (c) 2008 Applied Micro Circuits Corporation.6 * All rights reserved. James Hsiao <jhsiao@amcc.com>7 *8 * This filr defines the register set for Security Subsystem9 */10 11#ifndef __CRYPTO4XX_REG_DEF_H__12#define __CRYPTO4XX_REG_DEF_H__13 14/* CRYPTO4XX Register offset */15#define CRYPTO4XX_DESCRIPTOR 0x0000000016#define CRYPTO4XX_CTRL_STAT 0x0000000017#define CRYPTO4XX_SOURCE 0x0000000418#define CRYPTO4XX_DEST 0x0000000819#define CRYPTO4XX_SA 0x0000000C20#define CRYPTO4XX_SA_LENGTH 0x0000001021#define CRYPTO4XX_LENGTH 0x0000001422 23#define CRYPTO4XX_PE_DMA_CFG 0x0000004024#define CRYPTO4XX_PE_DMA_STAT 0x0000004425#define CRYPTO4XX_PDR_BASE 0x0000004826#define CRYPTO4XX_RDR_BASE 0x0000004c27#define CRYPTO4XX_RING_SIZE 0x0000005028#define CRYPTO4XX_RING_CTRL 0x0000005429#define CRYPTO4XX_INT_RING_STAT 0x0000005830#define CRYPTO4XX_EXT_RING_STAT 0x0000005c31#define CRYPTO4XX_IO_THRESHOLD 0x0000006032#define CRYPTO4XX_GATH_RING_BASE 0x0000006433#define CRYPTO4XX_SCAT_RING_BASE 0x0000006834#define CRYPTO4XX_PART_RING_SIZE 0x0000006c35#define CRYPTO4XX_PART_RING_CFG 0x0000007036 37#define CRYPTO4XX_PDR_BASE_UADDR 0x0000008038#define CRYPTO4XX_RDR_BASE_UADDR 0x0000008439#define CRYPTO4XX_PKT_SRC_UADDR 0x0000008840#define CRYPTO4XX_PKT_DEST_UADDR 0x0000008c41#define CRYPTO4XX_SA_UADDR 0x0000009042#define CRYPTO4XX_GATH_RING_BASE_UADDR 0x000000A043#define CRYPTO4XX_SCAT_RING_BASE_UADDR 0x000000A444 45#define CRYPTO4XX_SEQ_RD 0x0000040846#define CRYPTO4XX_SEQ_MASK_RD 0x0000040C47 48#define CRYPTO4XX_SA_CMD_0 0x0001060049#define CRYPTO4XX_SA_CMD_1 0x0001060450 51#define CRYPTO4XX_STATE_PTR 0x000106dc52#define CRYPTO4XX_STATE_IV 0x0001070053#define CRYPTO4XX_STATE_HASH_BYTE_CNT_0 0x0001071054#define CRYPTO4XX_STATE_HASH_BYTE_CNT_1 0x0001071455 56#define CRYPTO4XX_STATE_IDIGEST_0 0x0001071857#define CRYPTO4XX_STATE_IDIGEST_1 0x0001071c58 59#define CRYPTO4XX_DATA_IN 0x0001800060#define CRYPTO4XX_DATA_OUT 0x0001c00061 62#define CRYPTO4XX_INT_UNMASK_STAT 0x000500a063#define CRYPTO4XX_INT_MASK_STAT 0x000500a464#define CRYPTO4XX_INT_CLR 0x000500a465#define CRYPTO4XX_INT_EN 0x000500a866 67#define CRYPTO4XX_INT_PKA 0x0000000268#define CRYPTO4XX_INT_PDR_DONE 0x0000800069#define CRYPTO4XX_INT_MA_WR_ERR 0x0002000070#define CRYPTO4XX_INT_MA_RD_ERR 0x0001000071#define CRYPTO4XX_INT_PE_ERR 0x0000020072#define CRYPTO4XX_INT_USER_DMA_ERR 0x0000004073#define CRYPTO4XX_INT_SLAVE_ERR 0x0000001074#define CRYPTO4XX_INT_MASTER_ERR 0x0000000875#define CRYPTO4XX_INT_ERROR 0x0003025876 77#define CRYPTO4XX_INT_CFG 0x000500ac78#define CRYPTO4XX_INT_DESCR_RD 0x000500b079#define CRYPTO4XX_INT_DESCR_CNT 0x000500b480#define CRYPTO4XX_INT_TIMEOUT_CNT 0x000500b881 82#define CRYPTO4XX_DEVICE_CTRL 0x0006008083#define CRYPTO4XX_DEVICE_ID 0x0006008484#define CRYPTO4XX_DEVICE_INFO 0x0006008885#define CRYPTO4XX_DMA_USER_SRC 0x0006009486#define CRYPTO4XX_DMA_USER_DEST 0x0006009887#define CRYPTO4XX_DMA_USER_CMD 0x0006009C88 89#define CRYPTO4XX_DMA_CFG 0x000600d490#define CRYPTO4XX_BYTE_ORDER_CFG 0x000600d891#define CRYPTO4XX_ENDIAN_CFG 0x000600d892 93#define CRYPTO4XX_PRNG_STAT 0x0007000094#define CRYPTO4XX_PRNG_STAT_BUSY 0x195#define CRYPTO4XX_PRNG_CTRL 0x0007000496#define CRYPTO4XX_PRNG_SEED_L 0x0007000897#define CRYPTO4XX_PRNG_SEED_H 0x0007000c98 99#define CRYPTO4XX_PRNG_RES_0 0x00070020100#define CRYPTO4XX_PRNG_RES_1 0x00070024101#define CRYPTO4XX_PRNG_RES_2 0x00070028102#define CRYPTO4XX_PRNG_RES_3 0x0007002C103 104#define CRYPTO4XX_PRNG_LFSR_L 0x00070030105#define CRYPTO4XX_PRNG_LFSR_H 0x00070034106 107/*108 * Initialize CRYPTO ENGINE registers, and memory bases.109 */110#define PPC4XX_PDR_POLL 0x3ff111#define PPC4XX_OUTPUT_THRESHOLD 2112#define PPC4XX_INPUT_THRESHOLD 2113#define PPC4XX_PD_SIZE 6114#define PPC4XX_CTX_DONE_INT 0x2000115#define PPC4XX_PD_DONE_INT 0x8000116#define PPC4XX_TMO_ERR_INT 0x40000117#define PPC4XX_BYTE_ORDER 0x22222118#define PPC4XX_INTERRUPT_CLR 0x3ffff119#define PPC4XX_PRNG_CTRL_AUTO_EN 0x3120#define PPC4XX_DC_3DES_EN 1121#define PPC4XX_TRNG_EN 0x00020000122#define PPC4XX_INT_DESCR_CNT 7123#define PPC4XX_INT_TIMEOUT_CNT 0124#define PPC4XX_INT_TIMEOUT_CNT_REVB 0x3FF125#define PPC4XX_INT_CFG 1126/*127 * all follow define are ad hoc128 */129#define PPC4XX_RING_RETRY 100130#define PPC4XX_RING_POLL 100131#define PPC4XX_SDR_SIZE PPC4XX_NUM_SD132#define PPC4XX_GDR_SIZE PPC4XX_NUM_GD133 134/*135 * Generic Security Association (SA) with all possible fields. These will136 * never likely used except for reference purpose. These structure format137 * can be not changed as the hardware expects them to be layout as defined.138 * Field can be removed or reduced but ordering can not be changed.139 */140#define CRYPTO4XX_DMA_CFG_OFFSET 0x40141union ce_pe_dma_cfg {142 struct {143 u32 rsv:7;144 u32 dir_host:1;145 u32 rsv1:2;146 u32 bo_td_en:1;147 u32 dis_pdr_upd:1;148 u32 bo_sgpd_en:1;149 u32 bo_data_en:1;150 u32 bo_sa_en:1;151 u32 bo_pd_en:1;152 u32 rsv2:4;153 u32 dynamic_sa_en:1;154 u32 pdr_mode:2;155 u32 pe_mode:1;156 u32 rsv3:5;157 u32 reset_sg:1;158 u32 reset_pdr:1;159 u32 reset_pe:1;160 } bf;161 u32 w;162} __attribute__((packed));163 164#define CRYPTO4XX_PDR_BASE_OFFSET 0x48165#define CRYPTO4XX_RDR_BASE_OFFSET 0x4c166#define CRYPTO4XX_RING_SIZE_OFFSET 0x50167union ce_ring_size {168 struct {169 u32 ring_offset:16;170 u32 rsv:6;171 u32 ring_size:10;172 } bf;173 u32 w;174} __attribute__((packed));175 176#define CRYPTO4XX_RING_CONTROL_OFFSET 0x54177union ce_ring_control {178 struct {179 u32 continuous:1;180 u32 rsv:5;181 u32 ring_retry_divisor:10;182 u32 rsv1:4;183 u32 ring_poll_divisor:10;184 } bf;185 u32 w;186} __attribute__((packed));187 188#define CRYPTO4XX_IO_THRESHOLD_OFFSET 0x60189union ce_io_threshold {190 struct {191 u32 rsv:6;192 u32 output_threshold:10;193 u32 rsv1:6;194 u32 input_threshold:10;195 } bf;196 u32 w;197} __attribute__((packed));198 199#define CRYPTO4XX_GATHER_RING_BASE_OFFSET 0x64200#define CRYPTO4XX_SCATTER_RING_BASE_OFFSET 0x68201 202union ce_part_ring_size {203 struct {204 u32 sdr_size:16;205 u32 gdr_size:16;206 } bf;207 u32 w;208} __attribute__((packed));209 210#define MAX_BURST_SIZE_32 0211#define MAX_BURST_SIZE_64 1212#define MAX_BURST_SIZE_128 2213#define MAX_BURST_SIZE_256 3214 215/* gather descriptor control length */216struct gd_ctl_len {217 u32 len:16;218 u32 rsv:14;219 u32 done:1;220 u32 ready:1;221} __attribute__((packed));222 223struct ce_gd {224 u32 ptr;225 struct gd_ctl_len ctl_len;226} __attribute__((packed));227 228struct sd_ctl {229 u32 ctl:30;230 u32 done:1;231 u32 rdy:1;232} __attribute__((packed));233 234struct ce_sd {235 u32 ptr;236 struct sd_ctl ctl;237} __attribute__((packed));238 239#define PD_PAD_CTL_32 0x10240#define PD_PAD_CTL_64 0x20241#define PD_PAD_CTL_128 0x40242#define PD_PAD_CTL_256 0x80243union ce_pd_ctl {244 struct {245 u32 pd_pad_ctl:8;246 u32 status:8;247 u32 next_hdr:8;248 u32 rsv:2;249 u32 cached_sa:1;250 u32 hash_final:1;251 u32 init_arc4:1;252 u32 rsv1:1;253 u32 pe_done:1;254 u32 host_ready:1;255 } bf;256 u32 w;257} __attribute__((packed));258#define PD_CTL_HASH_FINAL BIT(4)259#define PD_CTL_PE_DONE BIT(1)260#define PD_CTL_HOST_READY BIT(0)261 262union ce_pd_ctl_len {263 struct {264 u32 bypass:8;265 u32 pe_done:1;266 u32 host_ready:1;267 u32 rsv:2;268 u32 pkt_len:20;269 } bf;270 u32 w;271} __attribute__((packed));272 273struct ce_pd {274 union ce_pd_ctl pd_ctl;275 u32 src;276 u32 dest;277 u32 sa; /* get from ctx->sa_dma_addr */278 u32 sa_len; /* only if dynamic sa is used */279 union ce_pd_ctl_len pd_ctl_len;280 281} __attribute__((packed));282#endif283