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1/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */2/*3 * Copyright 2015-2016 Freescale Semiconductor Inc.4 * Copyright 2017-2018 NXP5 */6 7#ifndef _CAAMALG_QI2_H_8#define _CAAMALG_QI2_H_9 10#include <crypto/internal/skcipher.h>11#include <linux/compiler_attributes.h>12#include <soc/fsl/dpaa2-io.h>13#include <soc/fsl/dpaa2-fd.h>14#include <linux/threads.h>15#include <linux/netdevice.h>16#include "dpseci.h"17#include "desc_constr.h"18 19#define DPAA2_CAAM_STORE_SIZE 1620/* NAPI weight *must* be a multiple of the store size. */21#define DPAA2_CAAM_NAPI_WEIGHT 51222 23/* The congestion entrance threshold was chosen so that on LS208824 * we support the maximum throughput for the available memory25 */26#define DPAA2_SEC_CONG_ENTRY_THRESH (128 * 1024 * 1024)27#define DPAA2_SEC_CONG_EXIT_THRESH (DPAA2_SEC_CONG_ENTRY_THRESH * 9 / 10)28 29/**30 * dpaa2_caam_priv - driver private data31 * @dpseci_id: DPSECI object unique ID32 * @major_ver: DPSECI major version33 * @minor_ver: DPSECI minor version34 * @dpseci_attr: DPSECI attributes35 * @sec_attr: SEC engine attributes36 * @rx_queue_attr: array of Rx queue attributes37 * @tx_queue_attr: array of Tx queue attributes38 * @cscn_mem: pointer to memory region containing the congestion SCN39 * it's size is larger than to accommodate alignment40 * @cscn_dma: dma address used by the QMAN to write CSCN messages41 * @dev: device associated with the DPSECI object42 * @mc_io: pointer to MC portal's I/O object43 * @domain: IOMMU domain44 * @ppriv: per CPU pointers to privata data45 */46struct dpaa2_caam_priv {47 int dpsec_id;48 49 u16 major_ver;50 u16 minor_ver;51 52 struct dpseci_attr dpseci_attr;53 struct dpseci_sec_attr sec_attr;54 struct dpseci_rx_queue_attr rx_queue_attr[DPSECI_MAX_QUEUE_NUM];55 struct dpseci_tx_queue_attr tx_queue_attr[DPSECI_MAX_QUEUE_NUM];56 int num_pairs;57 58 /* congestion */59 void *cscn_mem;60 dma_addr_t cscn_dma;61 62 struct device *dev;63 struct fsl_mc_io *mc_io;64 struct iommu_domain *domain;65 66 struct dpaa2_caam_priv_per_cpu __percpu *ppriv;67 struct dentry *dfs_root;68};69 70/**71 * dpaa2_caam_priv_per_cpu - per CPU private data72 * @napi: napi structure73 * @net_dev: netdev used by napi74 * @req_fqid: (virtual) request (Tx / enqueue) FQID75 * @rsp_fqid: (virtual) response (Rx / dequeue) FQID76 * @prio: internal queue number - index for dpaa2_caam_priv.*_queue_attr77 * @nctx: notification context of response FQ78 * @store: where dequeued frames are stored79 * @priv: backpointer to dpaa2_caam_priv80 * @dpio: portal used for data path operations81 */82struct dpaa2_caam_priv_per_cpu {83 struct napi_struct napi;84 struct net_device *net_dev;85 int req_fqid;86 int rsp_fqid;87 int prio;88 struct dpaa2_io_notification_ctx nctx;89 struct dpaa2_io_store *store;90 struct dpaa2_caam_priv *priv;91 struct dpaa2_io *dpio;92};93 94/* Length of a single buffer in the QI driver memory cache */95#define CAAM_QI_MEMCACHE_SIZE 51296 97/*98 * aead_edesc - s/w-extended aead descriptor99 * @src_nents: number of segments in input scatterlist100 * @dst_nents: number of segments in output scatterlist101 * @iv_dma: dma address of iv for checking continuity and link table102 * @qm_sg_bytes: length of dma mapped h/w link table103 * @qm_sg_dma: bus physical mapped address of h/w link table104 * @assoclen: associated data length, in CAAM endianness105 * @assoclen_dma: bus physical mapped address of req->assoclen106 * @sgt: the h/w link table, followed by IV107 */108struct aead_edesc {109 int src_nents;110 int dst_nents;111 dma_addr_t iv_dma;112 int qm_sg_bytes;113 dma_addr_t qm_sg_dma;114 unsigned int assoclen;115 dma_addr_t assoclen_dma;116 struct dpaa2_sg_entry sgt[];117};118 119/*120 * skcipher_edesc - s/w-extended skcipher descriptor121 * @src_nents: number of segments in input scatterlist122 * @dst_nents: number of segments in output scatterlist123 * @iv_dma: dma address of iv for checking continuity and link table124 * @qm_sg_bytes: length of dma mapped qm_sg space125 * @qm_sg_dma: I/O virtual address of h/w link table126 * @sgt: the h/w link table, followed by IV127 */128struct skcipher_edesc {129 int src_nents;130 int dst_nents;131 dma_addr_t iv_dma;132 int qm_sg_bytes;133 dma_addr_t qm_sg_dma;134 struct dpaa2_sg_entry sgt[];135};136 137/*138 * ahash_edesc - s/w-extended ahash descriptor139 * @qm_sg_dma: I/O virtual address of h/w link table140 * @src_nents: number of segments in input scatterlist141 * @qm_sg_bytes: length of dma mapped qm_sg space142 * @sgt: pointer to h/w link table143 */144struct ahash_edesc {145 dma_addr_t qm_sg_dma;146 int src_nents;147 int qm_sg_bytes;148 struct dpaa2_sg_entry sgt[];149};150 151/**152 * caam_flc - Flow Context (FLC)153 * @flc: Flow Context options154 * @sh_desc: Shared Descriptor155 */156struct caam_flc {157 u32 flc[16];158 u32 sh_desc[MAX_SDLEN];159} __aligned(CRYPTO_DMA_ALIGN);160 161enum optype {162 ENCRYPT = 0,163 DECRYPT,164 NUM_OP165};166 167/**168 * caam_request - the request structure the driver application should fill while169 * submitting a job to driver.170 * @fd_flt: Frame list table defining input and output171 * fd_flt[0] - FLE pointing to output buffer172 * fd_flt[1] - FLE pointing to input buffer173 * @fd_flt_dma: DMA address for the frame list table174 * @flc: Flow Context175 * @flc_dma: I/O virtual address of Flow Context176 * @cbk: Callback function to invoke when job is completed177 * @ctx: arbit context attached with request by the application178 * @edesc: extended descriptor; points to one of {skcipher,aead}_edesc179 */180struct caam_request {181 struct dpaa2_fl_entry fd_flt[2] __aligned(CRYPTO_DMA_ALIGN);182 dma_addr_t fd_flt_dma;183 struct caam_flc *flc;184 dma_addr_t flc_dma;185 void (*cbk)(void *ctx, u32 err);186 void *ctx;187 void *edesc;188 struct skcipher_request fallback_req;189};190 191/**192 * dpaa2_caam_enqueue() - enqueue a crypto request193 * @dev: device associated with the DPSECI object194 * @req: pointer to caam_request195 */196int dpaa2_caam_enqueue(struct device *dev, struct caam_request *req);197 198#endif /* _CAAMALG_QI2_H_ */199