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1/* SPDX-License-Identifier: GPL-2.0 */2#ifndef __NITROX_CSR_H3#define __NITROX_CSR_H4 5#include <asm/byteorder.h>6#include <linux/types.h>7 8/* EMU clusters */9#define NR_CLUSTERS 410/* Maximum cores per cluster,11 * varies based on partname12 */13#define AE_CORES_PER_CLUSTER 2014#define SE_CORES_PER_CLUSTER 1615 16#define AE_MAX_CORES (AE_CORES_PER_CLUSTER * NR_CLUSTERS)17#define SE_MAX_CORES (SE_CORES_PER_CLUSTER * NR_CLUSTERS)18#define ZIP_MAX_CORES 519 20/* BIST registers */21#define EMU_BIST_STATUSX(_i) (0x1402700 + ((_i) * 0x40000))22#define UCD_BIST_STATUS 0x12C007023#define NPS_CORE_BIST_REG 0x10000E824#define NPS_CORE_NPC_BIST_REG 0x100012825#define NPS_PKT_SLC_BIST_REG 0x104008826#define NPS_PKT_IN_BIST_REG 0x104010027#define POM_BIST_REG 0x11C010028#define BMI_BIST_REG 0x114008029#define EFL_CORE_BIST_REGX(_i) (0x1240100 + ((_i) * 0x400))30#define EFL_TOP_BIST_STAT 0x124109031#define BMO_BIST_REG 0x118008032#define LBC_BIST_STATUS 0x120002033#define PEM_BIST_STATUSX(_i) (0x1080468 | ((_i) << 18))34 35/* EMU registers */36#define EMU_SE_ENABLEX(_i) (0x1400000 + ((_i) * 0x40000))37#define EMU_AE_ENABLEX(_i) (0x1400008 + ((_i) * 0x40000))38#define EMU_WD_INT_ENA_W1SX(_i) (0x1402318 + ((_i) * 0x40000))39#define EMU_GE_INT_ENA_W1SX(_i) (0x1402518 + ((_i) * 0x40000))40#define EMU_FUSE_MAPX(_i) (0x1402708 + ((_i) * 0x40000))41 42/* UCD registers */43#define UCD_SE_EID_UCODE_BLOCK_NUMX(_i) (0x12C0000 + ((_i) * 0x1000))44#define UCD_AE_EID_UCODE_BLOCK_NUMX(_i) (0x12C0008 + ((_i) * 0x800))45#define UCD_UCODE_LOAD_BLOCK_NUM 0x12C001046#define UCD_UCODE_LOAD_IDX_DATAX(_i) (0x12C0018 + ((_i) * 0x20))47#define UCD_SE_CNTX(_i) (0x12C0040 + ((_i) * 0x1000))48#define UCD_AE_CNTX(_i) (0x12C0048 + ((_i) * 0x800))49 50/* AQM registers */51#define AQM_CTL 0x130000052#define AQM_INT 0x130000853#define AQM_DBELL_OVF_LO 0x130001054#define AQM_DBELL_OVF_HI 0x130001855#define AQM_DBELL_OVF_LO_W1S 0x130002056#define AQM_DBELL_OVF_LO_ENA_W1C 0x130002857#define AQM_DBELL_OVF_LO_ENA_W1S 0x130003058#define AQM_DBELL_OVF_HI_W1S 0x130003859#define AQM_DBELL_OVF_HI_ENA_W1C 0x130004060#define AQM_DBELL_OVF_HI_ENA_W1S 0x130004861#define AQM_DMA_RD_ERR_LO 0x130005062#define AQM_DMA_RD_ERR_HI 0x130005863#define AQM_DMA_RD_ERR_LO_W1S 0x130006064#define AQM_DMA_RD_ERR_LO_ENA_W1C 0x130006865#define AQM_DMA_RD_ERR_LO_ENA_W1S 0x130007066#define AQM_DMA_RD_ERR_HI_W1S 0x130007867#define AQM_DMA_RD_ERR_HI_ENA_W1C 0x130008068#define AQM_DMA_RD_ERR_HI_ENA_W1S 0x130008869#define AQM_EXEC_NA_LO 0x130009070#define AQM_EXEC_NA_HI 0x130009871#define AQM_EXEC_NA_LO_W1S 0x13000A072#define AQM_EXEC_NA_LO_ENA_W1C 0x13000A873#define AQM_EXEC_NA_LO_ENA_W1S 0x13000B074#define AQM_EXEC_NA_HI_W1S 0x13000B875#define AQM_EXEC_NA_HI_ENA_W1C 0x13000C076#define AQM_EXEC_NA_HI_ENA_W1S 0x13000C877#define AQM_EXEC_ERR_LO 0x13000D078#define AQM_EXEC_ERR_HI 0x13000D879#define AQM_EXEC_ERR_LO_W1S 0x13000E080#define AQM_EXEC_ERR_LO_ENA_W1C 0x13000E881#define AQM_EXEC_ERR_LO_ENA_W1S 0x13000F082#define AQM_EXEC_ERR_HI_W1S 0x13000F883#define AQM_EXEC_ERR_HI_ENA_W1C 0x130010084#define AQM_EXEC_ERR_HI_ENA_W1S 0x130010885#define AQM_ECC_INT 0x130011086#define AQM_ECC_INT_W1S 0x130011887#define AQM_ECC_INT_ENA_W1C 0x130012088#define AQM_ECC_INT_ENA_W1S 0x130012889#define AQM_ECC_CTL 0x130013090#define AQM_BIST_STATUS 0x130013891#define AQM_CMD_INF_THRX(x) (0x1300400 + ((x) * 0x8))92#define AQM_CMD_INFX(x) (0x1300800 + ((x) * 0x8))93#define AQM_GRP_EXECMSK_LOX(x) (0x1300C00 + ((x) * 0x10))94#define AQM_GRP_EXECMSK_HIX(x) (0x1300C08 + ((x) * 0x10))95#define AQM_ACTIVITY_STAT_LO 0x1300C8096#define AQM_ACTIVITY_STAT_HI 0x1300C8897#define AQM_Q_CMD_PROCX(x) (0x1301000 + ((x) * 0x8))98#define AQM_PERF_CTL_LO 0x130140099#define AQM_PERF_CTL_HI 0x1301408100#define AQM_PERF_CNT 0x1301410101 102#define AQMQ_DRBLX(x) (0x20000 + ((x) * 0x40000))103#define AQMQ_QSZX(x) (0x20008 + ((x) * 0x40000))104#define AQMQ_BADRX(x) (0x20010 + ((x) * 0x40000))105#define AQMQ_NXT_CMDX(x) (0x20018 + ((x) * 0x40000))106#define AQMQ_CMD_CNTX(x) (0x20020 + ((x) * 0x40000))107#define AQMQ_CMP_THRX(x) (0x20028 + ((x) * 0x40000))108#define AQMQ_CMP_CNTX(x) (0x20030 + ((x) * 0x40000))109#define AQMQ_TIM_LDX(x) (0x20038 + ((x) * 0x40000))110#define AQMQ_TIMERX(x) (0x20040 + ((x) * 0x40000))111#define AQMQ_ENX(x) (0x20048 + ((x) * 0x40000))112#define AQMQ_ACTIVITY_STATX(x) (0x20050 + ((x) * 0x40000))113#define AQM_VF_CMP_STATX(x) (0x28000 + ((x) * 0x40000))114 115/* NPS core registers */116#define NPS_CORE_GBL_VFCFG 0x1000000117#define NPS_CORE_CONTROL 0x1000008118#define NPS_CORE_INT_ACTIVE 0x1000080119#define NPS_CORE_INT 0x10000A0120#define NPS_CORE_INT_ENA_W1S 0x10000B8121#define NPS_STATS_PKT_DMA_RD_CNT 0x1000180122#define NPS_STATS_PKT_DMA_WR_CNT 0x1000190123 124/* NPS packet registers */125#define NPS_PKT_INT 0x1040018126#define NPS_PKT_MBOX_INT_LO 0x1040020127#define NPS_PKT_MBOX_INT_LO_ENA_W1C 0x1040030128#define NPS_PKT_MBOX_INT_LO_ENA_W1S 0x1040038129#define NPS_PKT_MBOX_INT_HI 0x1040040130#define NPS_PKT_MBOX_INT_HI_ENA_W1C 0x1040050131#define NPS_PKT_MBOX_INT_HI_ENA_W1S 0x1040058132#define NPS_PKT_IN_RERR_HI 0x1040108133#define NPS_PKT_IN_RERR_HI_ENA_W1S 0x1040120134#define NPS_PKT_IN_RERR_LO 0x1040128135#define NPS_PKT_IN_RERR_LO_ENA_W1S 0x1040140136#define NPS_PKT_IN_ERR_TYPE 0x1040148137#define NPS_PKT_IN_ERR_TYPE_ENA_W1S 0x1040160138#define NPS_PKT_IN_INSTR_CTLX(_i) (0x10060 + ((_i) * 0x40000))139#define NPS_PKT_IN_INSTR_BADDRX(_i) (0x10068 + ((_i) * 0x40000))140#define NPS_PKT_IN_INSTR_RSIZEX(_i) (0x10070 + ((_i) * 0x40000))141#define NPS_PKT_IN_DONE_CNTSX(_i) (0x10080 + ((_i) * 0x40000))142#define NPS_PKT_IN_INSTR_BAOFF_DBELLX(_i) (0x10078 + ((_i) * 0x40000))143#define NPS_PKT_IN_INT_LEVELSX(_i) (0x10088 + ((_i) * 0x40000))144 145#define NPS_PKT_SLC_RERR_HI 0x1040208146#define NPS_PKT_SLC_RERR_HI_ENA_W1S 0x1040220147#define NPS_PKT_SLC_RERR_LO 0x1040228148#define NPS_PKT_SLC_RERR_LO_ENA_W1S 0x1040240149#define NPS_PKT_SLC_ERR_TYPE 0x1040248150#define NPS_PKT_SLC_ERR_TYPE_ENA_W1S 0x1040260151/* Mailbox PF->VF PF Accessible Data registers */152#define NPS_PKT_MBOX_PF_VF_PFDATAX(_i) (0x1040800 + ((_i) * 0x8))153#define NPS_PKT_MBOX_VF_PF_PFDATAX(_i) (0x1040C00 + ((_i) * 0x8))154 155#define NPS_PKT_SLC_CTLX(_i) (0x10000 + ((_i) * 0x40000))156#define NPS_PKT_SLC_CNTSX(_i) (0x10008 + ((_i) * 0x40000))157#define NPS_PKT_SLC_INT_LEVELSX(_i) (0x10010 + ((_i) * 0x40000))158 159/* POM registers */160#define POM_INT_ENA_W1S 0x11C0018161#define POM_GRP_EXECMASKX(_i) (0x11C1100 | ((_i) * 8))162#define POM_INT 0x11C0000163#define POM_PERF_CTL 0x11CC400164 165/* BMI registers */166#define BMI_INT 0x1140000167#define BMI_CTL 0x1140020168#define BMI_INT_ENA_W1S 0x1140018169#define BMI_NPS_PKT_CNT 0x1140070170 171/* EFL registers */172#define EFL_CORE_INT_ENA_W1SX(_i) (0x1240018 + ((_i) * 0x400))173#define EFL_CORE_VF_ERR_INT0X(_i) (0x1240050 + ((_i) * 0x400))174#define EFL_CORE_VF_ERR_INT0_ENA_W1SX(_i) (0x1240068 + ((_i) * 0x400))175#define EFL_CORE_VF_ERR_INT1X(_i) (0x1240070 + ((_i) * 0x400))176#define EFL_CORE_VF_ERR_INT1_ENA_W1SX(_i) (0x1240088 + ((_i) * 0x400))177#define EFL_CORE_SE_ERR_INTX(_i) (0x12400A0 + ((_i) * 0x400))178#define EFL_RNM_CTL_STATUS 0x1241800179#define EFL_CORE_INTX(_i) (0x1240000 + ((_i) * 0x400))180 181/* BMO registers */182#define BMO_CTL2 0x1180028183#define BMO_NPS_SLC_PKT_CNT 0x1180078184 185/* LBC registers */186#define LBC_INT 0x1200000187#define LBC_INVAL_CTL 0x1201010188#define LBC_PLM_VF1_64_INT 0x1202008189#define LBC_INVAL_STATUS 0x1202010190#define LBC_INT_ENA_W1S 0x1203000191#define LBC_PLM_VF1_64_INT_ENA_W1S 0x1205008192#define LBC_PLM_VF65_128_INT 0x1206008193#define LBC_ELM_VF1_64_INT 0x1208000194#define LBC_PLM_VF65_128_INT_ENA_W1S 0x1209008195#define LBC_ELM_VF1_64_INT_ENA_W1S 0x120B000196#define LBC_ELM_VF65_128_INT 0x120C000197#define LBC_ELM_VF65_128_INT_ENA_W1S 0x120F000198 199#define RST_BOOT 0x10C1600200#define FUS_DAT1 0x10C1408201 202/* PEM registers */203#define PEM0_INT 0x1080428204 205/**206 * struct ucd_core_eid_ucode_block_num - Core Eid to Ucode Blk Mapping Registers207 * @ucode_len: Ucode length identifier 32KB or 64KB208 * @ucode_blk: Ucode Block Number209 */210union ucd_core_eid_ucode_block_num {211 u64 value;212 struct {213#if (defined(__BIG_ENDIAN_BITFIELD))214 u64 raz_4_63 : 60;215 u64 ucode_len : 1;216 u64 ucode_blk : 3;217#else218 u64 ucode_blk : 3;219 u64 ucode_len : 1;220 u64 raz_4_63 : 60;221#endif222 };223};224 225/**226 * struct aqm_grp_execmsk_lo - Available AE engines for the group227 * @exec_0_to_39: AE engines 0 to 39 status228 */229union aqm_grp_execmsk_lo {230 u64 value;231 struct {232#if (defined(__BIG_ENDIAN_BITFIELD))233 u64 raz_40_63 : 24;234 u64 exec_0_to_39 : 40;235#else236 u64 exec_0_to_39 : 40;237 u64 raz_40_63 : 24;238#endif239 };240};241 242/**243 * struct aqm_grp_execmsk_hi - Available AE engines for the group244 * @exec_40_to_79: AE engines 40 to 79 status245 */246union aqm_grp_execmsk_hi {247 u64 value;248 struct {249#if (defined(__BIG_ENDIAN_BITFIELD))250 u64 raz_40_63 : 24;251 u64 exec_40_to_79 : 40;252#else253 u64 exec_40_to_79 : 40;254 u64 raz_40_63 : 24;255#endif256 };257};258 259/**260 * struct aqmq_drbl - AQM Queue Doorbell Counter Registers261 * @dbell_count: Doorbell Counter262 */263union aqmq_drbl {264 u64 value;265 struct {266#if (defined(__BIG_ENDIAN_BITFIELD))267 u64 raz_32_63 : 32;268 u64 dbell_count : 32;269#else270 u64 dbell_count : 32;271 u64 raz_32_63 : 32;272#endif273 };274};275 276/**277 * struct aqmq_qsz - AQM Queue Host Queue Size Registers278 * @host_queue_size: Size, in numbers of 'aqmq_command_s' command279 * of the Host Ring.280 */281union aqmq_qsz {282 u64 value;283 struct {284#if (defined(__BIG_ENDIAN_BITFIELD))285 u64 raz_32_63 : 32;286 u64 host_queue_size : 32;287#else288 u64 host_queue_size : 32;289 u64 raz_32_63 : 32;290#endif291 };292};293 294/**295 * struct aqmq_cmp_thr - AQM Queue Commands Completed Threshold Registers296 * @commands_completed_threshold: Count of 'aqmq_command_s' commands executed297 * by AE engines for which completion interrupt is asserted.298 */299union aqmq_cmp_thr {300 u64 value;301 struct {302#if (defined(__BIG_ENDIAN_BITFIELD))303 u64 raz_32_63 : 32;304 u64 commands_completed_threshold : 32;305#else306 u64 commands_completed_threshold : 32;307 u64 raz_32_63 : 32;308#endif309 };310};311 312/**313 * struct aqmq_cmp_cnt - AQM Queue Commands Completed Count Registers314 * @resend: Bit to request completion interrupt Resend.315 * @completion_status: Command completion status of the ring.316 * @commands_completed_count: Count of 'aqmq_command_s' commands executed by317 * AE engines.318 */319union aqmq_cmp_cnt {320 u64 value;321 struct {322#if (defined(__BIG_ENDIAN_BITFIELD))323 u64 raz_34_63 : 30;324 u64 resend : 1;325 u64 completion_status : 1;326 u64 commands_completed_count : 32;327#else328 u64 commands_completed_count : 32;329 u64 completion_status : 1;330 u64 resend : 1;331 u64 raz_34_63 : 30;332#endif333 };334};335 336/**337 * struct aqmq_en - AQM Queue Enable Registers338 * @queue_status: 1 = AQMQ is enabled, 0 = AQMQ is disabled339 */340union aqmq_en {341 u64 value;342 struct {343#if (defined(__BIG_ENDIAN_BITFIELD))344 u64 raz_1_63 : 63;345 u64 queue_enable : 1;346#else347 u64 queue_enable : 1;348 u64 raz_1_63 : 63;349#endif350 };351};352 353/**354 * struct aqmq_activity_stat - AQM Queue Activity Status Registers355 * @queue_active: 1 = AQMQ is active, 0 = AQMQ is quiescent356 */357union aqmq_activity_stat {358 u64 value;359 struct {360#if (defined(__BIG_ENDIAN_BITFIELD))361 u64 raz_1_63 : 63;362 u64 queue_active : 1;363#else364 u64 queue_active : 1;365 u64 raz_1_63 : 63;366#endif367 };368};369 370/**371 * struct emu_fuse_map - EMU Fuse Map Registers372 * @ae_fuse: Fuse settings for AE 19..0373 * @se_fuse: Fuse settings for SE 15..0374 *375 * A set bit indicates the unit is fuse disabled.376 */377union emu_fuse_map {378 u64 value;379 struct {380#if (defined(__BIG_ENDIAN_BITFIELD))381 u64 valid : 1;382 u64 raz_52_62 : 11;383 u64 ae_fuse : 20;384 u64 raz_16_31 : 16;385 u64 se_fuse : 16;386#else387 u64 se_fuse : 16;388 u64 raz_16_31 : 16;389 u64 ae_fuse : 20;390 u64 raz_52_62 : 11;391 u64 valid : 1;392#endif393 } s;394};395 396/**397 * struct emu_se_enable - Symmetric Engine Enable Registers398 * @enable: Individual enables for each of the clusters399 * 16 symmetric engines.400 */401union emu_se_enable {402 u64 value;403 struct {404#if (defined(__BIG_ENDIAN_BITFIELD))405 u64 raz : 48;406 u64 enable : 16;407#else408 u64 enable : 16;409 u64 raz : 48;410#endif411 } s;412};413 414/**415 * struct emu_ae_enable - EMU Asymmetric engines.416 * @enable: Individual enables for each of the cluster's417 * 20 Asymmetric Engines.418 */419union emu_ae_enable {420 u64 value;421 struct {422#if (defined(__BIG_ENDIAN_BITFIELD))423 u64 raz : 44;424 u64 enable : 20;425#else426 u64 enable : 20;427 u64 raz : 44;428#endif429 } s;430};431 432/**433 * struct emu_wd_int_ena_w1s - EMU Interrupt Enable Registers434 * @ae_wd: Reads or sets enable for EMU(0..3)_WD_INT[AE_WD]435 * @se_wd: Reads or sets enable for EMU(0..3)_WD_INT[SE_WD]436 */437union emu_wd_int_ena_w1s {438 u64 value;439 struct {440#if (defined(__BIG_ENDIAN_BITFIELD))441 u64 raz2 : 12;442 u64 ae_wd : 20;443 u64 raz1 : 16;444 u64 se_wd : 16;445#else446 u64 se_wd : 16;447 u64 raz1 : 16;448 u64 ae_wd : 20;449 u64 raz2 : 12;450#endif451 } s;452};453 454/**455 * struct emu_ge_int_ena_w1s - EMU Interrupt Enable set registers456 * @ae_ge: Reads or sets enable for EMU(0..3)_GE_INT[AE_GE]457 * @se_ge: Reads or sets enable for EMU(0..3)_GE_INT[SE_GE]458 */459union emu_ge_int_ena_w1s {460 u64 value;461 struct {462#if (defined(__BIG_ENDIAN_BITFIELD))463 u64 raz_52_63 : 12;464 u64 ae_ge : 20;465 u64 raz_16_31: 16;466 u64 se_ge : 16;467#else468 u64 se_ge : 16;469 u64 raz_16_31: 16;470 u64 ae_ge : 20;471 u64 raz_52_63 : 12;472#endif473 } s;474};475 476/**477 * struct nps_pkt_slc_ctl - Solicited Packet Out Control Registers478 * @rh: Indicates whether to remove or include the response header479 * 1 = Include, 0 = Remove480 * @z: If set, 8 trailing 0x00 bytes will be added to the end of the481 * outgoing packet.482 * @enb: Enable for this port.483 */484union nps_pkt_slc_ctl {485 u64 value;486 struct {487#if defined(__BIG_ENDIAN_BITFIELD)488 u64 raz : 61;489 u64 rh : 1;490 u64 z : 1;491 u64 enb : 1;492#else493 u64 enb : 1;494 u64 z : 1;495 u64 rh : 1;496 u64 raz : 61;497#endif498 } s;499};500 501/**502 * struct nps_pkt_slc_cnts - Solicited Packet Out Count Registers503 * @slc_int: Returns a 1 when:504 * NPS_PKT_SLC(i)_CNTS[CNT] > NPS_PKT_SLC(i)_INT_LEVELS[CNT], or505 * NPS_PKT_SLC(i)_CNTS[TIMER] > NPS_PKT_SLC(i)_INT_LEVELS[TIMET].506 * To clear the bit, the CNTS register must be written to clear.507 * @in_int: Returns a 1 when:508 * NPS_PKT_IN(i)_DONE_CNTS[CNT] > NPS_PKT_IN(i)_INT_LEVELS[CNT].509 * To clear the bit, the DONE_CNTS register must be written to clear.510 * @mbox_int: Returns a 1 when:511 * NPS_PKT_MBOX_PF_VF(i)_INT[INTR] is set. To clear the bit,512 * write NPS_PKT_MBOX_PF_VF(i)_INT[INTR] with 1.513 * @timer: Timer, incremented every 2048 coprocessor clock cycles514 * when [CNT] is not zero. The hardware clears both [TIMER] and515 * [INT] when [CNT] goes to 0.516 * @cnt: Packet counter. Hardware adds to [CNT] as it sends packets out.517 * On a write to this CSR, hardware subtracts the amount written to the518 * [CNT] field from [CNT].519 */520union nps_pkt_slc_cnts {521 u64 value;522 struct {523#if defined(__BIG_ENDIAN_BITFIELD)524 u64 slc_int : 1;525 u64 uns_int : 1;526 u64 in_int : 1;527 u64 mbox_int : 1;528 u64 resend : 1;529 u64 raz : 5;530 u64 timer : 22;531 u64 cnt : 32;532#else533 u64 cnt : 32;534 u64 timer : 22;535 u64 raz : 5;536 u64 resend : 1;537 u64 mbox_int : 1;538 u64 in_int : 1;539 u64 uns_int : 1;540 u64 slc_int : 1;541#endif542 } s;543};544 545/**546 * struct nps_pkt_slc_int_levels - Solicited Packet Out Interrupt Levels547 * Registers.548 * @bmode: Determines whether NPS_PKT_SLC_CNTS[CNT] is a byte or549 * packet counter.550 * @timet: Output port counter time interrupt threshold.551 * @cnt: Output port counter interrupt threshold.552 */553union nps_pkt_slc_int_levels {554 u64 value;555 struct {556#if defined(__BIG_ENDIAN_BITFIELD)557 u64 bmode : 1;558 u64 raz : 9;559 u64 timet : 22;560 u64 cnt : 32;561#else562 u64 cnt : 32;563 u64 timet : 22;564 u64 raz : 9;565 u64 bmode : 1;566#endif567 } s;568};569 570/**571 * struct nps_pkt_inst - NPS Packet Interrupt Register572 * @in_err: Set when any NPS_PKT_IN_RERR_HI/LO bit and573 * corresponding NPS_PKT_IN_RERR_*_ENA_* bit are bot set.574 * @uns_err: Set when any NSP_PKT_UNS_RERR_HI/LO bit and575 * corresponding NPS_PKT_UNS_RERR_*_ENA_* bit are both set.576 * @slc_er: Set when any NSP_PKT_SLC_RERR_HI/LO bit and577 * corresponding NPS_PKT_SLC_RERR_*_ENA_* bit are both set.578 */579union nps_pkt_int {580 u64 value;581 struct {582#if defined(__BIG_ENDIAN_BITFIELD)583 u64 raz : 54;584 u64 uns_wto : 1;585 u64 in_err : 1;586 u64 uns_err : 1;587 u64 slc_err : 1;588 u64 in_dbe : 1;589 u64 in_sbe : 1;590 u64 uns_dbe : 1;591 u64 uns_sbe : 1;592 u64 slc_dbe : 1;593 u64 slc_sbe : 1;594#else595 u64 slc_sbe : 1;596 u64 slc_dbe : 1;597 u64 uns_sbe : 1;598 u64 uns_dbe : 1;599 u64 in_sbe : 1;600 u64 in_dbe : 1;601 u64 slc_err : 1;602 u64 uns_err : 1;603 u64 in_err : 1;604 u64 uns_wto : 1;605 u64 raz : 54;606#endif607 } s;608};609 610/**611 * struct nps_pkt_in_done_cnts - Input instruction ring counts registers612 * @slc_cnt: Returns a 1 when:613 * NPS_PKT_SLC(i)_CNTS[CNT] > NPS_PKT_SLC(i)_INT_LEVELS[CNT], or614 * NPS_PKT_SLC(i)_CNTS[TIMER] > NPS_PKT_SCL(i)_INT_LEVELS[TIMET]615 * To clear the bit, the CNTS register must be616 * written to clear the underlying condition617 * @uns_int: Return a 1 when:618 * NPS_PKT_UNS(i)_CNTS[CNT] > NPS_PKT_UNS(i)_INT_LEVELS[CNT], or619 * NPS_PKT_UNS(i)_CNTS[TIMER] > NPS_PKT_UNS(i)_INT_LEVELS[TIMET]620 * To clear the bit, the CNTS register must be621 * written to clear the underlying condition622 * @in_int: Returns a 1 when:623 * NPS_PKT_IN(i)_DONE_CNTS[CNT] > NPS_PKT_IN(i)_INT_LEVELS[CNT]624 * To clear the bit, the DONE_CNTS register625 * must be written to clear the underlying condition626 * @mbox_int: Returns a 1 when:627 * NPS_PKT_MBOX_PF_VF(i)_INT[INTR] is set.628 * To clear the bit, write NPS_PKT_MBOX_PF_VF(i)_INT[INTR]629 * with 1.630 * @resend: A write of 1 will resend an MSI-X interrupt message if any631 * of the following conditions are true for this ring "i".632 * NPS_PKT_SLC(i)_CNTS[CNT] > NPS_PKT_SLC(i)_INT_LEVELS[CNT]633 * NPS_PKT_SLC(i)_CNTS[TIMER] > NPS_PKT_SLC(i)_INT_LEVELS[TIMET]634 * NPS_PKT_UNS(i)_CNTS[CNT] > NPS_PKT_UNS(i)_INT_LEVELS[CNT]635 * NPS_PKT_UNS(i)_CNTS[TIMER] > NPS_PKT_UNS(i)_INT_LEVELS[TIMET]636 * NPS_PKT_IN(i)_DONE_CNTS[CNT] > NPS_PKT_IN(i)_INT_LEVELS[CNT]637 * NPS_PKT_MBOX_PF_VF(i)_INT[INTR] is set638 * @cnt: Packet counter. Hardware adds to [CNT] as it reads639 * packets. On a write to this CSR, hardware substracts the640 * amount written to the [CNT] field from [CNT], which will641 * clear PKT_IN(i)_INT_STATUS[INTR] if [CNT] becomes <=642 * NPS_PKT_IN(i)_INT_LEVELS[CNT]. This register should be643 * cleared before enabling a ring by reading the current644 * value and writing it back.645 */646union nps_pkt_in_done_cnts {647 u64 value;648 struct {649#if defined(__BIG_ENDIAN_BITFIELD)650 u64 slc_int : 1;651 u64 uns_int : 1;652 u64 in_int : 1;653 u64 mbox_int : 1;654 u64 resend : 1;655 u64 raz : 27;656 u64 cnt : 32;657#else658 u64 cnt : 32;659 u64 raz : 27;660 u64 resend : 1;661 u64 mbox_int : 1;662 u64 in_int : 1;663 u64 uns_int : 1;664 u64 slc_int : 1;665#endif666 } s;667};668 669/**670 * struct nps_pkt_in_instr_ctl - Input Instruction Ring Control Registers.671 * @is64b: If 1, the ring uses 64-byte instructions. If 0, the672 * ring uses 32-byte instructions.673 * @enb: Enable for the input ring.674 */675union nps_pkt_in_instr_ctl {676 u64 value;677 struct {678#if (defined(__BIG_ENDIAN_BITFIELD))679 u64 raz : 62;680 u64 is64b : 1;681 u64 enb : 1;682#else683 u64 enb : 1;684 u64 is64b : 1;685 u64 raz : 62;686#endif687 } s;688};689 690/**691 * struct nps_pkt_in_instr_rsize - Input instruction ring size registers692 * @rsize: Ring size (number of instructions)693 */694union nps_pkt_in_instr_rsize {695 u64 value;696 struct {697#if (defined(__BIG_ENDIAN_BITFIELD))698 u64 raz : 32;699 u64 rsize : 32;700#else701 u64 rsize : 32;702 u64 raz : 32;703#endif704 } s;705};706 707/**708 * struct nps_pkt_in_instr_baoff_dbell - Input instruction ring709 * base address offset and doorbell registers710 * @aoff: Address offset. The offset from the NPS_PKT_IN_INSTR_BADDR711 * where the next pointer is read.712 * @dbell: Pointer list doorbell count. Write operations to this field713 * increments the present value here. Read operations return the714 * present value.715 */716union nps_pkt_in_instr_baoff_dbell {717 u64 value;718 struct {719#if (defined(__BIG_ENDIAN_BITFIELD))720 u64 aoff : 32;721 u64 dbell : 32;722#else723 u64 dbell : 32;724 u64 aoff : 32;725#endif726 } s;727};728 729/**730 * struct nps_core_int_ena_w1s - NPS core interrupt enable set register731 * @host_nps_wr_err: Reads or sets enable for732 * NPS_CORE_INT[HOST_NPS_WR_ERR].733 * @npco_dma_malform: Reads or sets enable for734 * NPS_CORE_INT[NPCO_DMA_MALFORM].735 * @exec_wr_timeout: Reads or sets enable for736 * NPS_CORE_INT[EXEC_WR_TIMEOUT].737 * @host_wr_timeout: Reads or sets enable for738 * NPS_CORE_INT[HOST_WR_TIMEOUT].739 * @host_wr_err: Reads or sets enable for740 * NPS_CORE_INT[HOST_WR_ERR]741 */742union nps_core_int_ena_w1s {743 u64 value;744 struct {745#if (defined(__BIG_ENDIAN_BITFIELD))746 u64 raz4 : 55;747 u64 host_nps_wr_err : 1;748 u64 npco_dma_malform : 1;749 u64 exec_wr_timeout : 1;750 u64 host_wr_timeout : 1;751 u64 host_wr_err : 1;752 u64 raz3 : 1;753 u64 raz2 : 1;754 u64 raz1 : 1;755 u64 raz0 : 1;756#else757 u64 raz0 : 1;758 u64 raz1 : 1;759 u64 raz2 : 1;760 u64 raz3 : 1;761 u64 host_wr_err : 1;762 u64 host_wr_timeout : 1;763 u64 exec_wr_timeout : 1;764 u64 npco_dma_malform : 1;765 u64 host_nps_wr_err : 1;766 u64 raz4 : 55;767#endif768 } s;769};770 771/**772 * struct nps_core_gbl_vfcfg - Global VF Configuration Register.773 * @ilk_disable: When set, this bit indicates that the ILK interface has774 * been disabled.775 * @obaf: BMO allocation control776 * 0 = allocate per queue777 * 1 = allocate per VF778 * @ibaf: BMI allocation control779 * 0 = allocate per queue780 * 1 = allocate per VF781 * @zaf: ZIP allocation control782 * 0 = allocate per queue783 * 1 = allocate per VF784 * @aeaf: AE allocation control785 * 0 = allocate per queue786 * 1 = allocate per VF787 * @seaf: SE allocation control788 * 0 = allocation per queue789 * 1 = allocate per VF790 * @cfg: VF/PF mode.791 */792union nps_core_gbl_vfcfg {793 u64 value;794 struct {795#if (defined(__BIG_ENDIAN_BITFIELD))796 u64 raz :55;797 u64 ilk_disable :1;798 u64 obaf :1;799 u64 ibaf :1;800 u64 zaf :1;801 u64 aeaf :1;802 u64 seaf :1;803 u64 cfg :3;804#else805 u64 cfg :3;806 u64 seaf :1;807 u64 aeaf :1;808 u64 zaf :1;809 u64 ibaf :1;810 u64 obaf :1;811 u64 ilk_disable :1;812 u64 raz :55;813#endif814 } s;815};816 817/**818 * struct nps_core_int_active - NPS Core Interrupt Active Register819 * @resend: Resend MSI-X interrupt if needs to handle interrupts820 * Sofware can set this bit and then exit the ISR.821 * @ocla: Set when any OCLA(0)_INT and corresponding OCLA(0_INT_ENA_W1C822 * bit are set823 * @mbox: Set when any NPS_PKT_MBOX_INT_LO/HI and corresponding824 * NPS_PKT_MBOX_INT_LO_ENA_W1C/HI_ENA_W1C bits are set825 * @emu: bit i is set in [EMU] when any EMU(i)_INT bit is set826 * @bmo: Set when any BMO_INT bit is set827 * @bmi: Set when any BMI_INT bit is set or when any non-RO828 * BMI_INT and corresponding BMI_INT_ENA_W1C bits are both set829 * @aqm: Set when any AQM_INT bit is set830 * @zqm: Set when any ZQM_INT bit is set831 * @efl: Set when any EFL_INT RO bit is set or when any non-RO EFL_INT832 * and corresponding EFL_INT_ENA_W1C bits are both set833 * @ilk: Set when any ILK_INT bit is set834 * @lbc: Set when any LBC_INT RO bit is set or when any non-RO LBC_INT835 * and corresponding LBC_INT_ENA_W1C bits are bot set836 * @pem: Set when any PEM(0)_INT RO bit is set or when any non-RO837 * PEM(0)_INT and corresponding PEM(0)_INT_ENA_W1C bit are both set838 * @ucd: Set when any UCD_INT bit is set839 * @zctl: Set when any ZIP_INT RO bit is set or when any non-RO ZIP_INT840 * and corresponding ZIP_INT_ENA_W1C bits are both set841 * @lbm: Set when any LBM_INT bit is set842 * @nps_pkt: Set when any NPS_PKT_INT bit is set843 * @nps_core: Set when any NPS_CORE_INT RO bit is set or when non-RO844 * NPS_CORE_INT and corresponding NSP_CORE_INT_ENA_W1C bits are both set845 */846union nps_core_int_active {847 u64 value;848 struct {849#if (defined(__BIG_ENDIAN_BITFIELD))850 u64 resend : 1;851 u64 raz : 43;852 u64 ocla : 1;853 u64 mbox : 1;854 u64 emu : 4;855 u64 bmo : 1;856 u64 bmi : 1;857 u64 aqm : 1;858 u64 zqm : 1;859 u64 efl : 1;860 u64 ilk : 1;861 u64 lbc : 1;862 u64 pem : 1;863 u64 pom : 1;864 u64 ucd : 1;865 u64 zctl : 1;866 u64 lbm : 1;867 u64 nps_pkt : 1;868 u64 nps_core : 1;869#else870 u64 nps_core : 1;871 u64 nps_pkt : 1;872 u64 lbm : 1;873 u64 zctl: 1;874 u64 ucd : 1;875 u64 pom : 1;876 u64 pem : 1;877 u64 lbc : 1;878 u64 ilk : 1;879 u64 efl : 1;880 u64 zqm : 1;881 u64 aqm : 1;882 u64 bmi : 1;883 u64 bmo : 1;884 u64 emu : 4;885 u64 mbox : 1;886 u64 ocla : 1;887 u64 raz : 43;888 u64 resend : 1;889#endif890 } s;891};892 893/**894 * struct efl_core_int - EFL Interrupt Registers895 * @epci_decode_err: EPCI decoded a transacation that was unknown896 * This error should only occurred when there is a micrcode/SE error897 * and should be considered fatal898 * @ae_err: An AE uncorrectable error occurred.899 * See EFL_CORE(0..3)_AE_ERR_INT900 * @se_err: An SE uncorrectable error occurred.901 * See EFL_CORE(0..3)_SE_ERR_INT902 * @dbe: Double-bit error occurred in EFL903 * @sbe: Single-bit error occurred in EFL904 * @d_left: Asserted when new POM-Header-BMI-data is905 * being sent to an Exec, and that Exec has Not read all BMI906 * data associated with the previous POM header907 * @len_ovr: Asserted when an Exec-Read is issued that is more than908 * 14 greater in length that the BMI data left to be read909 */910union efl_core_int {911 u64 value;912 struct {913#if (defined(__BIG_ENDIAN_BITFIELD))914 u64 raz : 57;915 u64 epci_decode_err : 1;916 u64 ae_err : 1;917 u64 se_err : 1;918 u64 dbe : 1;919 u64 sbe : 1;920 u64 d_left : 1;921 u64 len_ovr : 1;922#else923 u64 len_ovr : 1;924 u64 d_left : 1;925 u64 sbe : 1;926 u64 dbe : 1;927 u64 se_err : 1;928 u64 ae_err : 1;929 u64 epci_decode_err : 1;930 u64 raz : 57;931#endif932 } s;933};934 935/**936 * struct efl_core_int_ena_w1s - EFL core interrupt enable set register937 * @epci_decode_err: Reads or sets enable for938 * EFL_CORE(0..3)_INT[EPCI_DECODE_ERR].939 * @d_left: Reads or sets enable for940 * EFL_CORE(0..3)_INT[D_LEFT].941 * @len_ovr: Reads or sets enable for942 * EFL_CORE(0..3)_INT[LEN_OVR].943 */944union efl_core_int_ena_w1s {945 u64 value;946 struct {947#if (defined(__BIG_ENDIAN_BITFIELD))948 u64 raz_7_63 : 57;949 u64 epci_decode_err : 1;950 u64 raz_2_5 : 4;951 u64 d_left : 1;952 u64 len_ovr : 1;953#else954 u64 len_ovr : 1;955 u64 d_left : 1;956 u64 raz_2_5 : 4;957 u64 epci_decode_err : 1;958 u64 raz_7_63 : 57;959#endif960 } s;961};962 963/**964 * struct efl_rnm_ctl_status - RNM Control and Status Register965 * @ent_sel: Select input to RNM FIFO966 * @exp_ent: Exported entropy enable for random number generator967 * @rng_rst: Reset to RNG. Setting this bit to 1 cancels the generation968 * of the current random number.969 * @rnm_rst: Reset the RNM. Setting this bit to 1 clears all sorted numbers970 * in the random number memory.971 * @rng_en: Enabled the output of the RNG.972 * @ent_en: Entropy enable for random number generator.973 */974union efl_rnm_ctl_status {975 u64 value;976 struct {977#if (defined(__BIG_ENDIAN_BITFIELD))978 u64 raz_9_63 : 55;979 u64 ent_sel : 4;980 u64 exp_ent : 1;981 u64 rng_rst : 1;982 u64 rnm_rst : 1;983 u64 rng_en : 1;984 u64 ent_en : 1;985#else986 u64 ent_en : 1;987 u64 rng_en : 1;988 u64 rnm_rst : 1;989 u64 rng_rst : 1;990 u64 exp_ent : 1;991 u64 ent_sel : 4;992 u64 raz_9_63 : 55;993#endif994 } s;995};996 997/**998 * struct bmi_ctl - BMI control register999 * @ilk_hdrq_thrsh: Maximum number of header queue locations1000 * that ILK packets may consume. When the threshold is1001 * exceeded ILK_XOFF is sent to the BMI_X2P_ARB.1002 * @nps_hdrq_thrsh: Maximum number of header queue locations1003 * that NPS packets may consume. When the threshold is1004 * exceeded NPS_XOFF is sent to the BMI_X2P_ARB.1005 * @totl_hdrq_thrsh: Maximum number of header queue locations1006 * that the sum of ILK and NPS packets may consume.1007 * @ilk_free_thrsh: Maximum number of buffers that ILK packet1008 * flows may consume before ILK_XOFF is sent to the BMI_X2P_ARB.1009 * @nps_free_thrsh: Maximum number of buffers that NPS packet1010 * flows may consume before NPS XOFF is sent to the BMI_X2p_ARB.1011 * @totl_free_thrsh: Maximum number of buffers that bot ILK and NPS1012 * packet flows may consume before both NPS_XOFF and ILK_XOFF1013 * are asserted to the BMI_X2P_ARB.1014 * @max_pkt_len: Maximum packet length, integral number of 256B1015 * buffers.1016 */1017union bmi_ctl {1018 u64 value;1019 struct {1020#if (defined(__BIG_ENDIAN_BITFIELD))1021 u64 raz_56_63 : 8;1022 u64 ilk_hdrq_thrsh : 8;1023 u64 nps_hdrq_thrsh : 8;1024 u64 totl_hdrq_thrsh : 8;1025 u64 ilk_free_thrsh : 8;1026 u64 nps_free_thrsh : 8;1027 u64 totl_free_thrsh : 8;1028 u64 max_pkt_len : 8;1029#else1030 u64 max_pkt_len : 8;1031 u64 totl_free_thrsh : 8;1032 u64 nps_free_thrsh : 8;1033 u64 ilk_free_thrsh : 8;1034 u64 totl_hdrq_thrsh : 8;1035 u64 nps_hdrq_thrsh : 8;1036 u64 ilk_hdrq_thrsh : 8;1037 u64 raz_56_63 : 8;1038#endif1039 } s;1040};1041 1042/**1043 * struct bmi_int_ena_w1s - BMI interrupt enable set register1044 * @ilk_req_oflw: Reads or sets enable for1045 * BMI_INT[ILK_REQ_OFLW].1046 * @nps_req_oflw: Reads or sets enable for1047 * BMI_INT[NPS_REQ_OFLW].1048 * @fpf_undrrn: Reads or sets enable for1049 * BMI_INT[FPF_UNDRRN].1050 * @eop_err_ilk: Reads or sets enable for1051 * BMI_INT[EOP_ERR_ILK].1052 * @eop_err_nps: Reads or sets enable for1053 * BMI_INT[EOP_ERR_NPS].1054 * @sop_err_ilk: Reads or sets enable for1055 * BMI_INT[SOP_ERR_ILK].1056 * @sop_err_nps: Reads or sets enable for1057 * BMI_INT[SOP_ERR_NPS].1058 * @pkt_rcv_err_ilk: Reads or sets enable for1059 * BMI_INT[PKT_RCV_ERR_ILK].1060 * @pkt_rcv_err_nps: Reads or sets enable for1061 * BMI_INT[PKT_RCV_ERR_NPS].1062 * @max_len_err_ilk: Reads or sets enable for1063 * BMI_INT[MAX_LEN_ERR_ILK].1064 * @max_len_err_nps: Reads or sets enable for1065 * BMI_INT[MAX_LEN_ERR_NPS].1066 */1067union bmi_int_ena_w1s {1068 u64 value;1069 struct {1070#if (defined(__BIG_ENDIAN_BITFIELD))1071 u64 raz_13_63 : 51;1072 u64 ilk_req_oflw : 1;1073 u64 nps_req_oflw : 1;1074 u64 raz_10 : 1;1075 u64 raz_9 : 1;1076 u64 fpf_undrrn : 1;1077 u64 eop_err_ilk : 1;1078 u64 eop_err_nps : 1;1079 u64 sop_err_ilk : 1;1080 u64 sop_err_nps : 1;1081 u64 pkt_rcv_err_ilk : 1;1082 u64 pkt_rcv_err_nps : 1;1083 u64 max_len_err_ilk : 1;1084 u64 max_len_err_nps : 1;1085#else1086 u64 max_len_err_nps : 1;1087 u64 max_len_err_ilk : 1;1088 u64 pkt_rcv_err_nps : 1;1089 u64 pkt_rcv_err_ilk : 1;1090 u64 sop_err_nps : 1;1091 u64 sop_err_ilk : 1;1092 u64 eop_err_nps : 1;1093 u64 eop_err_ilk : 1;1094 u64 fpf_undrrn : 1;1095 u64 raz_9 : 1;1096 u64 raz_10 : 1;1097 u64 nps_req_oflw : 1;1098 u64 ilk_req_oflw : 1;1099 u64 raz_13_63 : 51;1100#endif1101 } s;1102};1103 1104/**1105 * struct bmo_ctl2 - BMO Control2 Register1106 * @arb_sel: Determines P2X Arbitration1107 * @ilk_buf_thrsh: Maximum number of buffers that the1108 * ILK packet flows may consume before ILK XOFF is1109 * asserted to the POM.1110 * @nps_slc_buf_thrsh: Maximum number of buffers that the1111 * NPS_SLC packet flow may consume before NPS_SLC XOFF is1112 * asserted to the POM.1113 * @nps_uns_buf_thrsh: Maximum number of buffers that the1114 * NPS_UNS packet flow may consume before NPS_UNS XOFF is1115 * asserted to the POM.1116 * @totl_buf_thrsh: Maximum number of buffers that ILK, NPS_UNS and1117 * NPS_SLC packet flows may consume before NPS_UNS XOFF, NSP_SLC and1118 * ILK_XOFF are all asserted POM.1119 */1120union bmo_ctl2 {1121 u64 value;1122 struct {1123#if (defined(__BIG_ENDIAN_BITFIELD))1124 u64 arb_sel : 1;1125 u64 raz_32_62 : 31;1126 u64 ilk_buf_thrsh : 8;1127 u64 nps_slc_buf_thrsh : 8;1128 u64 nps_uns_buf_thrsh : 8;1129 u64 totl_buf_thrsh : 8;1130#else1131 u64 totl_buf_thrsh : 8;1132 u64 nps_uns_buf_thrsh : 8;1133 u64 nps_slc_buf_thrsh : 8;1134 u64 ilk_buf_thrsh : 8;1135 u64 raz_32_62 : 31;1136 u64 arb_sel : 1;1137#endif1138 } s;1139};1140 1141/**1142 * struct pom_int_ena_w1s - POM interrupt enable set register1143 * @illegal_intf: Reads or sets enable for POM_INT[ILLEGAL_INTF].1144 * @illegal_dport: Reads or sets enable for POM_INT[ILLEGAL_DPORT].1145 */1146union pom_int_ena_w1s {1147 u64 value;1148 struct {1149#if (defined(__BIG_ENDIAN_BITFIELD))1150 u64 raz2 : 60;1151 u64 illegal_intf : 1;1152 u64 illegal_dport : 1;1153 u64 raz1 : 1;1154 u64 raz0 : 1;1155#else1156 u64 raz0 : 1;1157 u64 raz1 : 1;1158 u64 illegal_dport : 1;1159 u64 illegal_intf : 1;1160 u64 raz2 : 60;1161#endif1162 } s;1163};1164 1165/**1166 * struct lbc_inval_ctl - LBC invalidation control register1167 * @wait_timer: Wait timer for wait state. [WAIT_TIMER] must1168 * always be written with its reset value.1169 * @cam_inval_start: Software should write [CAM_INVAL_START]=11170 * to initiate an LBC cache invalidation. After this, software1171 * should read LBC_INVAL_STATUS until LBC_INVAL_STATUS[DONE] is set.1172 * LBC hardware clears [CAVM_INVAL_START] before software can1173 * observed LBC_INVAL_STATUS[DONE] to be set1174 */1175union lbc_inval_ctl {1176 u64 value;1177 struct {1178#if (defined(__BIG_ENDIAN_BITFIELD))1179 u64 raz2 : 48;1180 u64 wait_timer : 8;1181 u64 raz1 : 6;1182 u64 cam_inval_start : 1;1183 u64 raz0 : 1;1184#else1185 u64 raz0 : 1;1186 u64 cam_inval_start : 1;1187 u64 raz1 : 6;1188 u64 wait_timer : 8;1189 u64 raz2 : 48;1190#endif1191 } s;1192};1193 1194/**1195 * struct lbc_int_ena_w1s - LBC interrupt enable set register1196 * @cam_hard_err: Reads or sets enable for LBC_INT[CAM_HARD_ERR].1197 * @cam_inval_abort: Reads or sets enable for LBC_INT[CAM_INVAL_ABORT].1198 * @over_fetch_err: Reads or sets enable for LBC_INT[OVER_FETCH_ERR].1199 * @cache_line_to_err: Reads or sets enable for1200 * LBC_INT[CACHE_LINE_TO_ERR].1201 * @cam_soft_err: Reads or sets enable for1202 * LBC_INT[CAM_SOFT_ERR].1203 * @dma_rd_err: Reads or sets enable for1204 * LBC_INT[DMA_RD_ERR].1205 */1206union lbc_int_ena_w1s {1207 u64 value;1208 struct {1209#if (defined(__BIG_ENDIAN_BITFIELD))1210 u64 raz_10_63 : 54;1211 u64 cam_hard_err : 1;1212 u64 cam_inval_abort : 1;1213 u64 over_fetch_err : 1;1214 u64 cache_line_to_err : 1;1215 u64 raz_2_5 : 4;1216 u64 cam_soft_err : 1;1217 u64 dma_rd_err : 1;1218#else1219 u64 dma_rd_err : 1;1220 u64 cam_soft_err : 1;1221 u64 raz_2_5 : 4;1222 u64 cache_line_to_err : 1;1223 u64 over_fetch_err : 1;1224 u64 cam_inval_abort : 1;1225 u64 cam_hard_err : 1;1226 u64 raz_10_63 : 54;1227#endif1228 } s;1229};1230 1231/**1232 * struct lbc_int - LBC interrupt summary register1233 * @cam_hard_err: indicates a fatal hardware error.1234 * It requires system reset.1235 * When [CAM_HARD_ERR] is set, LBC stops logging any new information in1236 * LBC_POM_MISS_INFO_LOG,1237 * LBC_POM_MISS_ADDR_LOG,1238 * LBC_EFL_MISS_INFO_LOG, and1239 * LBC_EFL_MISS_ADDR_LOG.1240 * Software should sample them.1241 * @cam_inval_abort: indicates a fatal hardware error.1242 * System reset is required.1243 * @over_fetch_err: indicates a fatal hardware error1244 * System reset is required1245 * @cache_line_to_err: is a debug feature.1246 * This timeout interrupt bit tells the software that1247 * a cacheline in LBC has non-zero usage and the context1248 * has not been used for greater than the1249 * LBC_TO_CNT[TO_CNT] time interval.1250 * @sbe: Memory SBE error. This is recoverable via ECC.1251 * See LBC_ECC_INT for more details.1252 * @dbe: Memory DBE error. This is a fatal and requires a1253 * system reset.1254 * @pref_dat_len_mismatch_err: Summary bit for context length1255 * mismatch errors.1256 * @rd_dat_len_mismatch_err: Summary bit for SE read data length1257 * greater than data prefect length errors.1258 * @cam_soft_err: is recoverable. Software must complete a1259 * LBC_INVAL_CTL[CAM_INVAL_START] invalidation sequence and1260 * then clear [CAM_SOFT_ERR].1261 * @dma_rd_err: A context prefect read of host memory returned with1262 * a read error.1263 */1264union lbc_int {1265 u64 value;1266 struct {1267#if (defined(__BIG_ENDIAN_BITFIELD))1268 u64 raz_10_63 : 54;1269 u64 cam_hard_err : 1;1270 u64 cam_inval_abort : 1;1271 u64 over_fetch_err : 1;1272 u64 cache_line_to_err : 1;1273 u64 sbe : 1;1274 u64 dbe : 1;1275 u64 pref_dat_len_mismatch_err : 1;1276 u64 rd_dat_len_mismatch_err : 1;1277 u64 cam_soft_err : 1;1278 u64 dma_rd_err : 1;1279#else1280 u64 dma_rd_err : 1;1281 u64 cam_soft_err : 1;1282 u64 rd_dat_len_mismatch_err : 1;1283 u64 pref_dat_len_mismatch_err : 1;1284 u64 dbe : 1;1285 u64 sbe : 1;1286 u64 cache_line_to_err : 1;1287 u64 over_fetch_err : 1;1288 u64 cam_inval_abort : 1;1289 u64 cam_hard_err : 1;1290 u64 raz_10_63 : 54;1291#endif1292 } s;1293};1294 1295/**1296 * struct lbc_inval_status: LBC Invalidation status register1297 * @cam_clean_entry_complete_cnt: The number of entries that are1298 * cleaned up successfully.1299 * @cam_clean_entry_cnt: The number of entries that have the CAM1300 * inval command issued.1301 * @cam_inval_state: cam invalidation FSM state1302 * @cam_inval_abort: cam invalidation abort1303 * @cam_rst_rdy: lbc_cam reset ready1304 * @done: LBC clears [DONE] when1305 * LBC_INVAL_CTL[CAM_INVAL_START] is written with a one,1306 * and sets [DONE] when it completes the invalidation1307 * sequence.1308 */1309union lbc_inval_status {1310 u64 value;1311 struct {1312#if (defined(__BIG_ENDIAN_BITFIELD))1313 u64 raz3 : 23;1314 u64 cam_clean_entry_complete_cnt : 9;1315 u64 raz2 : 7;1316 u64 cam_clean_entry_cnt : 9;1317 u64 raz1 : 5;1318 u64 cam_inval_state : 3;1319 u64 raz0 : 5;1320 u64 cam_inval_abort : 1;1321 u64 cam_rst_rdy : 1;1322 u64 done : 1;1323#else1324 u64 done : 1;1325 u64 cam_rst_rdy : 1;1326 u64 cam_inval_abort : 1;1327 u64 raz0 : 5;1328 u64 cam_inval_state : 3;1329 u64 raz1 : 5;1330 u64 cam_clean_entry_cnt : 9;1331 u64 raz2 : 7;1332 u64 cam_clean_entry_complete_cnt : 9;1333 u64 raz3 : 23;1334#endif1335 } s;1336};1337 1338/**1339 * struct rst_boot: RST Boot Register1340 * @jtcsrdis: when set, internal CSR access via JTAG TAP controller1341 * is disabled1342 * @jt_tst_mode: JTAG test mode1343 * @io_supply: I/O power supply setting based on IO_VDD_SELECT pin:1344 * 0x1 = 1.8V1345 * 0x2 = 2.5V1346 * 0x4 = 3.3V1347 * All other values are reserved1348 * @pnr_mul: clock multiplier1349 * @lboot: last boot cause mask, resets only with PLL_DC_OK1350 * @rboot: determines whether core 0 remains in reset after1351 * chip cold or warm or soft reset1352 * @rboot_pin: read only access to REMOTE_BOOT pin1353 */1354union rst_boot {1355 u64 value;1356 struct {1357#if (defined(__BIG_ENDIAN_BITFIELD))1358 u64 raz_63 : 1;1359 u64 jtcsrdis : 1;1360 u64 raz_59_61 : 3;1361 u64 jt_tst_mode : 1;1362 u64 raz_40_57 : 18;1363 u64 io_supply : 3;1364 u64 raz_30_36 : 7;1365 u64 pnr_mul : 6;1366 u64 raz_12_23 : 12;1367 u64 lboot : 10;1368 u64 rboot : 1;1369 u64 rboot_pin : 1;1370#else1371 u64 rboot_pin : 1;1372 u64 rboot : 1;1373 u64 lboot : 10;1374 u64 raz_12_23 : 12;1375 u64 pnr_mul : 6;1376 u64 raz_30_36 : 7;1377 u64 io_supply : 3;1378 u64 raz_40_57 : 18;1379 u64 jt_tst_mode : 1;1380 u64 raz_59_61 : 3;1381 u64 jtcsrdis : 1;1382 u64 raz_63 : 1;1383#endif1384 };1385};1386 1387/**1388 * struct fus_dat1: Fuse Data 1 Register1389 * @pll_mul: main clock PLL multiplier hardware limit1390 * @pll_half_dis: main clock PLL control1391 * @efus_lck: efuse lockdown1392 * @zip_info: ZIP information1393 * @bar2_sz_conf: when zero, BAR2 size conforms to1394 * PCIe specification1395 * @efus_ign: efuse ignore1396 * @nozip: ZIP disable1397 * @pll_alt_matrix: select alternate PLL matrix1398 * @pll_bwadj_denom: select CLKF denominator for1399 * BWADJ value1400 * @chip_id: chip ID1401 */1402union fus_dat1 {1403 u64 value;1404 struct {1405#if (defined(__BIG_ENDIAN_BITFIELD))1406 u64 raz_57_63 : 7;1407 u64 pll_mul : 3;1408 u64 pll_half_dis : 1;1409 u64 raz_43_52 : 10;1410 u64 efus_lck : 3;1411 u64 raz_26_39 : 14;1412 u64 zip_info : 5;1413 u64 bar2_sz_conf : 1;1414 u64 efus_ign : 1;1415 u64 nozip : 1;1416 u64 raz_11_17 : 7;1417 u64 pll_alt_matrix : 1;1418 u64 pll_bwadj_denom : 2;1419 u64 chip_id : 8;1420#else1421 u64 chip_id : 8;1422 u64 pll_bwadj_denom : 2;1423 u64 pll_alt_matrix : 1;1424 u64 raz_11_17 : 7;1425 u64 nozip : 1;1426 u64 efus_ign : 1;1427 u64 bar2_sz_conf : 1;1428 u64 zip_info : 5;1429 u64 raz_26_39 : 14;1430 u64 efus_lck : 3;1431 u64 raz_43_52 : 10;1432 u64 pll_half_dis : 1;1433 u64 pll_mul : 3;1434 u64 raz_57_63 : 7;1435#endif1436 };1437};1438 1439#endif /* __NITROX_CSR_H */1440