283 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright (C) 2012-2019 ARM Limited or its affiliates. */3 4#ifndef __CC_HOST_H__5#define __CC_HOST_H__6 7// --------------------------------------8// BLOCK: HOST_P9// --------------------------------------10 11 12/* IRR */13#define CC_HOST_IRR_REG_OFFSET 0xA00UL14#define CC_HOST_IRR_REE_OP_ABORTED_AES_0_INT_BIT_SHIFT 0x1UL15#define CC_HOST_IRR_REE_OP_ABORTED_AES_0_INT_BIT_SIZE 0x1UL16#define CC_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SHIFT 0x2UL17#define CC_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SIZE 0x1UL18#define CC_HOST_IRR_REE_OP_ABORTED_AES_1_INT_BIT_SHIFT 0x3UL19#define CC_HOST_IRR_REE_OP_ABORTED_AES_1_INT_BIT_SIZE 0x1UL20#define CC_HOST_IRR_REE_OP_ABORTED_AES_2_INT_BIT_SHIFT 0x4UL21#define CC_HOST_IRR_REE_OP_ABORTED_AES_2_INT_BIT_SIZE 0x1UL22#define CC_HOST_IRR_REE_OP_ABORTED_AES_3_INT_BIT_SHIFT 0x5UL23#define CC_HOST_IRR_REE_OP_ABORTED_AES_3_INT_BIT_SIZE 0x1UL24#define CC_HOST_IRR_REE_OP_ABORTED_AES_4_INT_BIT_SHIFT 0x6UL25#define CC_HOST_IRR_REE_OP_ABORTED_AES_4_INT_BIT_SIZE 0x1UL26#define CC_HOST_IRR_REE_OP_ABORTED_AES_5_INT_BIT_SHIFT 0x7UL27#define CC_HOST_IRR_REE_OP_ABORTED_AES_5_INT_BIT_SIZE 0x1UL28#define CC_HOST_IRR_AXI_ERR_INT_BIT_SHIFT 0x8UL29#define CC_HOST_IRR_AXI_ERR_INT_BIT_SIZE 0x1UL30#define CC_HOST_IRR_REE_OP_ABORTED_AES_6_INT_BIT_SHIFT 0x9UL31#define CC_HOST_IRR_REE_OP_ABORTED_AES_6_INT_BIT_SIZE 0x1UL32#define CC_HOST_IRR_REE_OP_ABORTED_AES_7_INT_BIT_SHIFT 0xAUL33#define CC_HOST_IRR_REE_OP_ABORTED_AES_7_INT_BIT_SIZE 0x1UL34#define CC_HOST_IRR_GPR0_BIT_SHIFT 0xBUL35#define CC_HOST_IRR_GPR0_BIT_SIZE 0x1UL36#define CC_HOST_IRR_REE_OP_ABORTED_SM_0_INT_BIT_SHIFT 0xCUL37#define CC_HOST_IRR_REE_OP_ABORTED_SM_0_INT_BIT_SIZE 0x1UL38#define CC_HOST_IRR_REE_OP_ABORTED_SM_1_INT_BIT_SHIFT 0xDUL39#define CC_HOST_IRR_REE_OP_ABORTED_SM_1_INT_BIT_SIZE 0x1UL40#define CC_HOST_IRR_REE_OP_ABORTED_SM_2_INT_BIT_SHIFT 0xEUL41#define CC_HOST_IRR_REE_OP_ABORTED_SM_2_INT_BIT_SIZE 0x1UL42#define CC_HOST_IRR_REE_OP_ABORTED_SM_3_INT_BIT_SHIFT 0xFUL43#define CC_HOST_IRR_REE_OP_ABORTED_SM_3_INT_BIT_SIZE 0x1UL44#define CC_HOST_IRR_REE_OP_ABORTED_SM_4_INT_BIT_SHIFT 0x10UL45#define CC_HOST_IRR_REE_OP_ABORTED_SM_4_INT_BIT_SIZE 0x1UL46#define CC_HOST_IRR_REE_OP_ABORTED_SM_5_INT_BIT_SHIFT 0x11UL47#define CC_HOST_IRR_REE_OP_ABORTED_SM_5_INT_BIT_SIZE 0x1UL48#define CC_HOST_IRR_REE_OP_ABORTED_SM_6_INT_BIT_SHIFT 0x12UL49#define CC_HOST_IRR_REE_OP_ABORTED_SM_6_INT_BIT_SIZE 0x1UL50#define CC_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SHIFT 0x13UL51#define CC_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SIZE 0x1UL52#define CC_HOST_IRR_REE_OP_ABORTED_SM_7_INT_BIT_SHIFT 0x14UL53#define CC_HOST_IRR_REE_OP_ABORTED_SM_7_INT_BIT_SIZE 0x1UL54#define CC_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT 0x17UL55#define CC_HOST_IRR_AXIM_COMP_INT_BIT_SIZE 0x1UL56#define CC_HOST_SEP_SRAM_THRESHOLD_REG_OFFSET 0xA10UL57#define CC_HOST_SEP_SRAM_THRESHOLD_VALUE_BIT_SHIFT 0x0UL58#define CC_HOST_SEP_SRAM_THRESHOLD_VALUE_BIT_SIZE 0xCUL59 60/* IMR */61#define CC_HOST_IMR_REG_OFFSET 0x0A04UL62#define CC_HOST_IMR_REE_OP_ABORTED_AES_0_MASK_BIT_SHIFT 0x1UL63#define CC_HOST_IMR_REE_OP_ABORTED_AES_0_MASK_BIT_SIZE 0x1UL64#define CC_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SHIFT 0x2UL65#define CC_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SIZE 0x1UL66#define CC_HOST_IMR_REE_OP_ABORTED_AES_1_MASK_BIT_SHIFT 0x3UL67#define CC_HOST_IMR_REE_OP_ABORTED_AES_1_MASK_BIT_SIZE 0x1UL68#define CC_HOST_IMR_REE_OP_ABORTED_AES_2_MASK_BIT_SHIFT 0x4UL69#define CC_HOST_IMR_REE_OP_ABORTED_AES_2_MASK_BIT_SIZE 0x1UL70#define CC_HOST_IMR_REE_OP_ABORTED_AES_3_MASK_BIT_SHIFT 0x5UL71#define CC_HOST_IMR_REE_OP_ABORTED_AES_3_MASK_BIT_SIZE 0x1UL72#define CC_HOST_IMR_REE_OP_ABORTED_AES_4_MASK_BIT_SHIFT 0x6UL73#define CC_HOST_IMR_REE_OP_ABORTED_AES_4_MASK_BIT_SIZE 0x1UL74#define CC_HOST_IMR_REE_OP_ABORTED_AES_5_MASK_BIT_SHIFT 0x7UL75#define CC_HOST_IMR_REE_OP_ABORTED_AES_5_MASK_BIT_SIZE 0x1UL76#define CC_HOST_IMR_AXI_ERR_MASK_BIT_SHIFT 0x8UL77#define CC_HOST_IMR_AXI_ERR_MASK_BIT_SIZE 0x1UL78#define CC_HOST_IMR_REE_OP_ABORTED_AES_6_MASK_BIT_SHIFT 0x9UL79#define CC_HOST_IMR_REE_OP_ABORTED_AES_6_MASK_BIT_SIZE 0x1UL80#define CC_HOST_IMR_REE_OP_ABORTED_AES_7_MASK_BIT_SHIFT 0xAUL81#define CC_HOST_IMR_REE_OP_ABORTED_AES_7_MASK_BIT_SIZE 0x1UL82#define CC_HOST_IMR_GPR0_BIT_SHIFT 0xBUL83#define CC_HOST_IMR_GPR0_BIT_SIZE 0x1UL84#define CC_HOST_IMR_REE_OP_ABORTED_SM_0_MASK_BIT_SHIFT 0xCUL85#define CC_HOST_IMR_REE_OP_ABORTED_SM_0_MASK_BIT_SIZE 0x1UL86#define CC_HOST_IMR_REE_OP_ABORTED_SM_1_MASK_BIT_SHIFT 0xDUL87#define CC_HOST_IMR_REE_OP_ABORTED_SM_1_MASK_BIT_SIZE 0x1UL88#define CC_HOST_IMR_REE_OP_ABORTED_SM_2_MASK_BIT_SHIFT 0xEUL89#define CC_HOST_IMR_REE_OP_ABORTED_SM_2_MASK_BIT_SIZE 0x1UL90#define CC_HOST_IMR_REE_OP_ABORTED_SM_3_MASK_BIT_SHIFT 0xFUL91#define CC_HOST_IMR_REE_OP_ABORTED_SM_3_MASK_BIT_SIZE 0x1UL92#define CC_HOST_IMR_REE_OP_ABORTED_SM_4_MASK_BIT_SHIFT 0x10UL93#define CC_HOST_IMR_REE_OP_ABORTED_SM_4_MASK_BIT_SIZE 0x1UL94#define CC_HOST_IMR_REE_OP_ABORTED_SM_5_MASK_BIT_SHIFT 0x11UL95#define CC_HOST_IMR_REE_OP_ABORTED_SM_5_MASK_BIT_SIZE 0x1UL96#define CC_HOST_IMR_REE_OP_ABORTED_SM_6_MASK_BIT_SHIFT 0x12UL97#define CC_HOST_IMR_REE_OP_ABORTED_SM_6_MASK_BIT_SIZE 0x1UL98#define CC_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SHIFT 0x13UL99#define CC_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SIZE 0x1UL100#define CC_HOST_IMR_REE_OP_ABORTED_SM_7_MASK_BIT_SHIFT 0x14UL101#define CC_HOST_IMR_REE_OP_ABORTED_SM_7_MASK_BIT_SIZE 0x1UL102#define CC_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SHIFT 0x17UL103#define CC_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SIZE 0x1UL104 105/* ICR */106#define CC_HOST_ICR_REG_OFFSET 0xA08UL107#define CC_HOST_ICR_DSCRPTR_COMPLETION_BIT_SHIFT 0x2UL108#define CC_HOST_ICR_DSCRPTR_COMPLETION_BIT_SIZE 0x1UL109#define CC_HOST_ICR_AXI_ERR_CLEAR_BIT_SHIFT 0x8UL110#define CC_HOST_ICR_AXI_ERR_CLEAR_BIT_SIZE 0x1UL111#define CC_HOST_ICR_GPR_INT_CLEAR_BIT_SHIFT 0xBUL112#define CC_HOST_ICR_GPR_INT_CLEAR_BIT_SIZE 0x1UL113#define CC_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SHIFT 0x13UL114#define CC_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SIZE 0x1UL115#define CC_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SHIFT 0x17UL116#define CC_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SIZE 0x1UL117#define CC_NVM_IS_IDLE_REG_OFFSET 0x0A10UL118#define CC_NVM_IS_IDLE_VALUE_BIT_SHIFT 0x0UL119#define CC_NVM_IS_IDLE_VALUE_BIT_SIZE 0x1UL120#define CC_SECURITY_DISABLED_REG_OFFSET 0x0A1CUL121#define CC_SECURITY_DISABLED_VALUE_BIT_SHIFT 0x0UL122#define CC_SECURITY_DISABLED_VALUE_BIT_SIZE 0x1UL123#define CC_HOST_SIGNATURE_712_REG_OFFSET 0xA24UL124#define CC_HOST_SIGNATURE_630_REG_OFFSET 0xAC8UL125#define CC_HOST_SIGNATURE_VALUE_BIT_SHIFT 0x0UL126#define CC_HOST_SIGNATURE_VALUE_BIT_SIZE 0x20UL127#define CC_HOST_BOOT_REG_OFFSET 0xA28UL128#define CC_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SHIFT 0x0UL129#define CC_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SIZE 0x1UL130#define CC_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SHIFT 0x1UL131#define CC_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SIZE 0x1UL132#define CC_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SHIFT 0x2UL133#define CC_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SIZE 0x1UL134#define CC_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SHIFT 0x3UL135#define CC_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SIZE 0x1UL136#define CC_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SHIFT 0x5UL137#define CC_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SIZE 0x1UL138#define CC_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SHIFT 0x6UL139#define CC_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SIZE 0x3UL140#define CC_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SHIFT 0x9UL141#define CC_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SIZE 0x1UL142#define CC_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SHIFT 0xAUL143#define CC_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SIZE 0x1UL144#define CC_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SHIFT 0xBUL145#define CC_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SIZE 0x1UL146#define CC_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SHIFT 0xCUL147#define CC_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SIZE 0x1UL148#define CC_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SHIFT 0xDUL149#define CC_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SIZE 0x1UL150#define CC_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SHIFT 0xEUL151#define CC_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SIZE 0x1UL152#define CC_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SHIFT 0xFUL153#define CC_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SIZE 0x1UL154#define CC_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SHIFT 0x10UL155#define CC_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SIZE 0x1UL156#define CC_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SHIFT 0x11UL157#define CC_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SIZE 0x1UL158#define CC_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SHIFT 0x12UL159#define CC_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SIZE 0x1UL160#define CC_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SHIFT 0x13UL161#define CC_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SIZE 0x1UL162#define CC_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SHIFT 0x14UL163#define CC_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SIZE 0x1UL164#define CC_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SHIFT 0x15UL165#define CC_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SIZE 0x1UL166#define CC_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SHIFT 0x16UL167#define CC_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SIZE 0x1UL168#define CC_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SHIFT 0x17UL169#define CC_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SIZE 0x1UL170#define CC_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SHIFT 0x18UL171#define CC_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SIZE 0x1UL172#define CC_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SHIFT 0x19UL173#define CC_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SIZE 0x1UL174#define CC_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SHIFT 0x1AUL175#define CC_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SIZE 0x1UL176#define CC_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SHIFT 0x1BUL177#define CC_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SIZE 0x1UL178#define CC_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SHIFT 0x1CUL179#define CC_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SIZE 0x1UL180#define CC_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SHIFT 0x1DUL181#define CC_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SIZE 0x1UL182#define CC_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SHIFT 0x1EUL183#define CC_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SIZE 0x1UL184#define CC_HOST_VERSION_712_REG_OFFSET 0xA40UL185#define CC_HOST_VERSION_630_REG_OFFSET 0xAD8UL186#define CC_HOST_VERSION_VALUE_BIT_SHIFT 0x0UL187#define CC_HOST_VERSION_VALUE_BIT_SIZE 0x20UL188#define CC_HOST_KFDE0_VALID_REG_OFFSET 0xA60UL189#define CC_HOST_KFDE0_VALID_VALUE_BIT_SHIFT 0x0UL190#define CC_HOST_KFDE0_VALID_VALUE_BIT_SIZE 0x1UL191#define CC_HOST_KFDE1_VALID_REG_OFFSET 0xA64UL192#define CC_HOST_KFDE1_VALID_VALUE_BIT_SHIFT 0x0UL193#define CC_HOST_KFDE1_VALID_VALUE_BIT_SIZE 0x1UL194#define CC_HOST_KFDE2_VALID_REG_OFFSET 0xA68UL195#define CC_HOST_KFDE2_VALID_VALUE_BIT_SHIFT 0x0UL196#define CC_HOST_KFDE2_VALID_VALUE_BIT_SIZE 0x1UL197#define CC_HOST_KFDE3_VALID_REG_OFFSET 0xA6CUL198#define CC_HOST_KFDE3_VALID_VALUE_BIT_SHIFT 0x0UL199#define CC_HOST_KFDE3_VALID_VALUE_BIT_SIZE 0x1UL200#define CC_HOST_GPR0_REG_OFFSET 0xA70UL201#define CC_HOST_GPR0_VALUE_BIT_SHIFT 0x0UL202#define CC_HOST_GPR0_VALUE_BIT_SIZE 0x20UL203#define CC_GPR_HOST_REG_OFFSET 0xA74UL204#define CC_GPR_HOST_VALUE_BIT_SHIFT 0x0UL205#define CC_GPR_HOST_VALUE_BIT_SIZE 0x20UL206#define CC_HOST_POWER_DOWN_EN_REG_OFFSET 0xA78UL207#define CC_HOST_POWER_DOWN_EN_VALUE_BIT_SHIFT 0x0UL208#define CC_HOST_POWER_DOWN_EN_VALUE_BIT_SIZE 0x1UL209#define CC_HOST_REMOVE_INPUT_PINS_REG_OFFSET 0x0A7CUL210#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_AES_ENGINE_BIT_SHIFT 0x0UL211#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_AES_ENGINE_BIT_SIZE 0x1UL212#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_AES_MAC_ENGINE_BIT_SHIFT 0x1UL213#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_AES_MAC_ENGINE_BIT_SIZE 0x1UL214#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_GHASH_ENGINE_BIT_SHIFT 0x2UL215#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_GHASH_ENGINE_BIT_SIZE 0x1UL216#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_DES_ENGINE_BIT_SHIFT 0x3UL217#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_DES_ENGINE_BIT_SIZE 0x1UL218#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_HASH_ENGINE_BIT_SHIFT 0x4UL219#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_HASH_ENGINE_BIT_SIZE 0x1UL220#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_SM3_ENGINE_BIT_SHIFT 0x5UL221#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_SM3_ENGINE_BIT_SIZE 0x1UL222#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_SM4_ENGINE_BIT_SHIFT 0x6UL223#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_SM4_ENGINE_BIT_SIZE 0x1UL224#define CC_HOST_REMOVE_INPUT_PINS_OTP_DISCONNECTED_BIT_SHIFT 0x7UL225#define CC_HOST_REMOVE_INPUT_PINS_OTP_DISCONNECTED_BIT_SIZE 0x1UL226// --------------------------------------227// BLOCK: ID_REGISTERS228// --------------------------------------229#define CC_PERIPHERAL_ID_4_REG_OFFSET 0x0FD0UL230#define CC_PERIPHERAL_ID_4_VALUE_BIT_SHIFT 0x0UL231#define CC_PERIPHERAL_ID_4_VALUE_BIT_SIZE 0x4UL232#define CC_PIDRESERVED0_REG_OFFSET 0x0FD4UL233#define CC_PIDRESERVED1_REG_OFFSET 0x0FD8UL234#define CC_PIDRESERVED2_REG_OFFSET 0x0FDCUL235#define CC_PERIPHERAL_ID_0_REG_OFFSET 0x0FE0UL236#define CC_PERIPHERAL_ID_0_VALUE_BIT_SHIFT 0x0UL237#define CC_PERIPHERAL_ID_0_VALUE_BIT_SIZE 0x8UL238#define CC_PERIPHERAL_ID_1_REG_OFFSET 0x0FE4UL239#define CC_PERIPHERAL_ID_1_PART_1_BIT_SHIFT 0x0UL240#define CC_PERIPHERAL_ID_1_PART_1_BIT_SIZE 0x4UL241#define CC_PERIPHERAL_ID_1_DES_0_JEP106_BIT_SHIFT 0x4UL242#define CC_PERIPHERAL_ID_1_DES_0_JEP106_BIT_SIZE 0x4UL243#define CC_PERIPHERAL_ID_2_REG_OFFSET 0x0FE8UL244#define CC_PERIPHERAL_ID_2_DES_1_JEP106_BIT_SHIFT 0x0UL245#define CC_PERIPHERAL_ID_2_DES_1_JEP106_BIT_SIZE 0x3UL246#define CC_PERIPHERAL_ID_2_JEDEC_BIT_SHIFT 0x3UL247#define CC_PERIPHERAL_ID_2_JEDEC_BIT_SIZE 0x1UL248#define CC_PERIPHERAL_ID_2_REVISION_BIT_SHIFT 0x4UL249#define CC_PERIPHERAL_ID_2_REVISION_BIT_SIZE 0x4UL250#define CC_PERIPHERAL_ID_3_REG_OFFSET 0x0FECUL251#define CC_PERIPHERAL_ID_3_CMOD_BIT_SHIFT 0x0UL252#define CC_PERIPHERAL_ID_3_CMOD_BIT_SIZE 0x4UL253#define CC_PERIPHERAL_ID_3_REVAND_BIT_SHIFT 0x4UL254#define CC_PERIPHERAL_ID_3_REVAND_BIT_SIZE 0x4UL255#define CC_COMPONENT_ID_0_REG_OFFSET 0x0FF0UL256#define CC_COMPONENT_ID_0_VALUE_BIT_SHIFT 0x0UL257#define CC_COMPONENT_ID_0_VALUE_BIT_SIZE 0x8UL258#define CC_COMPONENT_ID_1_REG_OFFSET 0x0FF4UL259#define CC_COMPONENT_ID_1_PRMBL_1_BIT_SHIFT 0x0UL260#define CC_COMPONENT_ID_1_PRMBL_1_BIT_SIZE 0x4UL261#define CC_COMPONENT_ID_1_CLASS_BIT_SHIFT 0x4UL262#define CC_COMPONENT_ID_1_CLASS_BIT_SIZE 0x4UL263#define CC_COMPONENT_ID_2_REG_OFFSET 0x0FF8UL264#define CC_COMPONENT_ID_2_VALUE_BIT_SHIFT 0x0UL265#define CC_COMPONENT_ID_2_VALUE_BIT_SIZE 0x8UL266#define CC_COMPONENT_ID_3_REG_OFFSET 0x0FFCUL267#define CC_COMPONENT_ID_3_VALUE_BIT_SHIFT 0x0UL268#define CC_COMPONENT_ID_3_VALUE_BIT_SIZE 0x8UL269// --------------------------------------270// BLOCK: HOST_SRAM271// --------------------------------------272#define CC_SRAM_DATA_REG_OFFSET 0xF00UL273#define CC_SRAM_DATA_VALUE_BIT_SHIFT 0x0UL274#define CC_SRAM_DATA_VALUE_BIT_SIZE 0x20UL275#define CC_SRAM_ADDR_REG_OFFSET 0xF04UL276#define CC_SRAM_ADDR_VALUE_BIT_SHIFT 0x0UL277#define CC_SRAM_ADDR_VALUE_BIT_SIZE 0xFUL278#define CC_SRAM_DATA_READY_REG_OFFSET 0xF08UL279#define CC_SRAM_DATA_READY_VALUE_BIT_SHIFT 0x0UL280#define CC_SRAM_DATA_READY_VALUE_BIT_SIZE 0x1UL281 282#endif //__CC_HOST_H__283