169 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */3 4#ifndef __CC_CRYS_KERNEL_H__5#define __CC_CRYS_KERNEL_H__6 7// --------------------------------------8// BLOCK: DSCRPTR9// --------------------------------------10#define CC_DSCRPTR_COMPLETION_COUNTER_REG_OFFSET 0xE00UL11#define CC_DSCRPTR_COMPLETION_COUNTER_COMPLETION_COUNTER_BIT_SHIFT 0x0UL12#define CC_DSCRPTR_COMPLETION_COUNTER_COMPLETION_COUNTER_BIT_SIZE 0x6UL13#define CC_DSCRPTR_COMPLETION_COUNTER_OVERFLOW_COUNTER_BIT_SHIFT 0x6UL14#define CC_DSCRPTR_COMPLETION_COUNTER_OVERFLOW_COUNTER_BIT_SIZE 0x1UL15#define CC_DSCRPTR_SW_RESET_REG_OFFSET 0xE40UL16#define CC_DSCRPTR_SW_RESET_VALUE_BIT_SHIFT 0x0UL17#define CC_DSCRPTR_SW_RESET_VALUE_BIT_SIZE 0x1UL18#define CC_DSCRPTR_QUEUE_SRAM_SIZE_REG_OFFSET 0xE60UL19#define CC_DSCRPTR_QUEUE_SRAM_SIZE_NUM_OF_DSCRPTR_BIT_SHIFT 0x0UL20#define CC_DSCRPTR_QUEUE_SRAM_SIZE_NUM_OF_DSCRPTR_BIT_SIZE 0xAUL21#define CC_DSCRPTR_QUEUE_SRAM_SIZE_DSCRPTR_SRAM_SIZE_BIT_SHIFT 0xAUL22#define CC_DSCRPTR_QUEUE_SRAM_SIZE_DSCRPTR_SRAM_SIZE_BIT_SIZE 0xCUL23#define CC_DSCRPTR_QUEUE_SRAM_SIZE_SRAM_SIZE_BIT_SHIFT 0x16UL24#define CC_DSCRPTR_QUEUE_SRAM_SIZE_SRAM_SIZE_BIT_SIZE 0x3UL25#define CC_DSCRPTR_SINGLE_ADDR_EN_REG_OFFSET 0xE64UL26#define CC_DSCRPTR_SINGLE_ADDR_EN_VALUE_BIT_SHIFT 0x0UL27#define CC_DSCRPTR_SINGLE_ADDR_EN_VALUE_BIT_SIZE 0x1UL28#define CC_DSCRPTR_MEASURE_CNTR_REG_OFFSET 0xE68UL29#define CC_DSCRPTR_MEASURE_CNTR_VALUE_BIT_SHIFT 0x0UL30#define CC_DSCRPTR_MEASURE_CNTR_VALUE_BIT_SIZE 0x20UL31#define CC_DSCRPTR_QUEUE_WORD0_REG_OFFSET 0xE80UL32#define CC_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SHIFT 0x0UL33#define CC_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SIZE 0x20UL34#define CC_DSCRPTR_QUEUE_WORD1_REG_OFFSET 0xE84UL35#define CC_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SHIFT 0x0UL36#define CC_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SIZE 0x2UL37#define CC_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SHIFT 0x2UL38#define CC_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SIZE 0x18UL39#define CC_DSCRPTR_QUEUE_WORD1_NS_BIT_BIT_SHIFT 0x1AUL40#define CC_DSCRPTR_QUEUE_WORD1_NS_BIT_BIT_SIZE 0x1UL41#define CC_DSCRPTR_QUEUE_WORD1_DIN_CONST_VALUE_BIT_SHIFT 0x1BUL42#define CC_DSCRPTR_QUEUE_WORD1_DIN_CONST_VALUE_BIT_SIZE 0x1UL43#define CC_DSCRPTR_QUEUE_WORD1_NOT_LAST_BIT_SHIFT 0x1CUL44#define CC_DSCRPTR_QUEUE_WORD1_NOT_LAST_BIT_SIZE 0x1UL45#define CC_DSCRPTR_QUEUE_WORD1_LOCK_QUEUE_BIT_SHIFT 0x1DUL46#define CC_DSCRPTR_QUEUE_WORD1_LOCK_QUEUE_BIT_SIZE 0x1UL47#define CC_DSCRPTR_QUEUE_WORD1_NOT_USED_BIT_SHIFT 0x1EUL48#define CC_DSCRPTR_QUEUE_WORD1_NOT_USED_BIT_SIZE 0x2UL49#define CC_DSCRPTR_QUEUE_WORD2_REG_OFFSET 0xE88UL50#define CC_DSCRPTR_QUEUE_WORD2_VALUE_BIT_SHIFT 0x0UL51#define CC_DSCRPTR_QUEUE_WORD2_VALUE_BIT_SIZE 0x20UL52#define CC_DSCRPTR_QUEUE_WORD3_REG_OFFSET 0xE8CUL53#define CC_DSCRPTR_QUEUE_WORD3_DOUT_DMA_MODE_BIT_SHIFT 0x0UL54#define CC_DSCRPTR_QUEUE_WORD3_DOUT_DMA_MODE_BIT_SIZE 0x2UL55#define CC_DSCRPTR_QUEUE_WORD3_DOUT_SIZE_BIT_SHIFT 0x2UL56#define CC_DSCRPTR_QUEUE_WORD3_DOUT_SIZE_BIT_SIZE 0x18UL57#define CC_DSCRPTR_QUEUE_WORD3_NS_BIT_BIT_SHIFT 0x1AUL58#define CC_DSCRPTR_QUEUE_WORD3_NS_BIT_BIT_SIZE 0x1UL59#define CC_DSCRPTR_QUEUE_WORD3_DOUT_LAST_IND_BIT_SHIFT 0x1BUL60#define CC_DSCRPTR_QUEUE_WORD3_DOUT_LAST_IND_BIT_SIZE 0x1UL61#define CC_DSCRPTR_QUEUE_WORD3_HASH_XOR_BIT_BIT_SHIFT 0x1DUL62#define CC_DSCRPTR_QUEUE_WORD3_HASH_XOR_BIT_BIT_SIZE 0x1UL63#define CC_DSCRPTR_QUEUE_WORD3_NOT_USED_BIT_SHIFT 0x1EUL64#define CC_DSCRPTR_QUEUE_WORD3_NOT_USED_BIT_SIZE 0x1UL65#define CC_DSCRPTR_QUEUE_WORD3_QUEUE_LAST_IND_BIT_SHIFT 0x1FUL66#define CC_DSCRPTR_QUEUE_WORD3_QUEUE_LAST_IND_BIT_SIZE 0x1UL67#define CC_DSCRPTR_QUEUE_WORD4_REG_OFFSET 0xE90UL68#define CC_DSCRPTR_QUEUE_WORD4_DATA_FLOW_MODE_BIT_SHIFT 0x0UL69#define CC_DSCRPTR_QUEUE_WORD4_DATA_FLOW_MODE_BIT_SIZE 0x6UL70#define CC_DSCRPTR_QUEUE_WORD4_AES_SEL_N_HASH_BIT_SHIFT 0x6UL71#define CC_DSCRPTR_QUEUE_WORD4_AES_SEL_N_HASH_BIT_SIZE 0x1UL72#define CC_DSCRPTR_QUEUE_WORD4_AES_XOR_CRYPTO_KEY_BIT_SHIFT 0x7UL73#define CC_DSCRPTR_QUEUE_WORD4_AES_XOR_CRYPTO_KEY_BIT_SIZE 0x1UL74#define CC_DSCRPTR_QUEUE_WORD4_ACK_NEEDED_BIT_SHIFT 0x8UL75#define CC_DSCRPTR_QUEUE_WORD4_ACK_NEEDED_BIT_SIZE 0x2UL76#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_MODE_BIT_SHIFT 0xAUL77#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_MODE_BIT_SIZE 0x4UL78#define CC_DSCRPTR_QUEUE_WORD4_CMAC_SIZE0_BIT_SHIFT 0xEUL79#define CC_DSCRPTR_QUEUE_WORD4_CMAC_SIZE0_BIT_SIZE 0x1UL80#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_DO_BIT_SHIFT 0xFUL81#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_DO_BIT_SIZE 0x2UL82#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF0_BIT_SHIFT 0x11UL83#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF0_BIT_SIZE 0x2UL84#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF1_BIT_SHIFT 0x13UL85#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF1_BIT_SIZE 0x1UL86#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF2_BIT_SHIFT 0x14UL87#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF2_BIT_SIZE 0x2UL88#define CC_DSCRPTR_QUEUE_WORD4_KEY_SIZE_BIT_SHIFT 0x16UL89#define CC_DSCRPTR_QUEUE_WORD4_KEY_SIZE_BIT_SIZE 0x2UL90#define CC_DSCRPTR_QUEUE_WORD4_SETUP_OPERATION_BIT_SHIFT 0x18UL91#define CC_DSCRPTR_QUEUE_WORD4_SETUP_OPERATION_BIT_SIZE 0x4UL92#define CC_DSCRPTR_QUEUE_WORD4_DIN_SRAM_ENDIANNESS_BIT_SHIFT 0x1CUL93#define CC_DSCRPTR_QUEUE_WORD4_DIN_SRAM_ENDIANNESS_BIT_SIZE 0x1UL94#define CC_DSCRPTR_QUEUE_WORD4_DOUT_SRAM_ENDIANNESS_BIT_SHIFT 0x1DUL95#define CC_DSCRPTR_QUEUE_WORD4_DOUT_SRAM_ENDIANNESS_BIT_SIZE 0x1UL96#define CC_DSCRPTR_QUEUE_WORD4_WORD_SWAP_BIT_SHIFT 0x1EUL97#define CC_DSCRPTR_QUEUE_WORD4_WORD_SWAP_BIT_SIZE 0x1UL98#define CC_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SHIFT 0x1FUL99#define CC_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SIZE 0x1UL100#define CC_DSCRPTR_QUEUE_WORD5_REG_OFFSET 0xE94UL101#define CC_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SHIFT 0x0UL102#define CC_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SIZE 0x10UL103#define CC_DSCRPTR_QUEUE_WORD5_DOUT_ADDR_HIGH_BIT_SHIFT 0x10UL104#define CC_DSCRPTR_QUEUE_WORD5_DOUT_ADDR_HIGH_BIT_SIZE 0x10UL105#define CC_DSCRPTR_QUEUE_WATERMARK_REG_OFFSET 0xE98UL106#define CC_DSCRPTR_QUEUE_WATERMARK_VALUE_BIT_SHIFT 0x0UL107#define CC_DSCRPTR_QUEUE_WATERMARK_VALUE_BIT_SIZE 0xAUL108#define CC_DSCRPTR_QUEUE_CONTENT_REG_OFFSET 0xE9CUL109#define CC_DSCRPTR_QUEUE_CONTENT_VALUE_BIT_SHIFT 0x0UL110#define CC_DSCRPTR_QUEUE_CONTENT_VALUE_BIT_SIZE 0xAUL111// --------------------------------------112// BLOCK: AXI_P113// --------------------------------------114#define CC_AXIM_MON_INFLIGHT_REG_OFFSET 0xB00UL115#define CC_AXIM_MON_INFLIGHT_VALUE_BIT_SHIFT 0x0UL116#define CC_AXIM_MON_INFLIGHT_VALUE_BIT_SIZE 0x8UL117#define CC_AXIM_MON_INFLIGHTLAST_REG_OFFSET 0xB40UL118#define CC_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SHIFT 0x0UL119#define CC_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SIZE 0x8UL120#define CC_AXIM_MON_COMP_REG_OFFSET 0xB80UL121#define CC_AXIM_MON_COMP8_REG_OFFSET 0xBA0UL122#define CC_AXIM_MON_COMP_VALUE_BIT_SHIFT 0x0UL123#define CC_AXIM_MON_COMP_VALUE_BIT_SIZE 0x10UL124#define CC_AXIM_MON_ERR_REG_OFFSET 0xBC4UL125#define CC_AXIM_MON_ERR_BRESP_BIT_SHIFT 0x0UL126#define CC_AXIM_MON_ERR_BRESP_BIT_SIZE 0x2UL127#define CC_AXIM_MON_ERR_BID_BIT_SHIFT 0x2UL128#define CC_AXIM_MON_ERR_BID_BIT_SIZE 0x4UL129#define CC_AXIM_MON_ERR_RRESP_BIT_SHIFT 0x10UL130#define CC_AXIM_MON_ERR_RRESP_BIT_SIZE 0x2UL131#define CC_AXIM_MON_ERR_RID_BIT_SHIFT 0x12UL132#define CC_AXIM_MON_ERR_RID_BIT_SIZE 0x4UL133#define CC_AXIM_CFG_REG_OFFSET 0xBE8UL134#define CC_AXIM_CFG_BRESPMASK_BIT_SHIFT 0x4UL135#define CC_AXIM_CFG_BRESPMASK_BIT_SIZE 0x1UL136#define CC_AXIM_CFG_RRESPMASK_BIT_SHIFT 0x5UL137#define CC_AXIM_CFG_RRESPMASK_BIT_SIZE 0x1UL138#define CC_AXIM_CFG_INFLTMASK_BIT_SHIFT 0x6UL139#define CC_AXIM_CFG_INFLTMASK_BIT_SIZE 0x1UL140#define CC_AXIM_CFG_COMPMASK_BIT_SHIFT 0x7UL141#define CC_AXIM_CFG_COMPMASK_BIT_SIZE 0x1UL142#define CC_AXIM_ACE_CONST_REG_OFFSET 0xBECUL143#define CC_AXIM_ACE_CONST_ARDOMAIN_BIT_SHIFT 0x0UL144#define CC_AXIM_ACE_CONST_ARDOMAIN_BIT_SIZE 0x2UL145#define CC_AXIM_ACE_CONST_AWDOMAIN_BIT_SHIFT 0x2UL146#define CC_AXIM_ACE_CONST_AWDOMAIN_BIT_SIZE 0x2UL147#define CC_AXIM_ACE_CONST_ARBAR_BIT_SHIFT 0x4UL148#define CC_AXIM_ACE_CONST_ARBAR_BIT_SIZE 0x2UL149#define CC_AXIM_ACE_CONST_AWBAR_BIT_SHIFT 0x6UL150#define CC_AXIM_ACE_CONST_AWBAR_BIT_SIZE 0x2UL151#define CC_AXIM_ACE_CONST_ARSNOOP_BIT_SHIFT 0x8UL152#define CC_AXIM_ACE_CONST_ARSNOOP_BIT_SIZE 0x4UL153#define CC_AXIM_ACE_CONST_AWSNOOP_NOT_ALIGNED_BIT_SHIFT 0xCUL154#define CC_AXIM_ACE_CONST_AWSNOOP_NOT_ALIGNED_BIT_SIZE 0x3UL155#define CC_AXIM_ACE_CONST_AWSNOOP_ALIGNED_BIT_SHIFT 0xFUL156#define CC_AXIM_ACE_CONST_AWSNOOP_ALIGNED_BIT_SIZE 0x3UL157#define CC_AXIM_ACE_CONST_AWADDR_NOT_MASKED_BIT_SHIFT 0x12UL158#define CC_AXIM_ACE_CONST_AWADDR_NOT_MASKED_BIT_SIZE 0x7UL159#define CC_AXIM_ACE_CONST_AWLEN_VAL_BIT_SHIFT 0x19UL160#define CC_AXIM_ACE_CONST_AWLEN_VAL_BIT_SIZE 0x4UL161#define CC_AXIM_CACHE_PARAMS_REG_OFFSET 0xBF0UL162#define CC_AXIM_CACHE_PARAMS_AWCACHE_LAST_BIT_SHIFT 0x0UL163#define CC_AXIM_CACHE_PARAMS_AWCACHE_LAST_BIT_SIZE 0x4UL164#define CC_AXIM_CACHE_PARAMS_AWCACHE_BIT_SHIFT 0x4UL165#define CC_AXIM_CACHE_PARAMS_AWCACHE_BIT_SIZE 0x4UL166#define CC_AXIM_CACHE_PARAMS_ARCACHE_BIT_SHIFT 0x8UL167#define CC_AXIM_CACHE_PARAMS_ARCACHE_BIT_SIZE 0x4UL168#endif // __CC_CRYS_KERNEL_H__169