60 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */3 4#ifndef _CC_LLI_DEFS_H_5#define _CC_LLI_DEFS_H_6 7#include <linux/types.h>8 9/* Max DLLI size10 * AKA CC_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SIZE11 */12#define DLLI_SIZE_BIT_SIZE 0x1813 14#define CC_MAX_MLLI_ENTRY_SIZE 0xFFFF15 16#define LLI_MAX_NUM_OF_DATA_ENTRIES 12817#define LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES 818#define MLLI_TABLE_MIN_ALIGNMENT 4 /* 32 bit alignment */19#define MAX_NUM_OF_BUFFERS_IN_MLLI 420#define MAX_NUM_OF_TOTAL_MLLI_ENTRIES \21 (2 * LLI_MAX_NUM_OF_DATA_ENTRIES + \22 LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES)23 24/* Size of entry */25#define LLI_ENTRY_WORD_SIZE 226#define LLI_ENTRY_BYTE_SIZE (LLI_ENTRY_WORD_SIZE * sizeof(u32))27 28/* Word0[31:0] = ADDR[31:0] */29#define LLI_WORD0_OFFSET 030#define LLI_LADDR_BIT_OFFSET 031#define LLI_LADDR_BIT_SIZE 3232/* Word1[31:16] = ADDR[47:32]; Word1[15:0] = SIZE */33#define LLI_WORD1_OFFSET 134#define LLI_SIZE_BIT_OFFSET 035#define LLI_SIZE_BIT_SIZE 1636#define LLI_HADDR_BIT_OFFSET 1637#define LLI_HADDR_BIT_SIZE 1638 39#define LLI_SIZE_MASK GENMASK((LLI_SIZE_BIT_SIZE - 1), LLI_SIZE_BIT_OFFSET)40#define LLI_HADDR_MASK GENMASK( \41 (LLI_HADDR_BIT_OFFSET + LLI_HADDR_BIT_SIZE - 1),\42 LLI_HADDR_BIT_OFFSET)43 44static inline void cc_lli_set_addr(u32 *lli_p, dma_addr_t addr)45{46 lli_p[LLI_WORD0_OFFSET] = (addr & U32_MAX);47#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT48 lli_p[LLI_WORD1_OFFSET] &= ~LLI_HADDR_MASK;49 lli_p[LLI_WORD1_OFFSET] |= FIELD_PREP(LLI_HADDR_MASK, (addr >> 32));50#endif /* CONFIG_ARCH_DMA_ADDR_T_64BIT */51}52 53static inline void cc_lli_set_size(u32 *lli_p, u16 size)54{55 lli_p[LLI_WORD1_OFFSET] &= ~LLI_SIZE_MASK;56 lli_p[LLI_WORD1_OFFSET] |= FIELD_PREP(LLI_SIZE_MASK, size);57}58 59#endif /*_CC_LLI_DEFS_H_*/60