342 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * sl3516-ce.h - hardware cryptographic offloader for cortina/gemini SoC4 *5 * Copyright (C) 2021 Corentin LABBE <clabbe@baylibre.com>6 *7 * General notes on this driver:8 * Called either Crypto Acceleration Engine Module, Security Acceleration Engine9 * or IPSEC module in the datasheet, it will be called Crypto Engine for short10 * in this driver.11 * The CE was designed to handle IPSEC and wifi(TKIP WEP) protocol.12 * It can handle AES, DES, 3DES, MD5, WEP, TKIP, SHA1, HMAC(MD5), HMAC(SHA1),13 * Michael cipher/digest suites.14 * It acts the same as a network hw, with both RX and TX chained descriptors.15 */16#include <crypto/aes.h>17#include <crypto/engine.h>18#include <crypto/scatterwalk.h>19#include <crypto/skcipher.h>20#include <linux/debugfs.h>21#include <linux/hw_random.h>22 23#define TQ0_TYPE_DATA 024#define TQ0_TYPE_CTRL BIT(0)25#define TQ1_CIPHER BIT(1)26#define TQ2_AUTH BIT(2)27#define TQ3_IV BIT(3)28#define TQ4_KEY0 BIT(4)29#define TQ5_KEY4 BIT(5)30#define TQ6_KEY6 BIT(6)31#define TQ7_AKEY0 BIT(7)32#define TQ8_AKEY2 BIT(8)33#define TQ9_AKEY2 BIT(9)34 35#define ECB_AES 0x236 37#define DESC_LAST 0x0138#define DESC_FIRST 0x0239 40#define IPSEC_ID 0x000041#define IPSEC_STATUS_REG 0x00a842#define IPSEC_RAND_NUM_REG 0x00ac43#define IPSEC_DMA_DEVICE_ID 0xff0044#define IPSEC_DMA_STATUS 0xff0445#define IPSEC_TXDMA_CTRL 0xff0846#define IPSEC_TXDMA_FIRST_DESC 0xff0c47#define IPSEC_TXDMA_CURR_DESC 0xff1048#define IPSEC_RXDMA_CTRL 0xff1449#define IPSEC_RXDMA_FIRST_DESC 0xff1850#define IPSEC_RXDMA_CURR_DESC 0xff1c51#define IPSEC_TXDMA_BUF_ADDR 0xff2852#define IPSEC_RXDMA_BUF_ADDR 0xff3853#define IPSEC_RXDMA_BUF_SIZE 0xff3054 55#define CE_ENCRYPTION 0x0156#define CE_DECRYPTION 0x0357 58#define MAXDESC 659 60#define DMA_STATUS_RS_EOFI BIT(22)61#define DMA_STATUS_RS_PERR BIT(24)62#define DMA_STATUS_RS_DERR BIT(25)63#define DMA_STATUS_TS_EOFI BIT(27)64#define DMA_STATUS_TS_PERR BIT(29)65#define DMA_STATUS_TS_DERR BIT(30)66 67#define TXDMA_CTRL_START BIT(31)68#define TXDMA_CTRL_CONTINUE BIT(30)69#define TXDMA_CTRL_CHAIN_MODE BIT(29)70/* the burst value is not documented in the datasheet */71#define TXDMA_CTRL_BURST_UNK BIT(22)72#define TXDMA_CTRL_INT_FAIL BIT(17)73#define TXDMA_CTRL_INT_PERR BIT(16)74 75#define RXDMA_CTRL_START BIT(31)76#define RXDMA_CTRL_CONTINUE BIT(30)77#define RXDMA_CTRL_CHAIN_MODE BIT(29)78/* the burst value is not documented in the datasheet */79#define RXDMA_CTRL_BURST_UNK BIT(22)80#define RXDMA_CTRL_INT_FINISH BIT(18)81#define RXDMA_CTRL_INT_FAIL BIT(17)82#define RXDMA_CTRL_INT_PERR BIT(16)83#define RXDMA_CTRL_INT_EOD BIT(15)84#define RXDMA_CTRL_INT_EOF BIT(14)85 86#define CE_CPU 087#define CE_DMA 188 89/*90 * struct sl3516_ce_descriptor - descriptor for CE operations91 * @frame_ctrl: Information for the current descriptor92 * @flag_status: For send packet, describe flag of operations.93 * @buf_adr: pointer to a send/recv buffer for data packet94 * @next_desc: control linking to other descriptors95 */96struct descriptor {97 union {98 u32 raw;99 /*100 * struct desc_frame_ctrl - Information for the current descriptor101 * @buffer_size: the size of buffer at buf_adr102 * @desc_count: Upon completion of a DMA operation, DMA103 * write the number of descriptors used104 * for the current frame105 * @checksum: unknown106 * @authcomp: unknown107 * @perr: Protocol error during processing this descriptor108 * @derr: Data error during processing this descriptor109 * @own: 0 if owned by CPU, 1 for DMA110 */111 struct desc_frame_ctrl {112 u32 buffer_size :16;113 u32 desc_count :6;114 u32 checksum :6;115 u32 authcomp :1;116 u32 perr :1;117 u32 derr :1;118 u32 own :1;119 } bits;120 } frame_ctrl;121 122 union {123 u32 raw;124 /*125 * struct desc_flag_status - flag for this descriptor126 * @tqflag: list of flag describing the type of operation127 * to be performed.128 */129 struct desc_tx_flag_status {130 u32 tqflag :10;131 u32 unused :22;132 } tx_flag;133 } flag_status;134 135 u32 buf_adr;136 137 union {138 u32 next_descriptor;139 /*140 * struct desc_next - describe chaining of descriptors141 * @sof_eof: does the descriptor is first (0x11),142 * the last (0x01), middle of a chan (0x00)143 * or the only one (0x11)144 * @dec: AHB bus address increase (0), decrease (1)145 * @eofie: End of frame interrupt enable146 * @ndar: Next descriptor address147 */148 struct desc_next {149 u32 sof_eof :2;150 u32 dec :1;151 u32 eofie :1;152 u32 ndar :28;153 } bits;154 } next_desc;155};156 157/*158 * struct control - The value of this register is used to set the159 * operation mode of the IPSec Module.160 * @process_id: Used to identify the process. The number will be copied161 * to the descriptor status of the received packet.162 * @auth_check_len: Number of 32-bit words to be checked or appended by the163 * authentication module164 * @auth_algorithm:165 * @auth_mode: 0:append 1:Check Authentication Result166 * @fcs_stream_copy: 0:enable 1:disable authentication stream copy167 * @mix_key_sel: 0:use rCipherKey0-3 1:use Key Mixer168 * @aesnk: AES Key Size169 * @cipher_algorithm: choice of CBC/ECE and AES/DES/3DES170 * @op_mode: Operation Mode for the IPSec Module171 */172struct pkt_control_header {173 u32 process_id :8;174 u32 auth_check_len :3;175 u32 un1 :1;176 u32 auth_algorithm :3;177 u32 auth_mode :1;178 u32 fcs_stream_copy :1;179 u32 un2 :2;180 u32 mix_key_sel :1;181 u32 aesnk :4;182 u32 cipher_algorithm :3;183 u32 un3 :1;184 u32 op_mode :4;185};186 187struct pkt_control_cipher {188 u32 algorithm_len :16;189 u32 header_len :16;190};191 192/*193 * struct pkt_control_ecb - control packet for ECB194 */195struct pkt_control_ecb {196 struct pkt_control_header control;197 struct pkt_control_cipher cipher;198 unsigned char key[AES_MAX_KEY_SIZE];199};200 201/*202 * struct sl3516_ce_dev - main container for all this driver information203 * @base: base address204 * @clks: clocks used205 * @reset: pointer to reset controller206 * @dev: the platform device207 * @engine: ptr to the crypto/crypto_engine208 * @complete: completion for the current task on this flow209 * @status: set to 1 by interrupt if task is done210 * @dtx: base DMA address for TX descriptors211 * @tx base address of TX descriptors212 * @drx: base DMA address for RX descriptors213 * @rx base address of RX descriptors214 * @ctx current used TX descriptor215 * @crx current used RX descriptor216 * @trng hw_random structure for RNG217 * @hwrng_stat_req number of HWRNG requests218 * @hwrng_stat_bytes total number of bytes generated by RNG219 * @stat_irq number of IRQ handled by CE220 * @stat_irq_tx number of TX IRQ handled by CE221 * @stat_irq_rx number of RX IRQ handled by CE222 * @stat_req number of requests handled by CE223 * @fallbak_sg_count_tx number of fallback due to destination SG count224 * @fallbak_sg_count_rx number of fallback due to source SG count225 * @fallbak_not_same_len number of fallback due to difference in SG length226 * @dbgfs_dir: Debugfs dentry for statistic directory227 * @dbgfs_stats: Debugfs dentry for statistic counters228 */229struct sl3516_ce_dev {230 void __iomem *base;231 struct clk *clks;232 struct reset_control *reset;233 struct device *dev;234 struct crypto_engine *engine;235 struct completion complete;236 int status;237 dma_addr_t dtx;238 struct descriptor *tx;239 dma_addr_t drx;240 struct descriptor *rx;241 int ctx;242 int crx;243 struct hwrng trng;244 unsigned long hwrng_stat_req;245 unsigned long hwrng_stat_bytes;246 unsigned long stat_irq;247 unsigned long stat_irq_tx;248 unsigned long stat_irq_rx;249 unsigned long stat_req;250 unsigned long fallback_sg_count_tx;251 unsigned long fallback_sg_count_rx;252 unsigned long fallback_not_same_len;253 unsigned long fallback_mod16;254 unsigned long fallback_align16;255#ifdef CONFIG_CRYPTO_DEV_SL3516_DEBUG256 struct dentry *dbgfs_dir;257 struct dentry *dbgfs_stats;258#endif259 void *pctrl;260 dma_addr_t dctrl;261};262 263struct sginfo {264 u32 addr;265 u32 len;266};267 268/*269 * struct sl3516_ce_cipher_req_ctx - context for a skcipher request270 * @t_src: list of mapped SGs with their size271 * @t_dst: list of mapped SGs with their size272 * @op_dir: direction (encrypt vs decrypt) for this request273 * @pctrllen: the length of the ctrl packet274 * @tqflag: the TQflag to set in data packet275 * @h pointer to the pkt_control_cipher header276 * @nr_sgs: number of source SG277 * @nr_sgd: number of destination SG278 * @fallback_req: request struct for invoking the fallback skcipher TFM279 */280struct sl3516_ce_cipher_req_ctx {281 struct sginfo t_src[MAXDESC];282 struct sginfo t_dst[MAXDESC];283 u32 op_dir;284 unsigned int pctrllen;285 u32 tqflag;286 struct pkt_control_cipher *h;287 int nr_sgs;288 int nr_sgd;289 struct skcipher_request fallback_req; // keep at the end290};291 292/*293 * struct sl3516_ce_cipher_tfm_ctx - context for a skcipher TFM294 * @key: pointer to key data295 * @keylen: len of the key296 * @ce: pointer to the private data of driver handling this TFM297 * @fallback_tfm: pointer to the fallback TFM298 */299struct sl3516_ce_cipher_tfm_ctx {300 u32 *key;301 u32 keylen;302 struct sl3516_ce_dev *ce;303 struct crypto_skcipher *fallback_tfm;304};305 306/*307 * struct sl3516_ce_alg_template - crypto_alg template308 * @type: the CRYPTO_ALG_TYPE for this template309 * @mode: value to be used in control packet for this algorithm310 * @ce: pointer to the sl3516_ce_dev structure associated with311 * this template312 * @alg: one of sub struct must be used313 * @stat_req: number of request done on this template314 * @stat_fb: number of request which has fallbacked315 * @stat_bytes: total data size done by this template316 */317struct sl3516_ce_alg_template {318 u32 type;319 u32 mode;320 struct sl3516_ce_dev *ce;321 union {322 struct skcipher_engine_alg skcipher;323 } alg;324 unsigned long stat_req;325 unsigned long stat_fb;326 unsigned long stat_bytes;327};328 329int sl3516_ce_aes_setkey(struct crypto_skcipher *tfm, const u8 *key,330 unsigned int keylen);331int sl3516_ce_cipher_init(struct crypto_tfm *tfm);332void sl3516_ce_cipher_exit(struct crypto_tfm *tfm);333int sl3516_ce_skdecrypt(struct skcipher_request *areq);334int sl3516_ce_skencrypt(struct skcipher_request *areq);335 336int sl3516_ce_run_task(struct sl3516_ce_dev *ce,337 struct sl3516_ce_cipher_req_ctx *rctx, const char *name);338 339int sl3516_ce_rng_register(struct sl3516_ce_dev *ce);340void sl3516_ce_rng_unregister(struct sl3516_ce_dev *ce);341int sl3516_ce_handle_cipher_request(struct crypto_engine *engine, void *areq);342