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1/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */2/* Copyright(c) 2020 Intel Corporation */3#ifndef ADF_GEN4_HW_DATA_H_4#define ADF_GEN4_HW_DATA_H_5 6#include <linux/units.h>7 8#include "adf_accel_devices.h"9#include "adf_cfg_common.h"10 11/* PCIe configuration space */12#define ADF_GEN4_BAR_MASK (BIT(0) | BIT(2) | BIT(4))13#define ADF_GEN4_SRAM_BAR 014#define ADF_GEN4_PMISC_BAR 115#define ADF_GEN4_ETR_BAR 216 17/* Clocks frequency */18#define ADF_GEN4_KPT_COUNTER_FREQ (100 * HZ_PER_MHZ)19 20/* Physical function fuses */21#define ADF_GEN4_FUSECTL0_OFFSET 0x2C822#define ADF_GEN4_FUSECTL1_OFFSET 0x2CC23#define ADF_GEN4_FUSECTL2_OFFSET 0x2D024#define ADF_GEN4_FUSECTL3_OFFSET 0x2D425#define ADF_GEN4_FUSECTL4_OFFSET 0x2D826#define ADF_GEN4_FUSECTL5_OFFSET 0x2DC27 28/* Accelerators */29#define ADF_GEN4_ACCELERATORS_MASK 0x130#define ADF_GEN4_MAX_ACCELERATORS 131#define ADF_GEN4_ADMIN_ACCELENGINES 132 33/* MSIX interrupt */34#define ADF_GEN4_SMIAPF_RP_X0_MASK_OFFSET 0x41A04035#define ADF_GEN4_SMIAPF_RP_X1_MASK_OFFSET 0x41A04436#define ADF_GEN4_SMIAPF_MASK_OFFSET 0x41A08437#define ADF_GEN4_MSIX_RTTABLE_OFFSET(i) (0x409000 + ((i) * 0x04))38 39/* Bank and ring configuration */40#define ADF_GEN4_MAX_RPS 6441#define ADF_GEN4_NUM_RINGS_PER_BANK 242#define ADF_GEN4_NUM_BANKS_PER_VF 443#define ADF_GEN4_ETR_MAX_BANKS 6444#define ADF_GEN4_RX_RINGS_OFFSET 145#define ADF_GEN4_TX_RINGS_MASK 0x146 47/* Arbiter configuration */48#define ADF_GEN4_ARB_CONFIG (BIT(31) | BIT(6) | BIT(0))49#define ADF_GEN4_ARB_OFFSET 0x050#define ADF_GEN4_ARB_WRK_2_SER_MAP_OFFSET 0x40051 52/* Admin Interface Reg Offset */53#define ADF_GEN4_ADMINMSGUR_OFFSET 0x50057454#define ADF_GEN4_ADMINMSGLR_OFFSET 0x50057855#define ADF_GEN4_MAILBOX_BASE_OFFSET 0x60097056 57/* Default ring mapping */58#define ADF_GEN4_DEFAULT_RING_TO_SRV_MAP \59 (ASYM << ADF_CFG_SERV_RING_PAIR_0_SHIFT | \60 SYM << ADF_CFG_SERV_RING_PAIR_1_SHIFT | \61 ASYM << ADF_CFG_SERV_RING_PAIR_2_SHIFT | \62 SYM << ADF_CFG_SERV_RING_PAIR_3_SHIFT)63 64/* WDT timers65 *66 * Timeout is in cycles. Clock speed may vary across products but this67 * value should be a few milli-seconds.68 */69#define ADF_SSM_WDT_DEFAULT_VALUE 0x7000000ULL70#define ADF_SSM_WDT_PKE_DEFAULT_VALUE 0x800000071#define ADF_SSMWDTL_OFFSET 0x5472#define ADF_SSMWDTH_OFFSET 0x5C73#define ADF_SSMWDTPKEL_OFFSET 0x5874#define ADF_SSMWDTPKEH_OFFSET 0x6075 76/* Ring reset */77#define ADF_RPRESET_POLL_TIMEOUT_US (5 * USEC_PER_SEC)78#define ADF_RPRESET_POLL_DELAY_US 2079#define ADF_WQM_CSR_RPRESETCTL_RESET BIT(0)80#define ADF_WQM_CSR_RPRESETCTL_DRAIN BIT(2)81#define ADF_WQM_CSR_RPRESETCTL(bank) (0x6000 + ((bank) << 3))82#define ADF_WQM_CSR_RPRESETSTS_STATUS BIT(0)83#define ADF_WQM_CSR_RPRESETSTS(bank) (ADF_WQM_CSR_RPRESETCTL(bank) + 4)84 85/* Ring interrupt */86#define ADF_RP_INT_SRC_SEL_F_RISE_MASK GENMASK(1, 0)87#define ADF_RP_INT_SRC_SEL_F_FALL_MASK GENMASK(2, 0)88#define ADF_RP_INT_SRC_SEL_RANGE_WIDTH 489#define ADF_COALESCED_POLL_TIMEOUT_US (1 * USEC_PER_SEC)90#define ADF_COALESCED_POLL_DELAY_US 100091#define ADF_WQM_CSR_RPINTSOU(bank) (0x200000 + ((bank) << 12))92#define ADF_WQM_CSR_RP_IDX_RX 193 94/* Error source registers */95#define ADF_GEN4_ERRSOU0 (0x41A200)96#define ADF_GEN4_ERRSOU1 (0x41A204)97#define ADF_GEN4_ERRSOU2 (0x41A208)98#define ADF_GEN4_ERRSOU3 (0x41A20C)99 100/* Error source mask registers */101#define ADF_GEN4_ERRMSK0 (0x41A210)102#define ADF_GEN4_ERRMSK1 (0x41A214)103#define ADF_GEN4_ERRMSK2 (0x41A218)104#define ADF_GEN4_ERRMSK3 (0x41A21C)105 106#define ADF_GEN4_VFLNOTIFY BIT(7)107 108/* Number of heartbeat counter pairs */109#define ADF_NUM_HB_CNT_PER_AE ADF_NUM_THREADS_PER_AE110 111/* Rate Limiting */112#define ADF_GEN4_RL_R2L_OFFSET 0x508000113#define ADF_GEN4_RL_L2C_OFFSET 0x509000114#define ADF_GEN4_RL_C2S_OFFSET 0x508818115#define ADF_GEN4_RL_TOKEN_PCIEIN_BUCKET_OFFSET 0x508800116#define ADF_GEN4_RL_TOKEN_PCIEOUT_BUCKET_OFFSET 0x508804117 118/* Arbiter threads mask with error value */119#define ADF_GEN4_ENA_THD_MASK_ERROR GENMASK(ADF_NUM_THREADS_PER_AE, 0)120 121/* PF2VM communication channel */122#define ADF_GEN4_PF2VM_OFFSET(i) (0x40B010 + (i) * 0x20)123#define ADF_GEN4_VM2PF_OFFSET(i) (0x40B014 + (i) * 0x20)124#define ADF_GEN4_VINTMSKPF2VM_OFFSET(i) (0x40B00C + (i) * 0x20)125#define ADF_GEN4_VINTSOUPF2VM_OFFSET(i) (0x40B008 + (i) * 0x20)126#define ADF_GEN4_VINTMSK_OFFSET(i) (0x40B004 + (i) * 0x20)127#define ADF_GEN4_VINTSOU_OFFSET(i) (0x40B000 + (i) * 0x20)128 129struct adf_gen4_vfmig {130 struct adf_mstate_mgr *mstate_mgr;131 bool bank_stopped[ADF_GEN4_NUM_BANKS_PER_VF];132};133 134void adf_gen4_set_ssm_wdtimer(struct adf_accel_dev *accel_dev);135 136enum icp_qat_gen4_slice_mask {137 ICP_ACCEL_GEN4_MASK_CIPHER_SLICE = BIT(0),138 ICP_ACCEL_GEN4_MASK_AUTH_SLICE = BIT(1),139 ICP_ACCEL_GEN4_MASK_PKE_SLICE = BIT(2),140 ICP_ACCEL_GEN4_MASK_COMPRESS_SLICE = BIT(3),141 ICP_ACCEL_GEN4_MASK_UCS_SLICE = BIT(4),142 ICP_ACCEL_GEN4_MASK_EIA3_SLICE = BIT(5),143 ICP_ACCEL_GEN4_MASK_SMX_SLICE = BIT(7),144 ICP_ACCEL_GEN4_MASK_WCP_WAT_SLICE = BIT(8),145 ICP_ACCEL_GEN4_MASK_ZUC_256_SLICE = BIT(9),146};147 148enum adf_gen4_rp_groups {149 RP_GROUP_0,150 RP_GROUP_1,151 RP_GROUP_COUNT152};153 154void adf_gen4_enable_error_correction(struct adf_accel_dev *accel_dev);155void adf_gen4_enable_ints(struct adf_accel_dev *accel_dev);156u32 adf_gen4_get_accel_mask(struct adf_hw_device_data *self);157void adf_gen4_get_admin_info(struct admin_info *admin_csrs_info);158void adf_gen4_get_arb_info(struct arb_info *arb_info);159u32 adf_gen4_get_etr_bar_id(struct adf_hw_device_data *self);160u32 adf_gen4_get_heartbeat_clock(struct adf_hw_device_data *self);161u32 adf_gen4_get_misc_bar_id(struct adf_hw_device_data *self);162u32 adf_gen4_get_num_accels(struct adf_hw_device_data *self);163u32 adf_gen4_get_num_aes(struct adf_hw_device_data *self);164enum dev_sku_info adf_gen4_get_sku(struct adf_hw_device_data *self);165u32 adf_gen4_get_sram_bar_id(struct adf_hw_device_data *self);166int adf_gen4_init_device(struct adf_accel_dev *accel_dev);167int adf_gen4_ring_pair_reset(struct adf_accel_dev *accel_dev, u32 bank_number);168void adf_gen4_set_msix_default_rttable(struct adf_accel_dev *accel_dev);169void adf_gen4_set_ssm_wdtimer(struct adf_accel_dev *accel_dev);170int adf_gen4_init_thd2arb_map(struct adf_accel_dev *accel_dev);171u16 adf_gen4_get_ring_to_svc_map(struct adf_accel_dev *accel_dev);172int adf_gen4_bank_quiesce_coal_timer(struct adf_accel_dev *accel_dev,173 u32 bank_idx, int timeout_ms);174int adf_gen4_bank_drain_start(struct adf_accel_dev *accel_dev,175 u32 bank_number, int timeout_us);176void adf_gen4_bank_drain_finish(struct adf_accel_dev *accel_dev,177 u32 bank_number);178int adf_gen4_bank_state_save(struct adf_accel_dev *accel_dev, u32 bank_number,179 struct bank_state *state);180int adf_gen4_bank_state_restore(struct adf_accel_dev *accel_dev,181 u32 bank_number, struct bank_state *state);182 183#endif184