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1/* SPDX-License-Identifier: GPL-2.0-only */2/* Copyright(c) 2023 Intel Corporation */3#ifndef ADF_GEN4_RAS_H_4#define ADF_GEN4_RAS_H_5 6#include <linux/bits.h>7 8struct adf_ras_ops;9 10/* ERRSOU0 Correctable error mask*/11#define ADF_GEN4_ERRSOU0_BIT BIT(0)12 13/* HI AE Correctable error log */14#define ADF_GEN4_HIAECORERRLOG_CPP0 0x41A30815 16/* HI AE Correctable error log enable */17#define ADF_GEN4_HIAECORERRLOGENABLE_CPP0 0x41A31818#define ADF_GEN4_ERRSOU1_HIAEUNCERRLOG_CPP0_BIT BIT(0)19#define ADF_GEN4_ERRSOU1_HICPPAGENTCMDPARERRLOG_BIT BIT(1)20#define ADF_GEN4_ERRSOU1_RIMEM_PARERR_STS_BIT BIT(2)21#define ADF_GEN4_ERRSOU1_TIMEM_PARERR_STS_BIT BIT(3)22#define ADF_GEN4_ERRSOU1_RIMISCSTS_BIT BIT(4)23 24#define ADF_GEN4_ERRSOU1_BITMASK ( \25 (ADF_GEN4_ERRSOU1_HIAEUNCERRLOG_CPP0_BIT) | \26 (ADF_GEN4_ERRSOU1_HICPPAGENTCMDPARERRLOG_BIT) | \27 (ADF_GEN4_ERRSOU1_RIMEM_PARERR_STS_BIT) | \28 (ADF_GEN4_ERRSOU1_TIMEM_PARERR_STS_BIT) | \29 (ADF_GEN4_ERRSOU1_RIMISCSTS_BIT))30 31/* HI AE Uncorrectable error log */32#define ADF_GEN4_HIAEUNCERRLOG_CPP0 0x41A30033 34/* HI AE Uncorrectable error log enable */35#define ADF_GEN4_HIAEUNCERRLOGENABLE_CPP0 0x41A32036 37/* HI CPP Agent Command parity error log */38#define ADF_GEN4_HICPPAGENTCMDPARERRLOG 0x41A31039 40/* HI CPP Agent Command parity error logging enable */41#define ADF_GEN4_HICPPAGENTCMDPARERRLOGENABLE 0x41A31442 43/* RI Memory parity error status register */44#define ADF_GEN4_RIMEM_PARERR_STS 0x41B12845 46/* RI Memory parity error reporting enable */47#define ADF_GEN4_RI_MEM_PAR_ERR_EN0 0x41B12C48 49/*50 * RI Memory parity error mask51 * BIT(0) - BIT(3) - ri_iosf_pdata_rxq[0:3] parity error52 * BIT(4) - ri_tlq_phdr parity error53 * BIT(5) - ri_tlq_pdata parity error54 * BIT(6) - ri_tlq_nphdr parity error55 * BIT(7) - ri_tlq_npdata parity error56 * BIT(8) - BIT(9) - ri_tlq_cplhdr[0:1] parity error57 * BIT(10) - BIT(17) - ri_tlq_cpldata[0:7] parity error58 * BIT(18) - set this bit to 1 to enable logging status to ri_mem_par_err_sts059 * BIT(19) - ri_cds_cmd_fifo parity error60 * BIT(20) - ri_obc_ricpl_fifo parity error61 * BIT(21) - ri_obc_tiricpl_fifo parity error62 * BIT(22) - ri_obc_cppcpl_fifo parity error63 * BIT(23) - ri_obc_pendcpl_fifo parity error64 * BIT(24) - ri_cpp_cmd_fifo parity error65 * BIT(25) - ri_cds_ticmd_fifo parity error66 * BIT(26) - riti_cmd_fifo parity error67 * BIT(27) - ri_int_msixtbl parity error68 * BIT(28) - ri_int_imstbl parity error69 * BIT(30) - ri_kpt_fuses parity error70 */71#define ADF_GEN4_RIMEM_PARERR_STS_UNCERR_BITMASK \72 (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(5) | \73 BIT(7) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | \74 BIT(14) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | \75 BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) | BIT(25) | \76 BIT(26) | BIT(27) | BIT(28) | BIT(30))77 78#define ADF_GEN4_RIMEM_PARERR_STS_FATAL_BITMASK \79 (BIT(4) | BIT(6) | BIT(8) | BIT(9))80 81/* TI CI parity status */82#define ADF_GEN4_TI_CI_PAR_STS 0x50060C83 84/* TI CI parity reporting mask */85#define ADF_GEN4_TI_CI_PAR_ERR_MASK 0x50060886 87/*88 * TI CI parity status mask89 * BIT(0) - CdCmdQ_sts patiry error status90 * BIT(1) - CdDataQ_sts parity error status91 * BIT(3) - CPP_SkidQ_sts parity error status92 * BIT(7) - CPP_SkidQ_sc_sts parity error status93 */94#define ADF_GEN4_TI_CI_PAR_STS_BITMASK \95 (BIT(0) | BIT(1) | BIT(3) | BIT(7))96 97/* TI PULLFUB parity status */98#define ADF_GEN4_TI_PULL0FUB_PAR_STS 0x50061899 100/* TI PULLFUB parity error reporting mask */101#define ADF_GEN4_TI_PULL0FUB_PAR_ERR_MASK 0x500614102 103/*104 * TI PULLFUB parity status mask105 * BIT(0) - TrnPullReqQ_sts parity status106 * BIT(1) - TrnSharedDataQ_sts parity status107 * BIT(2) - TrnPullReqDataQ_sts parity status108 * BIT(4) - CPP_CiPullReqQ_sts parity status109 * BIT(5) - CPP_TrnPullReqQ_sts parity status110 * BIT(6) - CPP_PullidQ_sts parity status111 * BIT(7) - CPP_WaitDataQ_sts parity status112 * BIT(8) - CPP_CdDataQ_sts parity status113 * BIT(9) - CPP_TrnDataQP0_sts parity status114 * BIT(10) - BIT(11) - CPP_TrnDataQRF[00:01]_sts parity status115 * BIT(12) - CPP_TrnDataQP1_sts parity status116 * BIT(13) - BIT(14) - CPP_TrnDataQRF[10:11]_sts parity status117 */118#define ADF_GEN4_TI_PULL0FUB_PAR_STS_BITMASK \119 (BIT(0) | BIT(1) | BIT(2) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | \120 BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14))121 122/* TI PUSHUB parity status */123#define ADF_GEN4_TI_PUSHFUB_PAR_STS 0x500630124 125/* TI PUSHFUB parity error reporting mask */126#define ADF_GEN4_TI_PUSHFUB_PAR_ERR_MASK 0x50062C127 128/*129 * TI PUSHUB parity status mask130 * BIT(0) - SbPushReqQ_sts parity status131 * BIT(1) - BIT(2) - SbPushDataQ[0:1]_sts parity status132 * BIT(4) - CPP_CdPushReqQ_sts parity status133 * BIT(5) - BIT(6) - CPP_CdPushDataQ[0:1]_sts parity status134 * BIT(7) - CPP_SbPushReqQ_sts parity status135 * BIT(8) - CPP_SbPushDataQP_sts parity status136 * BIT(9) - BIT(10) - CPP_SbPushDataQRF[0:1]_sts parity status137 */138#define ADF_GEN4_TI_PUSHFUB_PAR_STS_BITMASK \139 (BIT(0) | BIT(1) | BIT(2) | BIT(4) | BIT(5) | \140 BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10))141 142/* TI CD parity status */143#define ADF_GEN4_TI_CD_PAR_STS 0x50063C144 145/* TI CD parity error mask */146#define ADF_GEN4_TI_CD_PAR_ERR_MASK 0x500638147 148/*149 * TI CD parity status mask150 * BIT(0) - BIT(15) - CtxMdRam[0:15]_sts parity status151 * BIT(16) - Leaf2ClusterRam_sts parity status152 * BIT(17) - BIT(18) - Ring2LeafRam[0:1]_sts parity status153 * BIT(19) - VirtualQ_sts parity status154 * BIT(20) - DtRdQ_sts parity status155 * BIT(21) - DtWrQ_sts parity status156 * BIT(22) - RiCmdQ_sts parity status157 * BIT(23) - BypassQ_sts parity status158 * BIT(24) - DtRdQ_sc_sts parity status159 * BIT(25) - DtWrQ_sc_sts parity status160 */161#define ADF_GEN4_TI_CD_PAR_STS_BITMASK \162 (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | \163 BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | \164 BIT(14) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | \165 BIT(21) | BIT(22) | BIT(23) | BIT(24) | BIT(25))166 167/* TI TRNSB parity status */168#define ADF_GEN4_TI_TRNSB_PAR_STS 0x500648169 170/* TI TRNSB Parity error reporting mask */171#define ADF_GEN4_TI_TRNSB_PAR_ERR_MASK 0x500644172 173/*174 * TI TRNSB parity status mask175 * BIT(0) - TrnPHdrQP_sts parity status176 * BIT(1) - TrnPHdrQRF_sts parity status177 * BIT(2) - TrnPDataQP_sts parity status178 * BIT(3) - BIT(6) - TrnPDataQRF[0:3]_sts parity status179 * BIT(7) - TrnNpHdrQP_sts parity status180 * BIT(8) - BIT(9) - TrnNpHdrQRF[0:1]_sts parity status181 * BIT(10) - TrnCplHdrQ_sts parity status182 * BIT(11) - TrnPutObsReqQ_sts parity status183 * BIT(12) - TrnPushReqQ_sts parity status184 * BIT(13) - SbSplitIdRam_sts parity status185 * BIT(14) - SbReqCountQ_sts parity status186 * BIT(15) - SbCplTrkRam_sts parity status187 * BIT(16) - SbGetObsReqQ_sts parity status188 * BIT(17) - SbEpochIdQ_sts parity status189 * BIT(18) - SbAtCplHdrQ_sts parity status190 * BIT(19) - SbAtCplDataQ_sts parity status191 * BIT(20) - SbReqCountRam_sts parity status192 * BIT(21) - SbAtCplHdrQ_sc_sts parity status193 */194#define ADF_GEN4_TI_TRNSB_PAR_STS_BITMASK \195 (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | \196 BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12) | \197 BIT(13) | BIT(14) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | \198 BIT(19) | BIT(20) | BIT(21))199 200/* Status register to log misc error on RI */201#define ADF_GEN4_RIMISCSTS 0x41B1B8202 203/* Status control register to log misc RI error */204#define ADF_GEN4_RIMISCCTL 0x41B1BC205 206/*207 * ERRSOU2 bit mask208 * BIT(0) - SSM Interrupt Mask209 * BIT(1) - CFC on CPP. ORed of CFC Push error and Pull error210 * BIT(2) - BIT(4) - CPP attention interrupts, deprecated on gen4 devices211 * BIT(18) - PM interrupt212 */213#define ADF_GEN4_ERRSOU2_SSM_ERR_BIT BIT(0)214#define ADF_GEN4_ERRSOU2_CPP_CFC_ERR_STATUS_BIT BIT(1)215#define ADF_GEN4_ERRSOU2_CPP_CFC_ATT_INT_BITMASK \216 (BIT(2) | BIT(3) | BIT(4))217 218#define ADF_GEN4_ERRSOU2_PM_INT_BIT BIT(18)219 220#define ADF_GEN4_ERRSOU2_BITMASK \221 (ADF_GEN4_ERRSOU2_SSM_ERR_BIT | \222 ADF_GEN4_ERRSOU2_CPP_CFC_ERR_STATUS_BIT)223 224#define ADF_GEN4_ERRSOU2_DIS_BITMASK \225 (ADF_GEN4_ERRSOU2_SSM_ERR_BIT | \226 ADF_GEN4_ERRSOU2_CPP_CFC_ERR_STATUS_BIT | \227 ADF_GEN4_ERRSOU2_CPP_CFC_ATT_INT_BITMASK)228 229#define ADF_GEN4_IAINTSTATSSM 0x28230 231/* IAINTSTATSSM error bit mask definitions */232#define ADF_GEN4_IAINTSTATSSM_UERRSSMSH_BIT BIT(0)233#define ADF_GEN4_IAINTSTATSSM_CERRSSMSH_BIT BIT(1)234#define ADF_GEN4_IAINTSTATSSM_PPERR_BIT BIT(2)235#define ADF_GEN4_IAINTSTATSSM_SLICEHANG_ERR_BIT BIT(3)236#define ADF_GEN4_IAINTSTATSSM_SPPPARERR_BIT BIT(4)237#define ADF_GEN4_IAINTSTATSSM_SSMCPPERR_BIT BIT(5)238#define ADF_GEN4_IAINTSTATSSM_SSMSOFTERRORPARITY_BIT BIT(6)239#define ADF_GEN4_IAINTSTATSSM_SER_ERR_SSMSH_CERR_BIT BIT(7)240#define ADF_GEN4_IAINTSTATSSM_SER_ERR_SSMSH_UNCERR_BIT BIT(8)241 242#define ADF_GEN4_IAINTSTATSSM_BITMASK \243 (ADF_GEN4_IAINTSTATSSM_UERRSSMSH_BIT | \244 ADF_GEN4_IAINTSTATSSM_CERRSSMSH_BIT | \245 ADF_GEN4_IAINTSTATSSM_PPERR_BIT | \246 ADF_GEN4_IAINTSTATSSM_SLICEHANG_ERR_BIT | \247 ADF_GEN4_IAINTSTATSSM_SPPPARERR_BIT | \248 ADF_GEN4_IAINTSTATSSM_SSMCPPERR_BIT | \249 ADF_GEN4_IAINTSTATSSM_SSMSOFTERRORPARITY_BIT | \250 ADF_GEN4_IAINTSTATSSM_SER_ERR_SSMSH_CERR_BIT | \251 ADF_GEN4_IAINTSTATSSM_SER_ERR_SSMSH_UNCERR_BIT)252 253#define ADF_GEN4_UERRSSMSH 0x18254 255/*256 * UERRSSMSH error bit masks definitions257 *258 * BIT(0) - Indicates one uncorrectable error259 * BIT(15) - Indicates multiple uncorrectable errors260 * in device shared memory261 */262#define ADF_GEN4_UERRSSMSH_BITMASK (BIT(0) | BIT(15))263 264#define ADF_GEN4_UERRSSMSHAD 0x1C265 266#define ADF_GEN4_CERRSSMSH 0x10267 268/*269 * CERRSSMSH error bit270 * BIT(0) - Indicates one correctable error271 */272#define ADF_GEN4_CERRSSMSH_ERROR_BIT BIT(0)273 274#define ADF_GEN4_CERRSSMSHAD 0x14275 276/* SSM error handling features enable register */277#define ADF_GEN4_SSMFEATREN 0x198278 279/*280 * Disable SSM error detection and reporting features281 * enabled by device driver on RAS initialization282 *283 * following bits should be cleared :284 * BIT(4) - Disable parity for CPP parity285 * BIT(12) - Disable logging push/pull data error in pperr register.286 * BIT(16) - BIT(23) - Disable parity for SPPs287 * BIT(24) - BIT(27) - Disable parity for SPPs, if it's supported on the device.288 */289#define ADF_GEN4_SSMFEATREN_DIS_BITMASK \290 (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(5) | BIT(6) | BIT(7) | \291 BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(13) | BIT(14) | BIT(15))292 293#define ADF_GEN4_INTMASKSSM 0x0294 295/*296 * Error reporting mask in INTMASKSSM297 * BIT(0) - Shared memory uncorrectable interrupt mask298 * BIT(1) - Shared memory correctable interrupt mask299 * BIT(2) - PPERR interrupt mask300 * BIT(3) - CPP parity error Interrupt mask301 * BIT(4) - SSM interrupt generated by SER correctable error mask302 * BIT(5) - SSM interrupt generated by SER uncorrectable error303 * - not stop and scream - mask304 */305#define ADF_GEN4_INTMASKSSM_BITMASK \306 (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5))307 308/* CPP push or pull error */309#define ADF_GEN4_PPERR 0x8310 311#define ADF_GEN4_PPERR_BITMASK (BIT(0) | BIT(1))312 313#define ADF_GEN4_PPERRID 0xC314 315/* Slice hang handling related registers */316#define ADF_GEN4_SLICEHANGSTATUS_ATH_CPH 0x84317#define ADF_GEN4_SLICEHANGSTATUS_CPR_XLT 0x88318#define ADF_GEN4_SLICEHANGSTATUS_DCPR_UCS 0x90319#define ADF_GEN4_SLICEHANGSTATUS_WAT_WCP 0x8C320#define ADF_GEN4_SLICEHANGSTATUS_PKE 0x94321 322#define ADF_GEN4_SHINTMASKSSM_ATH_CPH 0xF0323#define ADF_GEN4_SHINTMASKSSM_CPR_XLT 0xF4324#define ADF_GEN4_SHINTMASKSSM_DCPR_UCS 0xFC325#define ADF_GEN4_SHINTMASKSSM_WAT_WCP 0xF8326#define ADF_GEN4_SHINTMASKSSM_PKE 0x100327 328/* SPP pull cmd parity err_*slice* CSR */329#define ADF_GEN4_SPPPULLCMDPARERR_ATH_CPH 0x1A4330#define ADF_GEN4_SPPPULLCMDPARERR_CPR_XLT 0x1A8331#define ADF_GEN4_SPPPULLCMDPARERR_DCPR_UCS 0x1B0332#define ADF_GEN4_SPPPULLCMDPARERR_PKE 0x1B4333#define ADF_GEN4_SPPPULLCMDPARERR_WAT_WCP 0x1AC334 335/* SPP pull data parity err_*slice* CSR */336#define ADF_GEN4_SPPPULLDATAPARERR_ATH_CPH 0x1BC337#define ADF_GEN4_SPPPULLDATAPARERR_CPR_XLT 0x1C0338#define ADF_GEN4_SPPPULLDATAPARERR_DCPR_UCS 0x1C8339#define ADF_GEN4_SPPPULLDATAPARERR_PKE 0x1CC340#define ADF_GEN4_SPPPULLDATAPARERR_WAT_WCP 0x1C4341 342/* SPP push cmd parity err_*slice* CSR */343#define ADF_GEN4_SPPPUSHCMDPARERR_ATH_CPH 0x1D4344#define ADF_GEN4_SPPPUSHCMDPARERR_CPR_XLT 0x1D8345#define ADF_GEN4_SPPPUSHCMDPARERR_DCPR_UCS 0x1E0346#define ADF_GEN4_SPPPUSHCMDPARERR_PKE 0x1E4347#define ADF_GEN4_SPPPUSHCMDPARERR_WAT_WCP 0x1DC348 349/* SPP push data parity err_*slice* CSR */350#define ADF_GEN4_SPPPUSHDATAPARERR_ATH_CPH 0x1EC351#define ADF_GEN4_SPPPUSHDATAPARERR_CPR_XLT 0x1F0352#define ADF_GEN4_SPPPUSHDATAPARERR_DCPR_UCS 0x1F8353#define ADF_GEN4_SPPPUSHDATAPARERR_PKE 0x1FC354#define ADF_GEN4_SPPPUSHDATAPARERR_WAT_WCP 0x1F4355 356/* Accelerator SPP parity error mask registers */357#define ADF_GEN4_SPPPARERRMSK_ATH_CPH 0x204358#define ADF_GEN4_SPPPARERRMSK_CPR_XLT 0x208359#define ADF_GEN4_SPPPARERRMSK_DCPR_UCS 0x210360#define ADF_GEN4_SPPPARERRMSK_PKE 0x214361#define ADF_GEN4_SPPPARERRMSK_WAT_WCP 0x20C362 363#define ADF_GEN4_SSMCPPERR 0x224364 365/*366 * Uncorrectable error mask in SSMCPPERR367 * BIT(0) - indicates CPP command parity error368 * BIT(1) - indicates CPP Main Push PPID parity error369 * BIT(2) - indicates CPP Main ePPID parity error370 * BIT(3) - indicates CPP Main push data parity error371 * BIT(4) - indicates CPP Main Pull PPID parity error372 * BIT(5) - indicates CPP target pull data parity error373 */374#define ADF_GEN4_SSMCPPERR_FATAL_BITMASK \375 (BIT(0) | BIT(1) | BIT(4))376 377#define ADF_GEN4_SSMCPPERR_UNCERR_BITMASK \378 (BIT(2) | BIT(3) | BIT(5))379 380#define ADF_GEN4_SSMSOFTERRORPARITY_SRC 0x9C381#define ADF_GEN4_SSMSOFTERRORPARITYMASK_SRC 0xB8382 383#define ADF_GEN4_SSMSOFTERRORPARITY_ATH_CPH 0xA0384#define ADF_GEN4_SSMSOFTERRORPARITYMASK_ATH_CPH 0xBC385 386#define ADF_GEN4_SSMSOFTERRORPARITY_CPR_XLT 0xA4387#define ADF_GEN4_SSMSOFTERRORPARITYMASK_CPR_XLT 0xC0388 389#define ADF_GEN4_SSMSOFTERRORPARITY_DCPR_UCS 0xAC390#define ADF_GEN4_SSMSOFTERRORPARITYMASK_DCPR_UCS 0xC8391 392#define ADF_GEN4_SSMSOFTERRORPARITY_PKE 0xB0393#define ADF_GEN4_SSMSOFTERRORPARITYMASK_PKE 0xCC394 395#define ADF_GEN4_SSMSOFTERRORPARITY_WAT_WCP 0xA8396#define ADF_GEN4_SSMSOFTERRORPARITYMASK_WAT_WCP 0xC4397 398/* RF parity error detected in SharedRAM */399#define ADF_GEN4_SSMSOFTERRORPARITY_SRC_BIT BIT(0)400 401#define ADF_GEN4_SER_ERR_SSMSH 0x44C402 403/*404 * Fatal error mask in SER_ERR_SSMSH405 * BIT(0) - Indicates an uncorrectable error has occurred in the406 * accelerator controller command RFs407 * BIT(2) - Parity error occurred in the bank SPP fifos408 * BIT(3) - Indicates Parity error occurred in following fifos in409 * the design410 * BIT(4) - Parity error occurred in flops in the design411 * BIT(5) - Uncorrectable error has occurred in the412 * target push and pull data register flop413 * BIT(7) - Indicates Parity error occurred in the Resource Manager414 * pending lock request fifos415 * BIT(8) - Indicates Parity error occurred in the Resource Manager416 * MECTX command queues logic417 * BIT(9) - Indicates Parity error occurred in the Resource Manager418 * MECTX sigdone fifo flops419 * BIT(10) - Indicates an uncorrectable error has occurred in the420 * Resource Manager MECTX command RFs421 * BIT(14) - Parity error occurred in Buffer Manager sigdone FIFO422 */423 #define ADF_GEN4_SER_ERR_SSMSH_FATAL_BITMASK \424 (BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(7) | \425 BIT(8) | BIT(9) | BIT(10) | BIT(14))426 427/*428 * Uncorrectable error mask in SER_ERR_SSMSH429 * BIT(12) Parity error occurred in Buffer Manager pool 0430 * BIT(13) Parity error occurred in Buffer Manager pool 1431 */432#define ADF_GEN4_SER_ERR_SSMSH_UNCERR_BITMASK \433 (BIT(12) | BIT(13))434 435/*436 * Correctable error mask in SER_ERR_SSMSH437 * BIT(1) - Indicates a correctable Error has occurred438 * in the slice controller command RFs439 * BIT(6) - Indicates a correctable Error has occurred in440 * the target push and pull data RFs441 * BIT(11) - Indicates an correctable Error has occurred in442 * the Resource Manager MECTX command RFs443 */444#define ADF_GEN4_SER_ERR_SSMSH_CERR_BITMASK \445 (BIT(1) | BIT(6) | BIT(11))446 447/* SSM shared memory SER error reporting mask */448#define ADF_GEN4_SER_EN_SSMSH 0x450449 450/*451 * SSM SER error reporting mask in SER_en_err_ssmsh452 * BIT(0) - Enables uncorrectable Error detection in :453 * 1) slice controller command RFs.454 * 2) target push/pull data registers455 * BIT(1) - Enables correctable Error detection in :456 * 1) slice controller command RFs457 * 2) target push/pull data registers458 * BIT(2) - Enables Parity error detection in459 * 1) bank SPP fifos460 * 2) gen4_pull_id_queue461 * 3) gen4_push_id_queue462 * 4) AE_pull_sigdn_fifo463 * 5) DT_push_sigdn_fifo464 * 6) slx_push_sigdn_fifo465 * 7) secure_push_cmd_fifo466 * 8) secure_pull_cmd_fifo467 * 9) Head register in FIFO wrapper468 * 10) current_cmd in individual push queue469 * 11) current_cmd in individual pull queue470 * 12) push_command_rxp arbitrated in ssm_push_cmd_queues471 * 13) pull_command_rxp arbitrated in ssm_pull_cmd_queues472 * BIT(3) - Enables uncorrectable Error detection in473 * the resource manager mectx cmd RFs.474 * BIT(4) - Enables correctable error detection in the Resource Manager475 * mectx command RFs476 * BIT(5) - Enables Parity error detection in477 * 1) resource manager lock request fifo478 * 2) mectx cmdqueues logic479 * 3) mectx sigdone fifo480 * BIT(6) - Enables Parity error detection in Buffer Manager pools481 * and sigdone fifo482 */483#define ADF_GEN4_SER_EN_SSMSH_BITMASK \484 (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6))485 486#define ADF_GEN4_CPP_CFC_ERR_STATUS 0x640C04487 488/*489 * BIT(1) - Indicates multiple CPP CFC errors490 * BIT(7) - Indicates CPP CFC command parity error type491 * BIT(8) - Indicated CPP CFC data parity error type492 */493#define ADF_GEN4_CPP_CFC_ERR_STATUS_MERR_BIT BIT(1)494#define ADF_GEN4_CPP_CFC_ERR_STATUS_CMDPAR_BIT BIT(7)495#define ADF_GEN4_CPP_CFC_ERR_STATUS_DATAPAR_BIT BIT(8)496 497/*498 * BIT(0) - Enables CFC to detect and log push/pull data error499 * BIT(1) - Enables CFC to generate interrupt to PCIEP for CPP error500 * BIT(4) - When 1 Parity detection is disabled501 * BIT(5) - When 1 Parity detection is disabled on CPP command bus502 * BIT(6) - When 1 Parity detection is disabled on CPP push/pull bus503 * BIT(9) - When 1 RF parity error detection is disabled504 */505#define ADF_GEN4_CPP_CFC_ERR_CTRL_BITMASK (BIT(0) | BIT(1))506 507#define ADF_GEN4_CPP_CFC_ERR_CTRL_DIS_BITMASK \508 (BIT(4) | BIT(5) | BIT(6) | BIT(9) | BIT(10))509 510#define ADF_GEN4_CPP_CFC_ERR_CTRL 0x640C00511 512/*513 * BIT(0) - Clears bit(0) of ADF_GEN4_CPP_CFC_ERR_STATUS514 * when an error is reported on CPP515 * BIT(1) - Clears bit(1) of ADF_GEN4_CPP_CFC_ERR_STATUS516 * when multiple errors are reported on CPP517 * BIT(2) - Clears bit(2) of ADF_GEN4_CPP_CFC_ERR_STATUS518 * when attention interrupt is reported519 */520#define ADF_GEN4_CPP_CFC_ERR_STATUS_CLR_BITMASK (BIT(0) | BIT(1) | BIT(2))521#define ADF_GEN4_CPP_CFC_ERR_STATUS_CLR 0x640C08522 523#define ADF_GEN4_CPP_CFC_ERR_PPID_LO 0x640C0C524#define ADF_GEN4_CPP_CFC_ERR_PPID_HI 0x640C10525 526/* Exception reporting in QAT SSM CMP */527#define ADF_GEN4_EXPRPSSMCPR 0x2000528 529/*530 * Uncorrectable error mask in EXPRPSSMCPR531 * BIT(2) - Hard fatal error532 * BIT(16) - Parity error detected in CPR Push FIFO533 * BIT(17) - Parity error detected in CPR Pull FIFO534 * BIT(18) - Parity error detected in CPR Hash Table535 * BIT(19) - Parity error detected in CPR History Buffer Copy 0536 * BIT(20) - Parity error detected in CPR History Buffer Copy 1537 * BIT(21) - Parity error detected in CPR History Buffer Copy 2538 * BIT(22) - Parity error detected in CPR History Buffer Copy 3539 * BIT(23) - Parity error detected in CPR History Buffer Copy 4540 * BIT(24) - Parity error detected in CPR History Buffer Copy 5541 * BIT(25) - Parity error detected in CPR History Buffer Copy 6542 * BIT(26) - Parity error detected in CPR History Buffer Copy 7543 */544#define ADF_GEN4_EXPRPSSMCPR_UNCERR_BITMASK \545 (BIT(2) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | \546 BIT(21) | BIT(22) | BIT(23) | BIT(24) | BIT(25) | BIT(26))547 548/* Exception reporting in QAT SSM XLT */549#define ADF_GEN4_EXPRPSSMXLT 0xA000550 551/*552 * Uncorrectable error mask in EXPRPSSMXLT553 * BIT(2) - If set, an Uncorrectable Error event occurred554 * BIT(16) - Parity error detected in XLT Push FIFO555 * BIT(17) - Parity error detected in XLT Pull FIFO556 * BIT(18) - Parity error detected in XLT HCTB0557 * BIT(19) - Parity error detected in XLT HCTB1558 * BIT(20) - Parity error detected in XLT HCTB2559 * BIT(21) - Parity error detected in XLT HCTB3560 * BIT(22) - Parity error detected in XLT CBCL561 * BIT(23) - Parity error detected in XLT LITPTR562 */563#define ADF_GEN4_EXPRPSSMXLT_UNCERR_BITMASK \564 (BIT(2) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | \565 BIT(22) | BIT(23))566 567/*568 * Correctable error mask in EXPRPSSMXLT569 * BIT(3) - Correctable error event occurred.570 */571#define ADF_GEN4_EXPRPSSMXLT_CERR_BIT BIT(3)572 573/* Exception reporting in QAT SSM DCMP */574#define ADF_GEN4_EXPRPSSMDCPR(_n_) (0x12000 + (_n_) * 0x80)575 576/*577 * Uncorrectable error mask in EXPRPSSMDCPR578 * BIT(2) - Even hard fatal error579 * BIT(4) - Odd hard fatal error580 * BIT(6) - decode soft error581 * BIT(16) - Parity error detected in CPR Push FIFO582 * BIT(17) - Parity error detected in CPR Pull FIFO583 * BIT(18) - Parity error detected in the Input Buffer584 * BIT(19) - symbuf0parerr585 * Parity error detected in CPR Push FIFO586 * BIT(20) - symbuf1parerr587 * Parity error detected in CPR Push FIFO588 */589#define ADF_GEN4_EXPRPSSMDCPR_UNCERR_BITMASK \590 (BIT(2) | BIT(4) | BIT(6) | BIT(16) | BIT(17) | \591 BIT(18) | BIT(19) | BIT(20))592 593/*594 * Correctable error mask in EXPRPSSMDCPR595 * BIT(3) - Even ecc correctable error596 * BIT(5) - Odd ecc correctable error597 */598#define ADF_GEN4_EXPRPSSMDCPR_CERR_BITMASK (BIT(3) | BIT(5))599 600#define ADF_GEN4_DCPR_SLICES_NUM 3601 602/*603 * ERRSOU3 bit masks604 * BIT(0) - indicates error Response Order Overflow and/or BME error605 * BIT(1) - indicates RI push/pull error606 * BIT(2) - indicates TI push/pull error607 * BIT(3) - indicates ARAM correctable error608 * BIT(4) - indicates ARAM uncorrectable error609 * BIT(5) - indicates TI pull parity error610 * BIT(6) - indicates RI push parity error611 * BIT(7) - indicates VFLR interrupt612 * BIT(8) - indicates ring pair interrupts for ATU detected fault613 * BIT(9) - indicates error when accessing RLT block614 */615#define ADF_GEN4_ERRSOU3_TIMISCSTS_BIT BIT(0)616#define ADF_GEN4_ERRSOU3_RICPPINTSTS_BITMASK (BIT(1) | BIT(6))617#define ADF_GEN4_ERRSOU3_TICPPINTSTS_BITMASK (BIT(2) | BIT(5))618#define ADF_GEN4_ERRSOU3_REG_ARAMCERR_BIT BIT(3)619#define ADF_GEN4_ERRSOU3_REG_ARAMUERR_BIT BIT(4)620#define ADF_GEN4_ERRSOU3_VFLRNOTIFY_BIT BIT(7)621#define ADF_GEN4_ERRSOU3_ATUFAULTSTATUS_BIT BIT(8)622#define ADF_GEN4_ERRSOU3_RLTERROR_BIT BIT(9)623 624#define ADF_GEN4_ERRSOU3_BITMASK ( \625 (ADF_GEN4_ERRSOU3_TIMISCSTS_BIT) | \626 (ADF_GEN4_ERRSOU3_RICPPINTSTS_BITMASK) | \627 (ADF_GEN4_ERRSOU3_TICPPINTSTS_BITMASK) | \628 (ADF_GEN4_ERRSOU3_REG_ARAMCERR_BIT) | \629 (ADF_GEN4_ERRSOU3_REG_ARAMUERR_BIT) | \630 (ADF_GEN4_ERRSOU3_VFLRNOTIFY_BIT) | \631 (ADF_GEN4_ERRSOU3_ATUFAULTSTATUS_BIT) | \632 (ADF_GEN4_ERRSOU3_RLTERROR_BIT))633 634/* TI Misc status register */635#define ADF_GEN4_TIMISCSTS 0x50054C636 637/* TI Misc error reporting mask */638#define ADF_GEN4_TIMISCCTL 0x500548639 640/*641 * TI Misc error reporting control mask642 * BIT(0) - Enables error detection and logging in TIMISCSTS register643 * BIT(1) - It has effect only when SRIOV enabled, this bit is 0 by default644 * BIT(2) - Enables the D-F-x counter within the dispatch arbiter645 * to start based on the command triggered from646 * BIT(30) - Disables VFLR functionality647 * By setting this bit will revert to CPM1.x functionality648 * bits 1, 2 and 30 value should be preserved and not meant to be changed649 * within RAS.650 */651#define ADF_GEN4_TIMISCCTL_BIT BIT(0)652#define ADF_GEN4_TIMSCCTL_RELAY_BITMASK (BIT(1) | BIT(2) | BIT(30))653 654/* RI CPP interface status register */655#define ADF_GEN4_RICPPINTSTS 0x41A330656 657/*658 * Uncorrectable error mask in RICPPINTSTS register659 * BIT(0) - RI asserted the CPP error signal during a push660 * BIT(1) - RI detected the CPP error signal asserted during a pull661 * BIT(2) - RI detected a push data parity error662 * BIT(3) - RI detected a push valid parity error663 */664#define ADF_GEN4_RICPPINTSTS_BITMASK \665 (BIT(0) | BIT(1) | BIT(2) | BIT(3))666 667/* RI CPP interface status register control */668#define ADF_GEN4_RICPPINTCTL 0x41A32C669 670/*671 * Control bit mask for RICPPINTCTL register672 * BIT(0) - value of 1 enables error detection and reporting673 * on the RI CPP Push interface674 * BIT(1) - value of 1 enables error detection and reporting675 * on the RI CPP Pull interface676 * BIT(2) - value of 1 enables error detection and reporting677 * on the RI Parity678 * BIT(3) - value of 1 enable checking parity on CPP679 * BIT(4) - value of 1 enables the stop feature of the stop and stream680 * for all RI CPP Command RFs681 */682#define ADF_GEN4_RICPPINTCTL_BITMASK \683 (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4))684 685/* Push ID of the command which triggered the transaction error on RI */686#define ADF_GEN4_RIERRPUSHID 0x41A334687 688/* Pull ID of the command which triggered the transaction error on RI */689#define ADF_GEN4_RIERRPULLID 0x41A338690 691/* TI CPP interface status register */692#define ADF_GEN4_TICPPINTSTS 0x50053C693 694/*695 * Uncorrectable error mask in TICPPINTSTS register696 * BIT(0) - value of 1 indicates that the TI asserted697 * the CPP error signal during a push698 * BIT(1) - value of 1 indicates that the TI detected699 * the CPP error signal asserted during a pull700 * BIT(2) - value of 1 indicates that the TI detected701 * a pull data parity error702 */703#define ADF_GEN4_TICPPINTSTS_BITMASK \704 (BIT(0) | BIT(1) | BIT(2))705 706/* TI CPP interface status register control */707#define ADF_GEN4_TICPPINTCTL 0x500538708 709/*710 * Control bit mask for TICPPINTCTL register711 * BIT(0) - value of 1 enables error detection and reporting on712 * the TI CPP Push interface713 * BIT(1) - value of 1 enables error detection and reporting on714 * the TI CPP Push interface715 * BIT(2) - value of 1 enables parity error detection and logging on716 * the TI CPP Pull interface717 * BIT(3) - value of 1 enables CPP CMD and Pull Data parity checking718 * BIT(4) - value of 1 enables TI stop part of stop and scream mode on719 * CPP/RF Parity error720 */721#define ADF_GEN4_TICPPINTCTL_BITMASK \722 (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4))723 724/* Push ID of the command which triggered the transaction error on TI */725#define ADF_GEN4_TIERRPUSHID 0x500540726 727/* Pull ID of the command which triggered the transaction error on TI */728#define ADF_GEN4_TIERRPULLID 0x500544729 730/* Correctable error in ARAM agent register */731#define ADF_GEN4_REG_ARAMCERR 0x1700732 733#define ADF_GEN4_REG_ARAMCERR_BIT BIT(0)734 735/*736 * Correctable error enablement in ARAM bit mask737 * BIT(3) - enable ARAM RAM to fix and log correctable error738 * BIT(26) - enables ARAM agent to generate interrupt for correctable error739 */740#define ADF_GEN4_REG_ARAMCERR_EN_BITMASK (BIT(3) | BIT(26))741 742/* Correctable error address in ARAM agent register */743#define ADF_GEN4_REG_ARAMCERRAD 0x1708744 745/* Uncorrectable error in ARAM agent register */746#define ADF_GEN4_REG_ARAMUERR 0x1704747 748/*749 * ARAM error bit mask750 * BIT(0) - indicates error logged in ARAMCERR or ARAMUCERR751 * BIT(18) - indicates uncorrectable multiple errors in ARAM agent752 */753#define ADF_GEN4_REG_ARAMUERR_ERROR_BIT BIT(0)754#define ADF_GEN4_REG_ARAMUERR_MULTI_ERRORS_BIT BIT(18)755 756/*757 * Uncorrectable error enablement in ARAM bit mask758 * BIT(3) - enable ARAM RAM to fix and log uncorrectable error759 * BIT(19) - enables ARAM agent to generate interrupt for uncorrectable error760 */761#define ADF_GEN4_REG_ARAMUERR_EN_BITMASK (BIT(3) | BIT(19))762 763/* Unorrectable error address in ARAM agent register */764#define ADF_GEN4_REG_ARAMUERRAD 0x170C765 766/* Uncorrectable error transaction push/pull ID registers*/767#define ADF_GEN4_REG_ERRPPID_LO 0x1714768#define ADF_GEN4_REG_ERRPPID_HI 0x1718769 770/* ARAM ECC block error enablement */771#define ADF_GEN4_REG_ARAMCERRUERR_EN 0x1808772 773/*774 * ARAM ECC block error control bit masks775 * BIT(0) - enable ARAM CD ECC block error detecting776 * BIT(1) - enable ARAM pull request ECC error detecting777 * BIT(2) - enable ARAM command dispatch ECC error detecting778 * BIT(3) - enable ARAM read datapath push ECC error detecting779 * BIT(4) - enable ARAM read datapath pull ECC error detecting780 * BIT(5) - enable ARAM RMW ECC error detecting781 * BIT(6) - enable ARAM write datapath RMW ECC error detecting782 * BIT(7) - enable ARAM write datapath ECC error detecting783 */784#define ADF_GEN4_REG_ARAMCERRUERR_EN_BITMASK \785 (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | \786 BIT(5) | BIT(6) | BIT(7))787 788/* ARAM misc memory target error registers*/789#define ADF_GEN4_REG_CPPMEMTGTERR 0x1710790 791/*792 * ARAM misc memory target error bit masks793 * BIT(0) - indicates an error in ARAM target memory794 * BIT(1) - indicates multiple errors in ARAM target memory795 * BIT(4) - indicates pull error in ARAM target memory796 * BIT(5) - indicates parity pull error in ARAM target memory797 * BIT(6) - indicates push error in ARAM target memory798 */799#define ADF_GEN4_REG_CPPMEMTGTERR_BITMASK \800 (BIT(0) | BIT(4) | BIT(5) | BIT(6))801 802#define ADF_GEN4_REG_CPPMEMTGTERR_MULTI_ERRORS_BIT BIT(1)803 804/*805 * ARAM misc memory target error enablement mask806 * BIT(2) - enables CPP memory to detect and log push/pull data error807 * BIT(7) - enables push/pull error to generate interrupts to RI808 * BIT(8) - enables ARAM to check parity on pull data and CPP command buses809 * BIT(9) - enables ARAM to autopush to AE when push/parity error is detected810 * on lookaside DT811 */812#define ADF_GEN4_REG_CPPMEMTGTERR_EN_BITMASK \813 (BIT(2) | BIT(7) | BIT(8) | BIT(9))814 815/* ATU fault status register */816#define ADF_GEN4_ATUFAULTSTATUS(i) (0x506000 + ((i) * 0x4))817 818#define ADF_GEN4_ATUFAULTSTATUS_BIT BIT(0)819 820/* Command Parity error detected on IOSFP Command to QAT */821#define ADF_GEN4_RIMISCSTS_BIT BIT(0)822 823void adf_gen4_init_ras_ops(struct adf_ras_ops *ras_ops);824 825#endif /* ADF_GEN4_RAS_H_ */826