327 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.4 */5 6#ifndef _REGS_V5_H_7#define _REGS_V5_H_8 9#include <linux/bitops.h>10 11#define REG_VERSION 0x00012#define REG_STATUS 0x10013#define REG_STATUS2 0x10414#define REG_ENGINES_AVAIL 0x10815#define REG_FIFO_SIZES 0x10c16#define REG_SEG_SIZE 0x11017#define REG_GOPROC 0x12018#define REG_ENCR_SEG_CFG 0x20019#define REG_ENCR_SEG_SIZE 0x20420#define REG_ENCR_SEG_START 0x20821#define REG_CNTR0_IV0 0x20c22#define REG_CNTR1_IV1 0x21023#define REG_CNTR2_IV2 0x21424#define REG_CNTR3_IV3 0x21825#define REG_CNTR_MASK 0x21C26#define REG_ENCR_CCM_INT_CNTR0 0x22027#define REG_ENCR_CCM_INT_CNTR1 0x22428#define REG_ENCR_CCM_INT_CNTR2 0x22829#define REG_ENCR_CCM_INT_CNTR3 0x22c30#define REG_ENCR_XTS_DU_SIZE 0x23031#define REG_CNTR_MASK2 0x23432#define REG_CNTR_MASK1 0x23833#define REG_CNTR_MASK0 0x23c34#define REG_AUTH_SEG_CFG 0x30035#define REG_AUTH_SEG_SIZE 0x30436#define REG_AUTH_SEG_START 0x30837#define REG_AUTH_IV0 0x31038#define REG_AUTH_IV1 0x31439#define REG_AUTH_IV2 0x31840#define REG_AUTH_IV3 0x31c41#define REG_AUTH_IV4 0x32042#define REG_AUTH_IV5 0x32443#define REG_AUTH_IV6 0x32844#define REG_AUTH_IV7 0x32c45#define REG_AUTH_IV8 0x33046#define REG_AUTH_IV9 0x33447#define REG_AUTH_IV10 0x33848#define REG_AUTH_IV11 0x33c49#define REG_AUTH_IV12 0x34050#define REG_AUTH_IV13 0x34451#define REG_AUTH_IV14 0x34852#define REG_AUTH_IV15 0x34c53#define REG_AUTH_INFO_NONCE0 0x35054#define REG_AUTH_INFO_NONCE1 0x35455#define REG_AUTH_INFO_NONCE2 0x35856#define REG_AUTH_INFO_NONCE3 0x35c57#define REG_AUTH_BYTECNT0 0x39058#define REG_AUTH_BYTECNT1 0x39459#define REG_AUTH_BYTECNT2 0x39860#define REG_AUTH_BYTECNT3 0x39c61#define REG_AUTH_EXP_MAC0 0x3a062#define REG_AUTH_EXP_MAC1 0x3a463#define REG_AUTH_EXP_MAC2 0x3a864#define REG_AUTH_EXP_MAC3 0x3ac65#define REG_AUTH_EXP_MAC4 0x3b066#define REG_AUTH_EXP_MAC5 0x3b467#define REG_AUTH_EXP_MAC6 0x3b868#define REG_AUTH_EXP_MAC7 0x3bc69#define REG_CONFIG 0x40070#define REG_GOPROC_QC_KEY 0x100071#define REG_GOPROC_OEM_KEY 0x200072#define REG_ENCR_KEY0 0x300073#define REG_ENCR_KEY1 0x300474#define REG_ENCR_KEY2 0x300875#define REG_ENCR_KEY3 0x300c76#define REG_ENCR_KEY4 0x301077#define REG_ENCR_KEY5 0x301478#define REG_ENCR_KEY6 0x301879#define REG_ENCR_KEY7 0x301c80#define REG_ENCR_XTS_KEY0 0x302081#define REG_ENCR_XTS_KEY1 0x302482#define REG_ENCR_XTS_KEY2 0x302883#define REG_ENCR_XTS_KEY3 0x302c84#define REG_ENCR_XTS_KEY4 0x303085#define REG_ENCR_XTS_KEY5 0x303486#define REG_ENCR_XTS_KEY6 0x303887#define REG_ENCR_XTS_KEY7 0x303c88#define REG_AUTH_KEY0 0x304089#define REG_AUTH_KEY1 0x304490#define REG_AUTH_KEY2 0x304891#define REG_AUTH_KEY3 0x304c92#define REG_AUTH_KEY4 0x305093#define REG_AUTH_KEY5 0x305494#define REG_AUTH_KEY6 0x305895#define REG_AUTH_KEY7 0x305c96#define REG_AUTH_KEY8 0x306097#define REG_AUTH_KEY9 0x306498#define REG_AUTH_KEY10 0x306899#define REG_AUTH_KEY11 0x306c100#define REG_AUTH_KEY12 0x3070101#define REG_AUTH_KEY13 0x3074102#define REG_AUTH_KEY14 0x3078103#define REG_AUTH_KEY15 0x307c104 105/* Register bits - REG_VERSION */106#define CORE_STEP_REV_SHIFT 0107#define CORE_STEP_REV_MASK GENMASK(15, 0)108#define CORE_MINOR_REV_SHIFT 16109#define CORE_MINOR_REV_MASK GENMASK(23, 16)110#define CORE_MAJOR_REV_SHIFT 24111#define CORE_MAJOR_REV_MASK GENMASK(31, 24)112 113/* Register bits - REG_STATUS */114#define MAC_FAILED_SHIFT 31115#define DOUT_SIZE_AVAIL_SHIFT 26116#define DOUT_SIZE_AVAIL_MASK GENMASK(30, 26)117#define DIN_SIZE_AVAIL_SHIFT 21118#define DIN_SIZE_AVAIL_MASK GENMASK(25, 21)119#define HSD_ERR_SHIFT 20120#define ACCESS_VIOL_SHIFT 19121#define PIPE_ACTIVE_ERR_SHIFT 18122#define CFG_CHNG_ERR_SHIFT 17123#define DOUT_ERR_SHIFT 16124#define DIN_ERR_SHIFT 15125#define AXI_ERR_SHIFT 14126#define CRYPTO_STATE_SHIFT 10127#define CRYPTO_STATE_MASK GENMASK(13, 10)128#define ENCR_BUSY_SHIFT 9129#define AUTH_BUSY_SHIFT 8130#define DOUT_INTR_SHIFT 7131#define DIN_INTR_SHIFT 6132#define OP_DONE_INTR_SHIFT 5133#define ERR_INTR_SHIFT 4134#define DOUT_RDY_SHIFT 3135#define DIN_RDY_SHIFT 2136#define OPERATION_DONE_SHIFT 1137#define SW_ERR_SHIFT 0138 139/* Register bits - REG_STATUS2 */140#define AXI_EXTRA_SHIFT 1141#define LOCKED_SHIFT 2142 143/* Register bits - REG_CONFIG */144#define REQ_SIZE_SHIFT 17145#define REQ_SIZE_MASK GENMASK(20, 17)146#define REQ_SIZE_ENUM_1_BEAT 0147#define REQ_SIZE_ENUM_2_BEAT 1148#define REQ_SIZE_ENUM_3_BEAT 2149#define REQ_SIZE_ENUM_4_BEAT 3150#define REQ_SIZE_ENUM_5_BEAT 4151#define REQ_SIZE_ENUM_6_BEAT 5152#define REQ_SIZE_ENUM_7_BEAT 6153#define REQ_SIZE_ENUM_8_BEAT 7154#define REQ_SIZE_ENUM_9_BEAT 8155#define REQ_SIZE_ENUM_10_BEAT 9156#define REQ_SIZE_ENUM_11_BEAT 10157#define REQ_SIZE_ENUM_12_BEAT 11158#define REQ_SIZE_ENUM_13_BEAT 12159#define REQ_SIZE_ENUM_14_BEAT 13160#define REQ_SIZE_ENUM_15_BEAT 14161#define REQ_SIZE_ENUM_16_BEAT 15162 163#define MAX_QUEUED_REQ_SHIFT 14164#define MAX_QUEUED_REQ_MASK GENMASK(24, 16)165#define ENUM_1_QUEUED_REQS 0166#define ENUM_2_QUEUED_REQS 1167#define ENUM_3_QUEUED_REQS 2168 169#define IRQ_ENABLES_SHIFT 10170#define IRQ_ENABLES_MASK GENMASK(13, 10)171 172#define LITTLE_ENDIAN_MODE_SHIFT 9173#define PIPE_SET_SELECT_SHIFT 5174#define PIPE_SET_SELECT_MASK GENMASK(8, 5)175 176#define HIGH_SPD_EN_N_SHIFT 4177#define MASK_DOUT_INTR_SHIFT 3178#define MASK_DIN_INTR_SHIFT 2179#define MASK_OP_DONE_INTR_SHIFT 1180#define MASK_ERR_INTR_SHIFT 0181 182/* Register bits - REG_AUTH_SEG_CFG */183#define COMP_EXP_MAC_SHIFT 24184#define COMP_EXP_MAC_DISABLED 0185#define COMP_EXP_MAC_ENABLED 1186 187#define F9_DIRECTION_SHIFT 23188#define F9_DIRECTION_UPLINK 0189#define F9_DIRECTION_DOWNLINK 1190 191#define AUTH_NONCE_NUM_WORDS_SHIFT 20192#define AUTH_NONCE_NUM_WORDS_MASK GENMASK(22, 20)193 194#define USE_PIPE_KEY_AUTH_SHIFT 19195#define USE_HW_KEY_AUTH_SHIFT 18196#define AUTH_FIRST_SHIFT 17197#define AUTH_LAST_SHIFT 16198 199#define AUTH_POS_SHIFT 14200#define AUTH_POS_MASK GENMASK(15, 14)201#define AUTH_POS_BEFORE 0202#define AUTH_POS_AFTER 1203 204#define AUTH_SIZE_SHIFT 9205#define AUTH_SIZE_MASK GENMASK(13, 9)206#define AUTH_SIZE_SHA1 0207#define AUTH_SIZE_SHA256 1208#define AUTH_SIZE_ENUM_1_BYTES 0209#define AUTH_SIZE_ENUM_2_BYTES 1210#define AUTH_SIZE_ENUM_3_BYTES 2211#define AUTH_SIZE_ENUM_4_BYTES 3212#define AUTH_SIZE_ENUM_5_BYTES 4213#define AUTH_SIZE_ENUM_6_BYTES 5214#define AUTH_SIZE_ENUM_7_BYTES 6215#define AUTH_SIZE_ENUM_8_BYTES 7216#define AUTH_SIZE_ENUM_9_BYTES 8217#define AUTH_SIZE_ENUM_10_BYTES 9218#define AUTH_SIZE_ENUM_11_BYTES 10219#define AUTH_SIZE_ENUM_12_BYTES 11220#define AUTH_SIZE_ENUM_13_BYTES 12221#define AUTH_SIZE_ENUM_14_BYTES 13222#define AUTH_SIZE_ENUM_15_BYTES 14223#define AUTH_SIZE_ENUM_16_BYTES 15224 225#define AUTH_MODE_SHIFT 6226#define AUTH_MODE_MASK GENMASK(8, 6)227#define AUTH_MODE_HASH 0228#define AUTH_MODE_HMAC 1229#define AUTH_MODE_CCM 0230#define AUTH_MODE_CMAC 1231 232#define AUTH_KEY_SIZE_SHIFT 3233#define AUTH_KEY_SIZE_MASK GENMASK(5, 3)234#define AUTH_KEY_SZ_AES128 0235#define AUTH_KEY_SZ_AES256 2236 237#define AUTH_ALG_SHIFT 0238#define AUTH_ALG_MASK GENMASK(2, 0)239#define AUTH_ALG_NONE 0240#define AUTH_ALG_SHA 1241#define AUTH_ALG_AES 2242#define AUTH_ALG_KASUMI 3243#define AUTH_ALG_SNOW3G 4244#define AUTH_ALG_ZUC 5245 246/* Register bits - REG_ENCR_XTS_DU_SIZE */247#define ENCR_XTS_DU_SIZE_SHIFT 0248#define ENCR_XTS_DU_SIZE_MASK GENMASK(19, 0)249 250/* Register bits - REG_ENCR_SEG_CFG */251#define F8_KEYSTREAM_ENABLE_SHIFT 17252#define F8_KEYSTREAM_DISABLED 0253#define F8_KEYSTREAM_ENABLED 1254 255#define F8_DIRECTION_SHIFT 16256#define F8_DIRECTION_UPLINK 0257#define F8_DIRECTION_DOWNLINK 1258 259#define USE_PIPE_KEY_ENCR_SHIFT 15260#define USE_PIPE_KEY_ENCR_ENABLED 1261#define USE_KEY_REGISTERS 0262 263#define USE_HW_KEY_ENCR_SHIFT 14264#define USE_KEY_REG 0265#define USE_HW_KEY 1266 267#define LAST_CCM_SHIFT 13268#define LAST_CCM_XFR 1269#define INTERM_CCM_XFR 0270 271#define CNTR_ALG_SHIFT 11272#define CNTR_ALG_MASK GENMASK(12, 11)273#define CNTR_ALG_NIST 0274 275#define ENCODE_SHIFT 10276 277#define ENCR_MODE_SHIFT 6278#define ENCR_MODE_MASK GENMASK(9, 6)279#define ENCR_MODE_ECB 0280#define ENCR_MODE_CBC 1281#define ENCR_MODE_CTR 2282#define ENCR_MODE_XTS 3283#define ENCR_MODE_CCM 4284 285#define ENCR_KEY_SZ_SHIFT 3286#define ENCR_KEY_SZ_MASK GENMASK(5, 3)287#define ENCR_KEY_SZ_DES 0288#define ENCR_KEY_SZ_3DES 1289#define ENCR_KEY_SZ_AES128 0290#define ENCR_KEY_SZ_AES256 2291 292#define ENCR_ALG_SHIFT 0293#define ENCR_ALG_MASK GENMASK(2, 0)294#define ENCR_ALG_NONE 0295#define ENCR_ALG_DES 1296#define ENCR_ALG_AES 2297#define ENCR_ALG_KASUMI 4298#define ENCR_ALG_SNOW_3G 5299#define ENCR_ALG_ZUC 6300 301/* Register bits - REG_GOPROC */302#define GO_SHIFT 0303#define CLR_CNTXT_SHIFT 1304#define RESULTS_DUMP_SHIFT 2305 306/* Register bits - REG_ENGINES_AVAIL */307#define ENCR_AES_SEL_SHIFT 0308#define DES_SEL_SHIFT 1309#define ENCR_SNOW3G_SEL_SHIFT 2310#define ENCR_KASUMI_SEL_SHIFT 3311#define SHA_SEL_SHIFT 4312#define SHA512_SEL_SHIFT 5313#define AUTH_AES_SEL_SHIFT 6314#define AUTH_SNOW3G_SEL_SHIFT 7315#define AUTH_KASUMI_SEL_SHIFT 8316#define BAM_PIPE_SETS_SHIFT 9317#define BAM_PIPE_SETS_MASK GENMASK(12, 9)318#define AXI_WR_BEATS_SHIFT 13319#define AXI_WR_BEATS_MASK GENMASK(18, 13)320#define AXI_RD_BEATS_SHIFT 19321#define AXI_RD_BEATS_MASK GENMASK(24, 19)322#define ENCR_ZUC_SEL_SHIFT 26323#define AUTH_ZUC_SEL_SHIFT 27324#define ZUC_ENABLE_SHIFT 28325 326#endif /* _REGS_V5_H_ */327