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1# SPDX-License-Identifier: GPL-2.0-only2menuconfig CXL_BUS3 tristate "CXL (Compute Express Link) Devices Support"4 depends on PCI5 select FW_LOADER6 select FW_UPLOAD7 select PCI_DOE8 select FIRMWARE_TABLE9 select NUMA_KEEP_MEMINFO if NUMA_MEMBLKS10 help11 CXL is a bus that is electrically compatible with PCI Express, but12 layers three protocols on that signalling (CXL.io, CXL.cache, and13 CXL.mem). The CXL.cache protocol allows devices to hold cachelines14 locally, the CXL.mem protocol allows devices to be fully coherent15 memory targets, the CXL.io protocol is equivalent to PCI Express.16 Say 'y' to enable support for the configuration and management of17 devices supporting these protocols.18 19if CXL_BUS20 21config CXL_PCI22 tristate "PCI manageability"23 default CXL_BUS24 help25 The CXL specification defines a "CXL memory device" sub-class in the26 PCI "memory controller" base class of devices. Device's identified by27 this class code provide support for volatile and / or persistent28 memory to be mapped into the system address map (Host-managed Device29 Memory (HDM)).30 31 Say 'y/m' to enable a driver that will attach to CXL memory expander32 devices enumerated by the memory device class code for configuration33 and management primarily via the mailbox interface. See Chapter 2.334 Type 3 CXL Device in the CXL 2.0 specification for more details.35 36 If unsure say 'm'.37 38config CXL_MEM_RAW_COMMANDS39 bool "RAW Command Interface for Memory Devices"40 depends on CXL_PCI41 help42 Enable CXL RAW command interface.43 44 The CXL driver ioctl interface may assign a kernel ioctl command45 number for each specification defined opcode. At any given point in46 time the number of opcodes that the specification defines and a device47 may implement may exceed the kernel's set of associated ioctl function48 numbers. The mismatch is either by omission, specification is too new,49 or by design. When prototyping new hardware, or developing / debugging50 the driver it is useful to be able to submit any possible command to51 the hardware, even commands that may crash the kernel due to their52 potential impact to memory currently in use by the kernel.53 54 If developing CXL hardware or the driver say Y, otherwise say N.55 56config CXL_ACPI57 tristate "CXL ACPI: Platform Support"58 depends on ACPI59 depends on ACPI_NUMA60 default CXL_BUS61 select ACPI_TABLE_LIB62 select ACPI_HMAT63 select CXL_PORT64 help65 Enable support for host managed device memory (HDM) resources66 published by a platform's ACPI CXL memory layout description. See67 Chapter 9.14.1 CXL Early Discovery Table (CEDT) in the CXL 2.068 specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS)69 (https://www.computeexpresslink.org/spec-landing). The CXL core70 consumes these resource to publish the root of a cxl_port decode71 hierarchy to map regions that represent System RAM, or Persistent72 Memory regions to be managed by LIBNVDIMM.73 74 If unsure say 'm'.75 76config CXL_PMEM77 tristate "CXL PMEM: Persistent Memory Support"78 depends on LIBNVDIMM79 default CXL_BUS80 help81 In addition to typical memory resources a platform may also advertise82 support for persistent memory attached via CXL. This support is83 managed via a bridge driver from CXL to the LIBNVDIMM system84 subsystem. Say 'y/m' to enable support for enumerating and85 provisioning the persistent memory capacity of CXL memory expanders.86 87 If unsure say 'm'.88 89config CXL_MEM90 tristate "CXL: Memory Expansion"91 depends on CXL_PCI92 default CXL_BUS93 help94 The CXL.mem protocol allows a device to act as a provider of "System95 RAM" and/or "Persistent Memory" that is fully coherent as if the96 memory were attached to the typical CPU memory controller. This is97 known as HDM "Host-managed Device Memory".98 99 Say 'y/m' to enable a driver that will attach to CXL.mem devices for100 memory expansion and control of HDM. See Chapter 9.13 in the CXL 2.0101 specification for a detailed description of HDM.102 103 If unsure say 'm'.104 105config CXL_PORT106 default CXL_BUS107 tristate108 109config CXL_SUSPEND110 def_bool y111 depends on SUSPEND && CXL_MEM112 113config CXL_REGION114 bool "CXL: Region Support"115 default CXL_BUS116 # For MAX_PHYSMEM_BITS117 depends on SPARSEMEM118 select MEMREGION119 select GET_FREE_REGION120 help121 Enable the CXL core to enumerate and provision CXL regions. A CXL122 region is defined by one or more CXL expanders that decode a given123 system-physical address range. For CXL regions established by124 platform-firmware this option enables memory error handling to125 identify the devices participating in a given interleaved memory126 range. Otherwise, platform-firmware managed CXL is enabled by being127 placed in the system address map and does not need a driver.128 129 If unsure say 'y'130 131config CXL_REGION_INVALIDATION_TEST132 bool "CXL: Region Cache Management Bypass (TEST)"133 depends on CXL_REGION134 help135 CXL Region management and security operations potentially invalidate136 the content of CPU caches without notifying those caches to137 invalidate the affected cachelines. The CXL Region driver attempts138 to invalidate caches when those events occur. If that invalidation139 fails the region will fail to enable. Reasons for cache140 invalidation failure are due to the CPU not providing a cache141 invalidation mechanism. For example usage of wbinvd is restricted to142 bare metal x86. However, for testing purposes toggling this option143 can disable that data integrity safety and proceed with enabling144 regions when there might be conflicting contents in the CPU cache.145 146 If unsure, or if this kernel is meant for production environments,147 say N.148 149endif150