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1// SPDX-License-Identifier: GPL-2.0-only2/* Copyright(c) 2021 Intel Corporation. All rights reserved. */3#include <linux/platform_device.h>4#include <linux/module.h>5#include <linux/device.h>6#include <linux/kernel.h>7#include <linux/acpi.h>8#include <linux/pci.h>9#include <linux/node.h>10#include <asm/div64.h>11#include "cxlpci.h"12#include "cxl.h"13 14#define CXL_RCRB_SIZE SZ_8K15 16struct cxl_cxims_data {17 int nr_maps;18 u64 xormaps[] __counted_by(nr_maps);19};20 21static const guid_t acpi_cxl_qtg_id_guid =22 GUID_INIT(0xF365F9A6, 0xA7DE, 0x4071,23 0xA6, 0x6A, 0xB4, 0x0C, 0x0B, 0x4F, 0x8E, 0x52);24 25 26static u64 cxl_xor_hpa_to_spa(struct cxl_root_decoder *cxlrd, u64 hpa)27{28 struct cxl_cxims_data *cximsd = cxlrd->platform_data;29 int hbiw = cxlrd->cxlsd.nr_targets;30 u64 val;31 int pos;32 33 /* No xormaps for host bridge interleave ways of 1 or 3 */34 if (hbiw == 1 || hbiw == 3)35 return hpa;36 37 /*38 * For root decoders using xormaps (hbiw: 2,4,6,8,12,16) restore39 * the position bit to its value before the xormap was applied at40 * HPA->DPA translation.41 *42 * pos is the lowest set bit in an XORMAP43 * val is the XORALLBITS(HPA & XORMAP)44 *45 * XORALLBITS: The CXL spec (3.1 Table 9-22) defines XORALLBITS46 * as an operation that outputs a single bit by XORing all the47 * bits in the input (hpa & xormap). Implement XORALLBITS using48 * hweight64(). If the hamming weight is even the XOR of those49 * bits results in val==0, if odd the XOR result is val==1.50 */51 52 for (int i = 0; i < cximsd->nr_maps; i++) {53 if (!cximsd->xormaps[i])54 continue;55 pos = __ffs(cximsd->xormaps[i]);56 val = (hweight64(hpa & cximsd->xormaps[i]) & 1);57 hpa = (hpa & ~(1ULL << pos)) | (val << pos);58 }59 60 return hpa;61}62 63struct cxl_cxims_context {64 struct device *dev;65 struct cxl_root_decoder *cxlrd;66};67 68static int cxl_parse_cxims(union acpi_subtable_headers *header, void *arg,69 const unsigned long end)70{71 struct acpi_cedt_cxims *cxims = (struct acpi_cedt_cxims *)header;72 struct cxl_cxims_context *ctx = arg;73 struct cxl_root_decoder *cxlrd = ctx->cxlrd;74 struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;75 struct device *dev = ctx->dev;76 struct cxl_cxims_data *cximsd;77 unsigned int hbig, nr_maps;78 int rc;79 80 rc = eig_to_granularity(cxims->hbig, &hbig);81 if (rc)82 return rc;83 84 /* Does this CXIMS entry apply to the given CXL Window? */85 if (hbig != cxld->interleave_granularity)86 return 0;87 88 /* IW 1,3 do not use xormaps and skip this parsing entirely */89 if (is_power_of_2(cxld->interleave_ways))90 /* 2, 4, 8, 16 way */91 nr_maps = ilog2(cxld->interleave_ways);92 else93 /* 6, 12 way */94 nr_maps = ilog2(cxld->interleave_ways / 3);95 96 if (cxims->nr_xormaps < nr_maps) {97 dev_dbg(dev, "CXIMS nr_xormaps[%d] expected[%d]\n",98 cxims->nr_xormaps, nr_maps);99 return -ENXIO;100 }101 102 cximsd = devm_kzalloc(dev, struct_size(cximsd, xormaps, nr_maps),103 GFP_KERNEL);104 if (!cximsd)105 return -ENOMEM;106 cximsd->nr_maps = nr_maps;107 memcpy(cximsd->xormaps, cxims->xormap_list,108 nr_maps * sizeof(*cximsd->xormaps));109 cxlrd->platform_data = cximsd;110 111 return 0;112}113 114static unsigned long cfmws_to_decoder_flags(int restrictions)115{116 unsigned long flags = CXL_DECODER_F_ENABLE;117 118 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE2)119 flags |= CXL_DECODER_F_TYPE2;120 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE3)121 flags |= CXL_DECODER_F_TYPE3;122 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_VOLATILE)123 flags |= CXL_DECODER_F_RAM;124 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_PMEM)125 flags |= CXL_DECODER_F_PMEM;126 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_FIXED)127 flags |= CXL_DECODER_F_LOCK;128 129 return flags;130}131 132static int cxl_acpi_cfmws_verify(struct device *dev,133 struct acpi_cedt_cfmws *cfmws)134{135 int rc, expected_len;136 unsigned int ways;137 138 if (cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_MODULO &&139 cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_XOR) {140 dev_err(dev, "CFMWS Unknown Interleave Arithmetic: %d\n",141 cfmws->interleave_arithmetic);142 return -EINVAL;143 }144 145 if (!IS_ALIGNED(cfmws->base_hpa, SZ_256M)) {146 dev_err(dev, "CFMWS Base HPA not 256MB aligned\n");147 return -EINVAL;148 }149 150 if (!IS_ALIGNED(cfmws->window_size, SZ_256M)) {151 dev_err(dev, "CFMWS Window Size not 256MB aligned\n");152 return -EINVAL;153 }154 155 rc = eiw_to_ways(cfmws->interleave_ways, &ways);156 if (rc) {157 dev_err(dev, "CFMWS Interleave Ways (%d) invalid\n",158 cfmws->interleave_ways);159 return -EINVAL;160 }161 162 expected_len = struct_size(cfmws, interleave_targets, ways);163 164 if (cfmws->header.length < expected_len) {165 dev_err(dev, "CFMWS length %d less than expected %d\n",166 cfmws->header.length, expected_len);167 return -EINVAL;168 }169 170 if (cfmws->header.length > expected_len)171 dev_dbg(dev, "CFMWS length %d greater than expected %d\n",172 cfmws->header.length, expected_len);173 174 return 0;175}176 177/*178 * Note, @dev must be the first member, see 'struct cxl_chbs_context'179 * and mock_acpi_table_parse_cedt()180 */181struct cxl_cfmws_context {182 struct device *dev;183 struct cxl_port *root_port;184 struct resource *cxl_res;185 int id;186};187 188/**189 * cxl_acpi_evaluate_qtg_dsm - Retrieve QTG ids via ACPI _DSM190 * @handle: ACPI handle191 * @coord: performance access coordinates192 * @entries: number of QTG IDs to return193 * @qos_class: int array provided by caller to return QTG IDs194 *195 * Return: number of QTG IDs returned, or -errno for errors196 *197 * Issue QTG _DSM with accompanied bandwidth and latency data in order to get198 * the QTG IDs that are suitable for the performance point in order of most199 * suitable to least suitable. Write back array of QTG IDs and return the200 * actual number of QTG IDs written back.201 */202static int203cxl_acpi_evaluate_qtg_dsm(acpi_handle handle, struct access_coordinate *coord,204 int entries, int *qos_class)205{206 union acpi_object *out_obj, *out_buf, *obj;207 union acpi_object in_array[4] = {208 [0].integer = { ACPI_TYPE_INTEGER, coord->read_latency },209 [1].integer = { ACPI_TYPE_INTEGER, coord->write_latency },210 [2].integer = { ACPI_TYPE_INTEGER, coord->read_bandwidth },211 [3].integer = { ACPI_TYPE_INTEGER, coord->write_bandwidth },212 };213 union acpi_object in_obj = {214 .package = {215 .type = ACPI_TYPE_PACKAGE,216 .count = 4,217 .elements = in_array,218 },219 };220 int count, pkg_entries, i;221 u16 max_qtg;222 int rc;223 224 if (!entries)225 return -EINVAL;226 227 out_obj = acpi_evaluate_dsm(handle, &acpi_cxl_qtg_id_guid, 1, 1, &in_obj);228 if (!out_obj)229 return -ENXIO;230 231 if (out_obj->type != ACPI_TYPE_PACKAGE) {232 rc = -ENXIO;233 goto out;234 }235 236 /* Check Max QTG ID */237 obj = &out_obj->package.elements[0];238 if (obj->type != ACPI_TYPE_INTEGER) {239 rc = -ENXIO;240 goto out;241 }242 243 max_qtg = obj->integer.value;244 245 /* It's legal to have 0 QTG entries */246 pkg_entries = out_obj->package.count;247 if (pkg_entries <= 1) {248 rc = 0;249 goto out;250 }251 252 /* Retrieve QTG IDs package */253 obj = &out_obj->package.elements[1];254 if (obj->type != ACPI_TYPE_PACKAGE) {255 rc = -ENXIO;256 goto out;257 }258 259 pkg_entries = obj->package.count;260 count = min(entries, pkg_entries);261 for (i = 0; i < count; i++) {262 u16 qtg_id;263 264 out_buf = &obj->package.elements[i];265 if (out_buf->type != ACPI_TYPE_INTEGER) {266 rc = -ENXIO;267 goto out;268 }269 270 qtg_id = out_buf->integer.value;271 if (qtg_id > max_qtg)272 pr_warn("QTG ID %u greater than MAX %u\n",273 qtg_id, max_qtg);274 275 qos_class[i] = qtg_id;276 }277 rc = count;278 279out:280 ACPI_FREE(out_obj);281 return rc;282}283 284static int cxl_acpi_qos_class(struct cxl_root *cxl_root,285 struct access_coordinate *coord, int entries,286 int *qos_class)287{288 struct device *dev = cxl_root->port.uport_dev;289 acpi_handle handle;290 291 if (!dev_is_platform(dev))292 return -ENODEV;293 294 handle = ACPI_HANDLE(dev);295 if (!handle)296 return -ENODEV;297 298 return cxl_acpi_evaluate_qtg_dsm(handle, coord, entries, qos_class);299}300 301static const struct cxl_root_ops acpi_root_ops = {302 .qos_class = cxl_acpi_qos_class,303};304 305static void del_cxl_resource(struct resource *res)306{307 if (!res)308 return;309 kfree(res->name);310 kfree(res);311}312 313static struct resource *alloc_cxl_resource(resource_size_t base,314 resource_size_t n, int id)315{316 struct resource *res __free(kfree) = kzalloc(sizeof(*res), GFP_KERNEL);317 318 if (!res)319 return NULL;320 321 res->start = base;322 res->end = base + n - 1;323 res->flags = IORESOURCE_MEM;324 res->name = kasprintf(GFP_KERNEL, "CXL Window %d", id);325 if (!res->name)326 return NULL;327 328 return no_free_ptr(res);329}330 331static int add_or_reset_cxl_resource(struct resource *parent, struct resource *res)332{333 int rc = insert_resource(parent, res);334 335 if (rc)336 del_cxl_resource(res);337 return rc;338}339 340DEFINE_FREE(put_cxlrd, struct cxl_root_decoder *,341 if (!IS_ERR_OR_NULL(_T)) put_device(&_T->cxlsd.cxld.dev))342DEFINE_FREE(del_cxl_resource, struct resource *, if (_T) del_cxl_resource(_T))343static int __cxl_parse_cfmws(struct acpi_cedt_cfmws *cfmws,344 struct cxl_cfmws_context *ctx)345{346 int target_map[CXL_DECODER_MAX_INTERLEAVE];347 struct cxl_port *root_port = ctx->root_port;348 struct cxl_cxims_context cxims_ctx;349 struct device *dev = ctx->dev;350 struct cxl_decoder *cxld;351 unsigned int ways, i, ig;352 int rc;353 354 rc = cxl_acpi_cfmws_verify(dev, cfmws);355 if (rc)356 return rc;357 358 rc = eiw_to_ways(cfmws->interleave_ways, &ways);359 if (rc)360 return rc;361 rc = eig_to_granularity(cfmws->granularity, &ig);362 if (rc)363 return rc;364 for (i = 0; i < ways; i++)365 target_map[i] = cfmws->interleave_targets[i];366 367 struct resource *res __free(del_cxl_resource) = alloc_cxl_resource(368 cfmws->base_hpa, cfmws->window_size, ctx->id++);369 if (!res)370 return -ENOMEM;371 372 /* add to the local resource tracking to establish a sort order */373 rc = add_or_reset_cxl_resource(ctx->cxl_res, no_free_ptr(res));374 if (rc)375 return rc;376 377 struct cxl_root_decoder *cxlrd __free(put_cxlrd) =378 cxl_root_decoder_alloc(root_port, ways);379 380 if (IS_ERR(cxlrd))381 return PTR_ERR(cxlrd);382 383 cxld = &cxlrd->cxlsd.cxld;384 cxld->flags = cfmws_to_decoder_flags(cfmws->restrictions);385 cxld->target_type = CXL_DECODER_HOSTONLYMEM;386 cxld->hpa_range = (struct range) {387 .start = cfmws->base_hpa,388 .end = cfmws->base_hpa + cfmws->window_size - 1,389 };390 cxld->interleave_ways = ways;391 /*392 * Minimize the x1 granularity to advertise support for any393 * valid region granularity394 */395 if (ways == 1)396 ig = CXL_DECODER_MIN_GRANULARITY;397 cxld->interleave_granularity = ig;398 399 if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_XOR) {400 if (ways != 1 && ways != 3) {401 cxims_ctx = (struct cxl_cxims_context) {402 .dev = dev,403 .cxlrd = cxlrd,404 };405 rc = acpi_table_parse_cedt(ACPI_CEDT_TYPE_CXIMS,406 cxl_parse_cxims, &cxims_ctx);407 if (rc < 0)408 return rc;409 if (!cxlrd->platform_data) {410 dev_err(dev, "No CXIMS for HBIG %u\n", ig);411 return -EINVAL;412 }413 }414 }415 416 cxlrd->qos_class = cfmws->qtg_id;417 418 if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_XOR)419 cxlrd->hpa_to_spa = cxl_xor_hpa_to_spa;420 421 rc = cxl_decoder_add(cxld, target_map);422 if (rc)423 return rc;424 return cxl_root_decoder_autoremove(dev, no_free_ptr(cxlrd));425}426 427static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,428 const unsigned long end)429{430 struct acpi_cedt_cfmws *cfmws = (struct acpi_cedt_cfmws *)header;431 struct cxl_cfmws_context *ctx = arg;432 struct device *dev = ctx->dev;433 int rc;434 435 rc = __cxl_parse_cfmws(cfmws, ctx);436 if (rc)437 dev_err(dev,438 "Failed to add decode range: [%#llx - %#llx] (%d)\n",439 cfmws->base_hpa,440 cfmws->base_hpa + cfmws->window_size - 1, rc);441 else442 dev_dbg(dev, "decode range: node: %d range [%#llx - %#llx]\n",443 phys_to_target_node(cfmws->base_hpa), cfmws->base_hpa,444 cfmws->base_hpa + cfmws->window_size - 1);445 446 /* never fail cxl_acpi load for a single window failure */447 return 0;448}449 450__mock struct acpi_device *to_cxl_host_bridge(struct device *host,451 struct device *dev)452{453 struct acpi_device *adev = to_acpi_device(dev);454 455 if (!acpi_pci_find_root(adev->handle))456 return NULL;457 458 if (strcmp(acpi_device_hid(adev), "ACPI0016") == 0)459 return adev;460 return NULL;461}462 463/* Note, @dev is used by mock_acpi_table_parse_cedt() */464struct cxl_chbs_context {465 struct device *dev;466 unsigned long long uid;467 resource_size_t base;468 u32 cxl_version;469 int nr_versions;470 u32 saved_version;471};472 473static int cxl_get_chbs_iter(union acpi_subtable_headers *header, void *arg,474 const unsigned long end)475{476 struct cxl_chbs_context *ctx = arg;477 struct acpi_cedt_chbs *chbs;478 479 chbs = (struct acpi_cedt_chbs *) header;480 481 if (chbs->cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11 &&482 chbs->length != CXL_RCRB_SIZE)483 return 0;484 485 if (!chbs->base)486 return 0;487 488 if (ctx->saved_version != chbs->cxl_version) {489 /*490 * cxl_version cannot be overwritten before the next two491 * checks, then use saved_version492 */493 ctx->saved_version = chbs->cxl_version;494 ctx->nr_versions++;495 }496 497 if (ctx->base != CXL_RESOURCE_NONE)498 return 0;499 500 if (ctx->uid != chbs->uid)501 return 0;502 503 ctx->cxl_version = chbs->cxl_version;504 ctx->base = chbs->base;505 506 return 0;507}508 509static int cxl_get_chbs(struct device *dev, struct acpi_device *hb,510 struct cxl_chbs_context *ctx)511{512 unsigned long long uid;513 int rc;514 515 rc = acpi_evaluate_integer(hb->handle, METHOD_NAME__UID, NULL, &uid);516 if (rc != AE_OK) {517 dev_err(dev, "unable to retrieve _UID\n");518 return -ENOENT;519 }520 521 dev_dbg(dev, "UID found: %lld\n", uid);522 *ctx = (struct cxl_chbs_context) {523 .dev = dev,524 .uid = uid,525 .base = CXL_RESOURCE_NONE,526 .cxl_version = UINT_MAX,527 .saved_version = UINT_MAX,528 };529 530 acpi_table_parse_cedt(ACPI_CEDT_TYPE_CHBS, cxl_get_chbs_iter, ctx);531 532 if (ctx->nr_versions > 1) {533 /*534 * Disclaim eRCD support given some component register may535 * only be found via CHBCR536 */537 dev_info(dev, "Unsupported platform config, mixed Virtual Host and Restricted CXL Host hierarchy.");538 }539 540 return 0;541}542 543static int get_genport_coordinates(struct device *dev, struct cxl_dport *dport)544{545 struct acpi_device *hb = to_cxl_host_bridge(NULL, dev);546 u32 uid;547 548 if (kstrtou32(acpi_device_uid(hb), 0, &uid))549 return -EINVAL;550 551 return acpi_get_genport_coordinates(uid, dport->coord);552}553 554static int add_host_bridge_dport(struct device *match, void *arg)555{556 int ret;557 acpi_status rc;558 struct device *bridge;559 struct cxl_dport *dport;560 struct cxl_chbs_context ctx;561 struct acpi_pci_root *pci_root;562 struct cxl_port *root_port = arg;563 struct device *host = root_port->dev.parent;564 struct acpi_device *hb = to_cxl_host_bridge(host, match);565 566 if (!hb)567 return 0;568 569 rc = cxl_get_chbs(match, hb, &ctx);570 if (rc)571 return rc;572 573 if (ctx.cxl_version == UINT_MAX) {574 dev_warn(match, "No CHBS found for Host Bridge (UID %lld)\n",575 ctx.uid);576 return 0;577 }578 579 if (ctx.base == CXL_RESOURCE_NONE) {580 dev_warn(match, "CHBS invalid for Host Bridge (UID %lld)\n",581 ctx.uid);582 return 0;583 }584 585 pci_root = acpi_pci_find_root(hb->handle);586 bridge = pci_root->bus->bridge;587 588 /*589 * In RCH mode, bind the component regs base to the dport. In590 * VH mode it will be bound to the CXL host bridge's port591 * object later in add_host_bridge_uport().592 */593 if (ctx.cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11) {594 dev_dbg(match, "RCRB found for UID %lld: %pa\n", ctx.uid,595 &ctx.base);596 dport = devm_cxl_add_rch_dport(root_port, bridge, ctx.uid,597 ctx.base);598 } else {599 dport = devm_cxl_add_dport(root_port, bridge, ctx.uid,600 CXL_RESOURCE_NONE);601 }602 603 if (IS_ERR(dport))604 return PTR_ERR(dport);605 606 ret = get_genport_coordinates(match, dport);607 if (ret)608 dev_dbg(match, "Failed to get generic port perf coordinates.\n");609 610 return 0;611}612 613/*614 * A host bridge is a dport to a CFMWS decode and it is a uport to the615 * dport (PCIe Root Ports) in the host bridge.616 */617static int add_host_bridge_uport(struct device *match, void *arg)618{619 struct cxl_port *root_port = arg;620 struct device *host = root_port->dev.parent;621 struct acpi_device *hb = to_cxl_host_bridge(host, match);622 struct acpi_pci_root *pci_root;623 struct cxl_dport *dport;624 struct cxl_port *port;625 struct device *bridge;626 struct cxl_chbs_context ctx;627 resource_size_t component_reg_phys;628 int rc;629 630 if (!hb)631 return 0;632 633 pci_root = acpi_pci_find_root(hb->handle);634 bridge = pci_root->bus->bridge;635 dport = cxl_find_dport_by_dev(root_port, bridge);636 if (!dport) {637 dev_dbg(host, "host bridge expected and not found\n");638 return 0;639 }640 641 if (dport->rch) {642 dev_info(bridge, "host supports CXL (restricted)\n");643 return 0;644 }645 646 rc = cxl_get_chbs(match, hb, &ctx);647 if (rc)648 return rc;649 650 if (ctx.cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11) {651 dev_warn(bridge,652 "CXL CHBS version mismatch, skip port registration\n");653 return 0;654 }655 656 component_reg_phys = ctx.base;657 if (component_reg_phys != CXL_RESOURCE_NONE)658 dev_dbg(match, "CHBCR found for UID %lld: %pa\n",659 ctx.uid, &component_reg_phys);660 661 rc = devm_cxl_register_pci_bus(host, bridge, pci_root->bus);662 if (rc)663 return rc;664 665 port = devm_cxl_add_port(host, bridge, component_reg_phys, dport);666 if (IS_ERR(port))667 return PTR_ERR(port);668 669 dev_info(bridge, "host supports CXL\n");670 671 return 0;672}673 674static int add_root_nvdimm_bridge(struct device *match, void *data)675{676 struct cxl_decoder *cxld;677 struct cxl_port *root_port = data;678 struct cxl_nvdimm_bridge *cxl_nvb;679 struct device *host = root_port->dev.parent;680 681 if (!is_root_decoder(match))682 return 0;683 684 cxld = to_cxl_decoder(match);685 if (!(cxld->flags & CXL_DECODER_F_PMEM))686 return 0;687 688 cxl_nvb = devm_cxl_add_nvdimm_bridge(host, root_port);689 if (IS_ERR(cxl_nvb)) {690 dev_dbg(host, "failed to register pmem\n");691 return PTR_ERR(cxl_nvb);692 }693 dev_dbg(host, "%s: add: %s\n", dev_name(&root_port->dev),694 dev_name(&cxl_nvb->dev));695 return 1;696}697 698static struct lock_class_key cxl_root_key;699 700static void cxl_acpi_lock_reset_class(void *dev)701{702 device_lock_reset_class(dev);703}704 705static void cxl_set_public_resource(struct resource *priv, struct resource *pub)706{707 priv->desc = (unsigned long) pub;708}709 710static struct resource *cxl_get_public_resource(struct resource *priv)711{712 return (struct resource *) priv->desc;713}714 715static void remove_cxl_resources(void *data)716{717 struct resource *res, *next, *cxl = data;718 719 for (res = cxl->child; res; res = next) {720 struct resource *victim = cxl_get_public_resource(res);721 722 next = res->sibling;723 remove_resource(res);724 725 if (victim) {726 remove_resource(victim);727 kfree(victim);728 }729 730 del_cxl_resource(res);731 }732}733 734/**735 * add_cxl_resources() - reflect CXL fixed memory windows in iomem_resource736 * @cxl_res: A standalone resource tree where each CXL window is a sibling737 *738 * Walk each CXL window in @cxl_res and add it to iomem_resource potentially739 * expanding its boundaries to ensure that any conflicting resources become740 * children. If a window is expanded it may then conflict with a another window741 * entry and require the window to be truncated or trimmed. Consider this742 * situation:743 *744 * |-- "CXL Window 0" --||----- "CXL Window 1" -----|745 * |--------------- "System RAM" -------------|746 *747 * ...where platform firmware has established as System RAM resource across 2748 * windows, but has left some portion of window 1 for dynamic CXL region749 * provisioning. In this case "Window 0" will span the entirety of the "System750 * RAM" span, and "CXL Window 1" is truncated to the remaining tail past the end751 * of that "System RAM" resource.752 */753static int add_cxl_resources(struct resource *cxl_res)754{755 struct resource *res, *new, *next;756 757 for (res = cxl_res->child; res; res = next) {758 new = kzalloc(sizeof(*new), GFP_KERNEL);759 if (!new)760 return -ENOMEM;761 new->name = res->name;762 new->start = res->start;763 new->end = res->end;764 new->flags = IORESOURCE_MEM;765 new->desc = IORES_DESC_CXL;766 767 /*768 * Record the public resource in the private cxl_res tree for769 * later removal.770 */771 cxl_set_public_resource(res, new);772 773 insert_resource_expand_to_fit(&iomem_resource, new);774 775 next = res->sibling;776 while (next && resource_overlaps(new, next)) {777 if (resource_contains(new, next)) {778 struct resource *_next = next->sibling;779 780 remove_resource(next);781 del_cxl_resource(next);782 next = _next;783 } else784 next->start = new->end + 1;785 }786 }787 return 0;788}789 790static int pair_cxl_resource(struct device *dev, void *data)791{792 struct resource *cxl_res = data;793 struct resource *p;794 795 if (!is_root_decoder(dev))796 return 0;797 798 for (p = cxl_res->child; p; p = p->sibling) {799 struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(dev);800 struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;801 struct resource res = {802 .start = cxld->hpa_range.start,803 .end = cxld->hpa_range.end,804 .flags = IORESOURCE_MEM,805 };806 807 if (resource_contains(p, &res)) {808 cxlrd->res = cxl_get_public_resource(p);809 break;810 }811 }812 813 return 0;814}815 816static int cxl_acpi_probe(struct platform_device *pdev)817{818 int rc;819 struct resource *cxl_res;820 struct cxl_root *cxl_root;821 struct cxl_port *root_port;822 struct device *host = &pdev->dev;823 struct acpi_device *adev = ACPI_COMPANION(host);824 struct cxl_cfmws_context ctx;825 826 device_lock_set_class(&pdev->dev, &cxl_root_key);827 rc = devm_add_action_or_reset(&pdev->dev, cxl_acpi_lock_reset_class,828 &pdev->dev);829 if (rc)830 return rc;831 832 cxl_res = devm_kzalloc(host, sizeof(*cxl_res), GFP_KERNEL);833 if (!cxl_res)834 return -ENOMEM;835 cxl_res->name = "CXL mem";836 cxl_res->start = 0;837 cxl_res->end = -1;838 cxl_res->flags = IORESOURCE_MEM;839 840 cxl_root = devm_cxl_add_root(host, &acpi_root_ops);841 if (IS_ERR(cxl_root))842 return PTR_ERR(cxl_root);843 root_port = &cxl_root->port;844 845 rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,846 add_host_bridge_dport);847 if (rc < 0)848 return rc;849 850 rc = devm_add_action_or_reset(host, remove_cxl_resources, cxl_res);851 if (rc)852 return rc;853 854 ctx = (struct cxl_cfmws_context) {855 .dev = host,856 .root_port = root_port,857 .cxl_res = cxl_res,858 };859 rc = acpi_table_parse_cedt(ACPI_CEDT_TYPE_CFMWS, cxl_parse_cfmws, &ctx);860 if (rc < 0)861 return -ENXIO;862 863 rc = add_cxl_resources(cxl_res);864 if (rc)865 return rc;866 867 /*868 * Populate the root decoders with their related iomem resource,869 * if present870 */871 device_for_each_child(&root_port->dev, cxl_res, pair_cxl_resource);872 873 /*874 * Root level scanned with host-bridge as dports, now scan host-bridges875 * for their role as CXL uports to their CXL-capable PCIe Root Ports.876 */877 rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,878 add_host_bridge_uport);879 if (rc < 0)880 return rc;881 882 if (IS_ENABLED(CONFIG_CXL_PMEM))883 rc = device_for_each_child(&root_port->dev, root_port,884 add_root_nvdimm_bridge);885 if (rc < 0)886 return rc;887 888 /* In case PCI is scanned before ACPI re-trigger memdev attach */889 cxl_bus_rescan();890 return 0;891}892 893static const struct acpi_device_id cxl_acpi_ids[] = {894 { "ACPI0017" },895 { },896};897MODULE_DEVICE_TABLE(acpi, cxl_acpi_ids);898 899static const struct platform_device_id cxl_test_ids[] = {900 { "cxl_acpi" },901 { },902};903MODULE_DEVICE_TABLE(platform, cxl_test_ids);904 905static struct platform_driver cxl_acpi_driver = {906 .probe = cxl_acpi_probe,907 .driver = {908 .name = KBUILD_MODNAME,909 .acpi_match_table = cxl_acpi_ids,910 },911 .id_table = cxl_test_ids,912};913 914static int __init cxl_acpi_init(void)915{916 return platform_driver_register(&cxl_acpi_driver);917}918 919static void __exit cxl_acpi_exit(void)920{921 platform_driver_unregister(&cxl_acpi_driver);922 cxl_bus_drain();923}924 925/* load before dax_hmem sees 'Soft Reserved' CXL ranges */926subsys_initcall(cxl_acpi_init);927 928/*929 * Arrange for host-bridge ports to be active synchronous with930 * cxl_acpi_probe() exit.931 */932MODULE_SOFTDEP("pre: cxl_port");933 934module_exit(cxl_acpi_exit);935MODULE_DESCRIPTION("CXL ACPI: Platform Support");936MODULE_LICENSE("GPL v2");937MODULE_IMPORT_NS(CXL);938MODULE_IMPORT_NS(ACPI);939