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1/* SPDX-License-Identifier: GPL-2.0-only */2/* Copyright(c) 2020 Intel Corporation. */3 4#ifndef __CXL_CORE_H__5#define __CXL_CORE_H__6 7extern const struct device_type cxl_nvdimm_bridge_type;8extern const struct device_type cxl_nvdimm_type;9extern const struct device_type cxl_pmu_type;10 11extern struct attribute_group cxl_base_attribute_group;12 13#ifdef CONFIG_CXL_REGION14extern struct device_attribute dev_attr_create_pmem_region;15extern struct device_attribute dev_attr_create_ram_region;16extern struct device_attribute dev_attr_delete_region;17extern struct device_attribute dev_attr_region;18extern const struct device_type cxl_pmem_region_type;19extern const struct device_type cxl_dax_region_type;20extern const struct device_type cxl_region_type;21void cxl_decoder_kill_region(struct cxl_endpoint_decoder *cxled);22#define CXL_REGION_ATTR(x) (&dev_attr_##x.attr)23#define CXL_REGION_TYPE(x) (&cxl_region_type)24#define SET_CXL_REGION_ATTR(x) (&dev_attr_##x.attr),25#define CXL_PMEM_REGION_TYPE(x) (&cxl_pmem_region_type)26#define CXL_DAX_REGION_TYPE(x) (&cxl_dax_region_type)27int cxl_region_init(void);28void cxl_region_exit(void);29int cxl_get_poison_by_endpoint(struct cxl_port *port);30struct cxl_region *cxl_dpa_to_region(const struct cxl_memdev *cxlmd, u64 dpa);31u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, const struct cxl_memdev *cxlmd,32 u64 dpa);33 34#else35static inline u64 cxl_dpa_to_hpa(struct cxl_region *cxlr,36 const struct cxl_memdev *cxlmd, u64 dpa)37{38 return ULLONG_MAX;39}40static inline41struct cxl_region *cxl_dpa_to_region(const struct cxl_memdev *cxlmd, u64 dpa)42{43 return NULL;44}45static inline int cxl_get_poison_by_endpoint(struct cxl_port *port)46{47 return 0;48}49static inline void cxl_decoder_kill_region(struct cxl_endpoint_decoder *cxled)50{51}52static inline int cxl_region_init(void)53{54 return 0;55}56static inline void cxl_region_exit(void)57{58}59#define CXL_REGION_ATTR(x) NULL60#define CXL_REGION_TYPE(x) NULL61#define SET_CXL_REGION_ATTR(x)62#define CXL_PMEM_REGION_TYPE(x) NULL63#define CXL_DAX_REGION_TYPE(x) NULL64#endif65 66struct cxl_send_command;67struct cxl_mem_query_commands;68int cxl_query_cmd(struct cxl_memdev *cxlmd,69 struct cxl_mem_query_commands __user *q);70int cxl_send_cmd(struct cxl_memdev *cxlmd, struct cxl_send_command __user *s);71void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,72 resource_size_t length);73 74struct dentry *cxl_debugfs_create_dir(const char *dir);75int cxl_dpa_set_mode(struct cxl_endpoint_decoder *cxled,76 enum cxl_decoder_mode mode);77int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, unsigned long long size);78int cxl_dpa_free(struct cxl_endpoint_decoder *cxled);79resource_size_t cxl_dpa_size(struct cxl_endpoint_decoder *cxled);80resource_size_t cxl_dpa_resource_start(struct cxl_endpoint_decoder *cxled);81 82enum cxl_rcrb {83 CXL_RCRB_DOWNSTREAM,84 CXL_RCRB_UPSTREAM,85};86struct cxl_rcrb_info;87resource_size_t __rcrb_to_component(struct device *dev,88 struct cxl_rcrb_info *ri,89 enum cxl_rcrb which);90u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t rcrb);91 92extern struct rw_semaphore cxl_dpa_rwsem;93extern struct rw_semaphore cxl_region_rwsem;94 95int cxl_memdev_init(void);96void cxl_memdev_exit(void);97void cxl_mbox_init(void);98 99enum cxl_poison_trace_type {100 CXL_POISON_TRACE_LIST,101 CXL_POISON_TRACE_INJECT,102 CXL_POISON_TRACE_CLEAR,103};104 105long cxl_pci_get_latency(struct pci_dev *pdev);106int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c);107int cxl_update_hmat_access_coordinates(int nid, struct cxl_region *cxlr,108 enum access_coordinate_class access);109bool cxl_need_node_perf_attrs_update(int nid);110int cxl_port_get_switch_dport_bandwidth(struct cxl_port *port,111 struct access_coordinate *c);112 113#endif /* __CXL_CORE_H__ */114