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1// SPDX-License-Identifier: GPL-2.02/* Copyright(c) 2022 Intel Corporation. All rights reserved. */3#undef TRACE_SYSTEM4#define TRACE_SYSTEM cxl5 6#if !defined(_CXL_EVENTS_H) || defined(TRACE_HEADER_MULTI_READ)7#define _CXL_EVENTS_H8 9#include <linux/tracepoint.h>10#include <linux/pci.h>11#include <linux/unaligned.h>12 13#include <cxl.h>14#include <cxlmem.h>15#include "core.h"16 17#define CXL_RAS_UC_CACHE_DATA_PARITY BIT(0)18#define CXL_RAS_UC_CACHE_ADDR_PARITY BIT(1)19#define CXL_RAS_UC_CACHE_BE_PARITY BIT(2)20#define CXL_RAS_UC_CACHE_DATA_ECC BIT(3)21#define CXL_RAS_UC_MEM_DATA_PARITY BIT(4)22#define CXL_RAS_UC_MEM_ADDR_PARITY BIT(5)23#define CXL_RAS_UC_MEM_BE_PARITY BIT(6)24#define CXL_RAS_UC_MEM_DATA_ECC BIT(7)25#define CXL_RAS_UC_REINIT_THRESH BIT(8)26#define CXL_RAS_UC_RSVD_ENCODE BIT(9)27#define CXL_RAS_UC_POISON BIT(10)28#define CXL_RAS_UC_RECV_OVERFLOW BIT(11)29#define CXL_RAS_UC_INTERNAL_ERR BIT(14)30#define CXL_RAS_UC_IDE_TX_ERR BIT(15)31#define CXL_RAS_UC_IDE_RX_ERR BIT(16)32 33#define show_uc_errs(status) __print_flags(status, " | ", \34 { CXL_RAS_UC_CACHE_DATA_PARITY, "Cache Data Parity Error" }, \35 { CXL_RAS_UC_CACHE_ADDR_PARITY, "Cache Address Parity Error" }, \36 { CXL_RAS_UC_CACHE_BE_PARITY, "Cache Byte Enable Parity Error" }, \37 { CXL_RAS_UC_CACHE_DATA_ECC, "Cache Data ECC Error" }, \38 { CXL_RAS_UC_MEM_DATA_PARITY, "Memory Data Parity Error" }, \39 { CXL_RAS_UC_MEM_ADDR_PARITY, "Memory Address Parity Error" }, \40 { CXL_RAS_UC_MEM_BE_PARITY, "Memory Byte Enable Parity Error" }, \41 { CXL_RAS_UC_MEM_DATA_ECC, "Memory Data ECC Error" }, \42 { CXL_RAS_UC_REINIT_THRESH, "REINIT Threshold Hit" }, \43 { CXL_RAS_UC_RSVD_ENCODE, "Received Unrecognized Encoding" }, \44 { CXL_RAS_UC_POISON, "Received Poison From Peer" }, \45 { CXL_RAS_UC_RECV_OVERFLOW, "Receiver Overflow" }, \46 { CXL_RAS_UC_INTERNAL_ERR, "Component Specific Error" }, \47 { CXL_RAS_UC_IDE_TX_ERR, "IDE Tx Error" }, \48 { CXL_RAS_UC_IDE_RX_ERR, "IDE Rx Error" } \49)50 51TRACE_EVENT(cxl_aer_uncorrectable_error,52 TP_PROTO(const struct cxl_memdev *cxlmd, u32 status, u32 fe, u32 *hl),53 TP_ARGS(cxlmd, status, fe, hl),54 TP_STRUCT__entry(55 __string(memdev, dev_name(&cxlmd->dev))56 __string(host, dev_name(cxlmd->dev.parent))57 __field(u64, serial)58 __field(u32, status)59 __field(u32, first_error)60 __array(u32, header_log, CXL_HEADERLOG_SIZE_U32)61 ),62 TP_fast_assign(63 __assign_str(memdev);64 __assign_str(host);65 __entry->serial = cxlmd->cxlds->serial;66 __entry->status = status;67 __entry->first_error = fe;68 /*69 * Embed the 512B headerlog data for user app retrieval and70 * parsing, but no need to print this in the trace buffer.71 */72 memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE);73 ),74 TP_printk("memdev=%s host=%s serial=%lld: status: '%s' first_error: '%s'",75 __get_str(memdev), __get_str(host), __entry->serial,76 show_uc_errs(__entry->status),77 show_uc_errs(__entry->first_error)78 )79);80 81#define CXL_RAS_CE_CACHE_DATA_ECC BIT(0)82#define CXL_RAS_CE_MEM_DATA_ECC BIT(1)83#define CXL_RAS_CE_CRC_THRESH BIT(2)84#define CLX_RAS_CE_RETRY_THRESH BIT(3)85#define CXL_RAS_CE_CACHE_POISON BIT(4)86#define CXL_RAS_CE_MEM_POISON BIT(5)87#define CXL_RAS_CE_PHYS_LAYER_ERR BIT(6)88 89#define show_ce_errs(status) __print_flags(status, " | ", \90 { CXL_RAS_CE_CACHE_DATA_ECC, "Cache Data ECC Error" }, \91 { CXL_RAS_CE_MEM_DATA_ECC, "Memory Data ECC Error" }, \92 { CXL_RAS_CE_CRC_THRESH, "CRC Threshold Hit" }, \93 { CLX_RAS_CE_RETRY_THRESH, "Retry Threshold" }, \94 { CXL_RAS_CE_CACHE_POISON, "Received Cache Poison From Peer" }, \95 { CXL_RAS_CE_MEM_POISON, "Received Memory Poison From Peer" }, \96 { CXL_RAS_CE_PHYS_LAYER_ERR, "Received Error From Physical Layer" } \97)98 99TRACE_EVENT(cxl_aer_correctable_error,100 TP_PROTO(const struct cxl_memdev *cxlmd, u32 status),101 TP_ARGS(cxlmd, status),102 TP_STRUCT__entry(103 __string(memdev, dev_name(&cxlmd->dev))104 __string(host, dev_name(cxlmd->dev.parent))105 __field(u64, serial)106 __field(u32, status)107 ),108 TP_fast_assign(109 __assign_str(memdev);110 __assign_str(host);111 __entry->serial = cxlmd->cxlds->serial;112 __entry->status = status;113 ),114 TP_printk("memdev=%s host=%s serial=%lld: status: '%s'",115 __get_str(memdev), __get_str(host), __entry->serial,116 show_ce_errs(__entry->status)117 )118);119 120#define cxl_event_log_type_str(type) \121 __print_symbolic(type, \122 { CXL_EVENT_TYPE_INFO, "Informational" }, \123 { CXL_EVENT_TYPE_WARN, "Warning" }, \124 { CXL_EVENT_TYPE_FAIL, "Failure" }, \125 { CXL_EVENT_TYPE_FATAL, "Fatal" })126 127TRACE_EVENT(cxl_overflow,128 129 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log,130 struct cxl_get_event_payload *payload),131 132 TP_ARGS(cxlmd, log, payload),133 134 TP_STRUCT__entry(135 __string(memdev, dev_name(&cxlmd->dev))136 __string(host, dev_name(cxlmd->dev.parent))137 __field(int, log)138 __field(u64, serial)139 __field(u64, first_ts)140 __field(u64, last_ts)141 __field(u16, count)142 ),143 144 TP_fast_assign(145 __assign_str(memdev);146 __assign_str(host);147 __entry->serial = cxlmd->cxlds->serial;148 __entry->log = log;149 __entry->count = le16_to_cpu(payload->overflow_err_count);150 __entry->first_ts = le64_to_cpu(payload->first_overflow_timestamp);151 __entry->last_ts = le64_to_cpu(payload->last_overflow_timestamp);152 ),153 154 TP_printk("memdev=%s host=%s serial=%lld: log=%s : %u records from %llu to %llu",155 __get_str(memdev), __get_str(host), __entry->serial,156 cxl_event_log_type_str(__entry->log), __entry->count,157 __entry->first_ts, __entry->last_ts)158 159);160 161/*162 * Common Event Record Format163 * CXL 3.0 section 8.2.9.2.1; Table 8-42164 */165#define CXL_EVENT_RECORD_FLAG_PERMANENT BIT(2)166#define CXL_EVENT_RECORD_FLAG_MAINT_NEEDED BIT(3)167#define CXL_EVENT_RECORD_FLAG_PERF_DEGRADED BIT(4)168#define CXL_EVENT_RECORD_FLAG_HW_REPLACE BIT(5)169#define show_hdr_flags(flags) __print_flags(flags, " | ", \170 { CXL_EVENT_RECORD_FLAG_PERMANENT, "PERMANENT_CONDITION" }, \171 { CXL_EVENT_RECORD_FLAG_MAINT_NEEDED, "MAINTENANCE_NEEDED" }, \172 { CXL_EVENT_RECORD_FLAG_PERF_DEGRADED, "PERFORMANCE_DEGRADED" }, \173 { CXL_EVENT_RECORD_FLAG_HW_REPLACE, "HARDWARE_REPLACEMENT_NEEDED" } \174)175 176/*177 * Define macros for the common header of each CXL event.178 *179 * Tracepoints using these macros must do 3 things:180 *181 * 1) Add CXL_EVT_TP_entry to TP_STRUCT__entry182 * 2) Use CXL_EVT_TP_fast_assign within TP_fast_assign;183 * pass the dev, log, and CXL event header184 * NOTE: The uuid must be assigned by the specific trace event185 * 3) Use CXL_EVT_TP_printk() instead of TP_printk()186 *187 * See the generic_event tracepoint as an example.188 */189#define CXL_EVT_TP_entry \190 __string(memdev, dev_name(&cxlmd->dev)) \191 __string(host, dev_name(cxlmd->dev.parent)) \192 __field(int, log) \193 __field_struct(uuid_t, hdr_uuid) \194 __field(u64, serial) \195 __field(u32, hdr_flags) \196 __field(u16, hdr_handle) \197 __field(u16, hdr_related_handle) \198 __field(u64, hdr_timestamp) \199 __field(u8, hdr_length) \200 __field(u8, hdr_maint_op_class)201 202#define CXL_EVT_TP_fast_assign(cxlmd, l, hdr) \203 __assign_str(memdev); \204 __assign_str(host); \205 __entry->log = (l); \206 __entry->serial = (cxlmd)->cxlds->serial; \207 __entry->hdr_length = (hdr).length; \208 __entry->hdr_flags = get_unaligned_le24((hdr).flags); \209 __entry->hdr_handle = le16_to_cpu((hdr).handle); \210 __entry->hdr_related_handle = le16_to_cpu((hdr).related_handle); \211 __entry->hdr_timestamp = le64_to_cpu((hdr).timestamp); \212 __entry->hdr_maint_op_class = (hdr).maint_op_class213 214#define CXL_EVT_TP_printk(fmt, ...) \215 TP_printk("memdev=%s host=%s serial=%lld log=%s : time=%llu uuid=%pUb " \216 "len=%d flags='%s' handle=%x related_handle=%x " \217 "maint_op_class=%u : " fmt, \218 __get_str(memdev), __get_str(host), __entry->serial, \219 cxl_event_log_type_str(__entry->log), \220 __entry->hdr_timestamp, &__entry->hdr_uuid, __entry->hdr_length,\221 show_hdr_flags(__entry->hdr_flags), __entry->hdr_handle, \222 __entry->hdr_related_handle, __entry->hdr_maint_op_class, \223 ##__VA_ARGS__)224 225TRACE_EVENT(cxl_generic_event,226 227 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log,228 const uuid_t *uuid, struct cxl_event_generic *gen_rec),229 230 TP_ARGS(cxlmd, log, uuid, gen_rec),231 232 TP_STRUCT__entry(233 CXL_EVT_TP_entry234 __array(u8, data, CXL_EVENT_RECORD_DATA_LENGTH)235 ),236 237 TP_fast_assign(238 CXL_EVT_TP_fast_assign(cxlmd, log, gen_rec->hdr);239 memcpy(&__entry->hdr_uuid, uuid, sizeof(uuid_t));240 memcpy(__entry->data, gen_rec->data, CXL_EVENT_RECORD_DATA_LENGTH);241 ),242 243 CXL_EVT_TP_printk("%s",244 __print_hex(__entry->data, CXL_EVENT_RECORD_DATA_LENGTH))245);246 247/*248 * Physical Address field masks249 *250 * General Media Event Record251 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43252 *253 * DRAM Event Record254 * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44255 */256#define CXL_DPA_FLAGS_MASK GENMASK(1, 0)257#define CXL_DPA_MASK GENMASK_ULL(63, 6)258 259#define CXL_DPA_VOLATILE BIT(0)260#define CXL_DPA_NOT_REPAIRABLE BIT(1)261#define show_dpa_flags(flags) __print_flags(flags, "|", \262 { CXL_DPA_VOLATILE, "VOLATILE" }, \263 { CXL_DPA_NOT_REPAIRABLE, "NOT_REPAIRABLE" } \264)265 266/*267 * General Media Event Record - GMER268 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43269 */270#define CXL_GMER_EVT_DESC_UNCORECTABLE_EVENT BIT(0)271#define CXL_GMER_EVT_DESC_THRESHOLD_EVENT BIT(1)272#define CXL_GMER_EVT_DESC_POISON_LIST_OVERFLOW BIT(2)273#define show_event_desc_flags(flags) __print_flags(flags, "|", \274 { CXL_GMER_EVT_DESC_UNCORECTABLE_EVENT, "UNCORRECTABLE_EVENT" }, \275 { CXL_GMER_EVT_DESC_THRESHOLD_EVENT, "THRESHOLD_EVENT" }, \276 { CXL_GMER_EVT_DESC_POISON_LIST_OVERFLOW, "POISON_LIST_OVERFLOW" } \277)278 279#define CXL_GMER_MEM_EVT_TYPE_ECC_ERROR 0x00280#define CXL_GMER_MEM_EVT_TYPE_INV_ADDR 0x01281#define CXL_GMER_MEM_EVT_TYPE_DATA_PATH_ERROR 0x02282#define show_gmer_mem_event_type(type) __print_symbolic(type, \283 { CXL_GMER_MEM_EVT_TYPE_ECC_ERROR, "ECC Error" }, \284 { CXL_GMER_MEM_EVT_TYPE_INV_ADDR, "Invalid Address" }, \285 { CXL_GMER_MEM_EVT_TYPE_DATA_PATH_ERROR, "Data Path Error" } \286)287 288#define CXL_GMER_TRANS_UNKNOWN 0x00289#define CXL_GMER_TRANS_HOST_READ 0x01290#define CXL_GMER_TRANS_HOST_WRITE 0x02291#define CXL_GMER_TRANS_HOST_SCAN_MEDIA 0x03292#define CXL_GMER_TRANS_HOST_INJECT_POISON 0x04293#define CXL_GMER_TRANS_INTERNAL_MEDIA_SCRUB 0x05294#define CXL_GMER_TRANS_INTERNAL_MEDIA_MANAGEMENT 0x06295#define show_trans_type(type) __print_symbolic(type, \296 { CXL_GMER_TRANS_UNKNOWN, "Unknown" }, \297 { CXL_GMER_TRANS_HOST_READ, "Host Read" }, \298 { CXL_GMER_TRANS_HOST_WRITE, "Host Write" }, \299 { CXL_GMER_TRANS_HOST_SCAN_MEDIA, "Host Scan Media" }, \300 { CXL_GMER_TRANS_HOST_INJECT_POISON, "Host Inject Poison" }, \301 { CXL_GMER_TRANS_INTERNAL_MEDIA_SCRUB, "Internal Media Scrub" }, \302 { CXL_GMER_TRANS_INTERNAL_MEDIA_MANAGEMENT, "Internal Media Management" } \303)304 305#define CXL_GMER_VALID_CHANNEL BIT(0)306#define CXL_GMER_VALID_RANK BIT(1)307#define CXL_GMER_VALID_DEVICE BIT(2)308#define CXL_GMER_VALID_COMPONENT BIT(3)309#define show_valid_flags(flags) __print_flags(flags, "|", \310 { CXL_GMER_VALID_CHANNEL, "CHANNEL" }, \311 { CXL_GMER_VALID_RANK, "RANK" }, \312 { CXL_GMER_VALID_DEVICE, "DEVICE" }, \313 { CXL_GMER_VALID_COMPONENT, "COMPONENT" } \314)315 316TRACE_EVENT(cxl_general_media,317 318 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log,319 struct cxl_region *cxlr, u64 hpa, struct cxl_event_gen_media *rec),320 321 TP_ARGS(cxlmd, log, cxlr, hpa, rec),322 323 TP_STRUCT__entry(324 CXL_EVT_TP_entry325 /* General Media */326 __field(u64, dpa)327 __field(u8, descriptor)328 __field(u8, type)329 __field(u8, transaction_type)330 __field(u8, channel)331 __field(u32, device)332 __array(u8, comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE)333 /* Following are out of order to pack trace record */334 __field(u64, hpa)335 __field_struct(uuid_t, region_uuid)336 __field(u16, validity_flags)337 __field(u8, rank)338 __field(u8, dpa_flags)339 __string(region_name, cxlr ? dev_name(&cxlr->dev) : "")340 ),341 342 TP_fast_assign(343 CXL_EVT_TP_fast_assign(cxlmd, log, rec->media_hdr.hdr);344 __entry->hdr_uuid = CXL_EVENT_GEN_MEDIA_UUID;345 346 /* General Media */347 __entry->dpa = le64_to_cpu(rec->media_hdr.phys_addr);348 __entry->dpa_flags = __entry->dpa & CXL_DPA_FLAGS_MASK;349 /* Mask after flags have been parsed */350 __entry->dpa &= CXL_DPA_MASK;351 __entry->descriptor = rec->media_hdr.descriptor;352 __entry->type = rec->media_hdr.type;353 __entry->transaction_type = rec->media_hdr.transaction_type;354 __entry->channel = rec->media_hdr.channel;355 __entry->rank = rec->media_hdr.rank;356 __entry->device = get_unaligned_le24(rec->device);357 memcpy(__entry->comp_id, &rec->component_id,358 CXL_EVENT_GEN_MED_COMP_ID_SIZE);359 __entry->validity_flags = get_unaligned_le16(&rec->media_hdr.validity_flags);360 __entry->hpa = hpa;361 if (cxlr) {362 __assign_str(region_name);363 uuid_copy(&__entry->region_uuid, &cxlr->params.uuid);364 } else {365 __assign_str(region_name);366 uuid_copy(&__entry->region_uuid, &uuid_null);367 }368 ),369 370 CXL_EVT_TP_printk("dpa=%llx dpa_flags='%s' " \371 "descriptor='%s' type='%s' transaction_type='%s' channel=%u rank=%u " \372 "device=%x comp_id=%s validity_flags='%s' " \373 "hpa=%llx region=%s region_uuid=%pUb",374 __entry->dpa, show_dpa_flags(__entry->dpa_flags),375 show_event_desc_flags(__entry->descriptor),376 show_gmer_mem_event_type(__entry->type),377 show_trans_type(__entry->transaction_type),378 __entry->channel, __entry->rank, __entry->device,379 __print_hex(__entry->comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE),380 show_valid_flags(__entry->validity_flags),381 __entry->hpa, __get_str(region_name), &__entry->region_uuid382 )383);384 385/*386 * DRAM Event Record - DER387 *388 * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44389 */390/*391 * DRAM Event Record defines many fields the same as the General Media Event392 * Record. Reuse those definitions as appropriate.393 */394#define CXL_DER_MEM_EVT_TYPE_ECC_ERROR 0x00395#define CXL_DER_MEM_EVT_TYPE_SCRUB_MEDIA_ECC_ERROR 0x01396#define CXL_DER_MEM_EVT_TYPE_INV_ADDR 0x02397#define CXL_DER_MEM_EVT_TYPE_DATA_PATH_ERROR 0x03398#define show_dram_mem_event_type(type) __print_symbolic(type, \399 { CXL_DER_MEM_EVT_TYPE_ECC_ERROR, "ECC Error" }, \400 { CXL_DER_MEM_EVT_TYPE_SCRUB_MEDIA_ECC_ERROR, "Scrub Media ECC Error" }, \401 { CXL_DER_MEM_EVT_TYPE_INV_ADDR, "Invalid Address" }, \402 { CXL_DER_MEM_EVT_TYPE_DATA_PATH_ERROR, "Data Path Error" } \403)404 405#define CXL_DER_VALID_CHANNEL BIT(0)406#define CXL_DER_VALID_RANK BIT(1)407#define CXL_DER_VALID_NIBBLE BIT(2)408#define CXL_DER_VALID_BANK_GROUP BIT(3)409#define CXL_DER_VALID_BANK BIT(4)410#define CXL_DER_VALID_ROW BIT(5)411#define CXL_DER_VALID_COLUMN BIT(6)412#define CXL_DER_VALID_CORRECTION_MASK BIT(7)413#define show_dram_valid_flags(flags) __print_flags(flags, "|", \414 { CXL_DER_VALID_CHANNEL, "CHANNEL" }, \415 { CXL_DER_VALID_RANK, "RANK" }, \416 { CXL_DER_VALID_NIBBLE, "NIBBLE" }, \417 { CXL_DER_VALID_BANK_GROUP, "BANK GROUP" }, \418 { CXL_DER_VALID_BANK, "BANK" }, \419 { CXL_DER_VALID_ROW, "ROW" }, \420 { CXL_DER_VALID_COLUMN, "COLUMN" }, \421 { CXL_DER_VALID_CORRECTION_MASK, "CORRECTION MASK" } \422)423 424TRACE_EVENT(cxl_dram,425 426 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log,427 struct cxl_region *cxlr, u64 hpa, struct cxl_event_dram *rec),428 429 TP_ARGS(cxlmd, log, cxlr, hpa, rec),430 431 TP_STRUCT__entry(432 CXL_EVT_TP_entry433 /* DRAM */434 __field(u64, dpa)435 __field(u8, descriptor)436 __field(u8, type)437 __field(u8, transaction_type)438 __field(u8, channel)439 __field(u16, validity_flags)440 __field(u16, column) /* Out of order to pack trace record */441 __field(u32, nibble_mask)442 __field(u32, row)443 __array(u8, cor_mask, CXL_EVENT_DER_CORRECTION_MASK_SIZE)444 __field(u64, hpa)445 __field_struct(uuid_t, region_uuid)446 __field(u8, rank) /* Out of order to pack trace record */447 __field(u8, bank_group) /* Out of order to pack trace record */448 __field(u8, bank) /* Out of order to pack trace record */449 __field(u8, dpa_flags) /* Out of order to pack trace record */450 __string(region_name, cxlr ? dev_name(&cxlr->dev) : "")451 ),452 453 TP_fast_assign(454 CXL_EVT_TP_fast_assign(cxlmd, log, rec->media_hdr.hdr);455 __entry->hdr_uuid = CXL_EVENT_DRAM_UUID;456 457 /* DRAM */458 __entry->dpa = le64_to_cpu(rec->media_hdr.phys_addr);459 __entry->dpa_flags = __entry->dpa & CXL_DPA_FLAGS_MASK;460 __entry->dpa &= CXL_DPA_MASK;461 __entry->descriptor = rec->media_hdr.descriptor;462 __entry->type = rec->media_hdr.type;463 __entry->transaction_type = rec->media_hdr.transaction_type;464 __entry->validity_flags = get_unaligned_le16(rec->media_hdr.validity_flags);465 __entry->channel = rec->media_hdr.channel;466 __entry->rank = rec->media_hdr.rank;467 __entry->nibble_mask = get_unaligned_le24(rec->nibble_mask);468 __entry->bank_group = rec->bank_group;469 __entry->bank = rec->bank;470 __entry->row = get_unaligned_le24(rec->row);471 __entry->column = get_unaligned_le16(rec->column);472 memcpy(__entry->cor_mask, &rec->correction_mask,473 CXL_EVENT_DER_CORRECTION_MASK_SIZE);474 __entry->hpa = hpa;475 if (cxlr) {476 __assign_str(region_name);477 uuid_copy(&__entry->region_uuid, &cxlr->params.uuid);478 } else {479 __assign_str(region_name);480 uuid_copy(&__entry->region_uuid, &uuid_null);481 }482 ),483 484 CXL_EVT_TP_printk("dpa=%llx dpa_flags='%s' descriptor='%s' type='%s' " \485 "transaction_type='%s' channel=%u rank=%u nibble_mask=%x " \486 "bank_group=%u bank=%u row=%u column=%u cor_mask=%s " \487 "validity_flags='%s' " \488 "hpa=%llx region=%s region_uuid=%pUb",489 __entry->dpa, show_dpa_flags(__entry->dpa_flags),490 show_event_desc_flags(__entry->descriptor),491 show_dram_mem_event_type(__entry->type),492 show_trans_type(__entry->transaction_type),493 __entry->channel, __entry->rank, __entry->nibble_mask,494 __entry->bank_group, __entry->bank,495 __entry->row, __entry->column,496 __print_hex(__entry->cor_mask, CXL_EVENT_DER_CORRECTION_MASK_SIZE),497 show_dram_valid_flags(__entry->validity_flags),498 __entry->hpa, __get_str(region_name), &__entry->region_uuid499 )500);501 502/*503 * Memory Module Event Record - MMER504 *505 * CXL res 3.0 section 8.2.9.2.1.3; Table 8-45506 */507#define CXL_MMER_HEALTH_STATUS_CHANGE 0x00508#define CXL_MMER_MEDIA_STATUS_CHANGE 0x01509#define CXL_MMER_LIFE_USED_CHANGE 0x02510#define CXL_MMER_TEMP_CHANGE 0x03511#define CXL_MMER_DATA_PATH_ERROR 0x04512#define CXL_MMER_LSA_ERROR 0x05513#define show_dev_evt_type(type) __print_symbolic(type, \514 { CXL_MMER_HEALTH_STATUS_CHANGE, "Health Status Change" }, \515 { CXL_MMER_MEDIA_STATUS_CHANGE, "Media Status Change" }, \516 { CXL_MMER_LIFE_USED_CHANGE, "Life Used Change" }, \517 { CXL_MMER_TEMP_CHANGE, "Temperature Change" }, \518 { CXL_MMER_DATA_PATH_ERROR, "Data Path Error" }, \519 { CXL_MMER_LSA_ERROR, "LSA Error" } \520)521 522/*523 * Device Health Information - DHI524 *525 * CXL res 3.0 section 8.2.9.8.3.1; Table 8-100526 */527#define CXL_DHI_HS_MAINTENANCE_NEEDED BIT(0)528#define CXL_DHI_HS_PERFORMANCE_DEGRADED BIT(1)529#define CXL_DHI_HS_HW_REPLACEMENT_NEEDED BIT(2)530#define show_health_status_flags(flags) __print_flags(flags, "|", \531 { CXL_DHI_HS_MAINTENANCE_NEEDED, "MAINTENANCE_NEEDED" }, \532 { CXL_DHI_HS_PERFORMANCE_DEGRADED, "PERFORMANCE_DEGRADED" }, \533 { CXL_DHI_HS_HW_REPLACEMENT_NEEDED, "REPLACEMENT_NEEDED" } \534)535 536#define CXL_DHI_MS_NORMAL 0x00537#define CXL_DHI_MS_NOT_READY 0x01538#define CXL_DHI_MS_WRITE_PERSISTENCY_LOST 0x02539#define CXL_DHI_MS_ALL_DATA_LOST 0x03540#define CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_EVENT_POWER_LOSS 0x04541#define CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_EVENT_SHUTDOWN 0x05542#define CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_IMMINENT 0x06543#define CXL_DHI_MS_WRITE_ALL_DATA_LOSS_EVENT_POWER_LOSS 0x07544#define CXL_DHI_MS_WRITE_ALL_DATA_LOSS_EVENT_SHUTDOWN 0x08545#define CXL_DHI_MS_WRITE_ALL_DATA_LOSS_IMMINENT 0x09546#define show_media_status(ms) __print_symbolic(ms, \547 { CXL_DHI_MS_NORMAL, \548 "Normal" }, \549 { CXL_DHI_MS_NOT_READY, \550 "Not Ready" }, \551 { CXL_DHI_MS_WRITE_PERSISTENCY_LOST, \552 "Write Persistency Lost" }, \553 { CXL_DHI_MS_ALL_DATA_LOST, \554 "All Data Lost" }, \555 { CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_EVENT_POWER_LOSS, \556 "Write Persistency Loss in the Event of Power Loss" }, \557 { CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_EVENT_SHUTDOWN, \558 "Write Persistency Loss in Event of Shutdown" }, \559 { CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_IMMINENT, \560 "Write Persistency Loss Imminent" }, \561 { CXL_DHI_MS_WRITE_ALL_DATA_LOSS_EVENT_POWER_LOSS, \562 "All Data Loss in Event of Power Loss" }, \563 { CXL_DHI_MS_WRITE_ALL_DATA_LOSS_EVENT_SHUTDOWN, \564 "All Data loss in the Event of Shutdown" }, \565 { CXL_DHI_MS_WRITE_ALL_DATA_LOSS_IMMINENT, \566 "All Data Loss Imminent" } \567)568 569#define CXL_DHI_AS_NORMAL 0x0570#define CXL_DHI_AS_WARNING 0x1571#define CXL_DHI_AS_CRITICAL 0x2572#define show_two_bit_status(as) __print_symbolic(as, \573 { CXL_DHI_AS_NORMAL, "Normal" }, \574 { CXL_DHI_AS_WARNING, "Warning" }, \575 { CXL_DHI_AS_CRITICAL, "Critical" } \576)577#define show_one_bit_status(as) __print_symbolic(as, \578 { CXL_DHI_AS_NORMAL, "Normal" }, \579 { CXL_DHI_AS_WARNING, "Warning" } \580)581 582#define CXL_DHI_AS_LIFE_USED(as) (as & 0x3)583#define CXL_DHI_AS_DEV_TEMP(as) ((as & 0xC) >> 2)584#define CXL_DHI_AS_COR_VOL_ERR_CNT(as) ((as & 0x10) >> 4)585#define CXL_DHI_AS_COR_PER_ERR_CNT(as) ((as & 0x20) >> 5)586 587TRACE_EVENT(cxl_memory_module,588 589 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log,590 struct cxl_event_mem_module *rec),591 592 TP_ARGS(cxlmd, log, rec),593 594 TP_STRUCT__entry(595 CXL_EVT_TP_entry596 597 /* Memory Module Event */598 __field(u8, event_type)599 600 /* Device Health Info */601 __field(u8, health_status)602 __field(u8, media_status)603 __field(u8, life_used)604 __field(u32, dirty_shutdown_cnt)605 __field(u32, cor_vol_err_cnt)606 __field(u32, cor_per_err_cnt)607 __field(s16, device_temp)608 __field(u8, add_status)609 ),610 611 TP_fast_assign(612 CXL_EVT_TP_fast_assign(cxlmd, log, rec->hdr);613 __entry->hdr_uuid = CXL_EVENT_MEM_MODULE_UUID;614 615 /* Memory Module Event */616 __entry->event_type = rec->event_type;617 618 /* Device Health Info */619 __entry->health_status = rec->info.health_status;620 __entry->media_status = rec->info.media_status;621 __entry->life_used = rec->info.life_used;622 __entry->dirty_shutdown_cnt = get_unaligned_le32(rec->info.dirty_shutdown_cnt);623 __entry->cor_vol_err_cnt = get_unaligned_le32(rec->info.cor_vol_err_cnt);624 __entry->cor_per_err_cnt = get_unaligned_le32(rec->info.cor_per_err_cnt);625 __entry->device_temp = get_unaligned_le16(rec->info.device_temp);626 __entry->add_status = rec->info.add_status;627 ),628 629 CXL_EVT_TP_printk("event_type='%s' health_status='%s' media_status='%s' " \630 "as_life_used=%s as_dev_temp=%s as_cor_vol_err_cnt=%s " \631 "as_cor_per_err_cnt=%s life_used=%u device_temp=%d " \632 "dirty_shutdown_cnt=%u cor_vol_err_cnt=%u cor_per_err_cnt=%u",633 show_dev_evt_type(__entry->event_type),634 show_health_status_flags(__entry->health_status),635 show_media_status(__entry->media_status),636 show_two_bit_status(CXL_DHI_AS_LIFE_USED(__entry->add_status)),637 show_two_bit_status(CXL_DHI_AS_DEV_TEMP(__entry->add_status)),638 show_one_bit_status(CXL_DHI_AS_COR_VOL_ERR_CNT(__entry->add_status)),639 show_one_bit_status(CXL_DHI_AS_COR_PER_ERR_CNT(__entry->add_status)),640 __entry->life_used, __entry->device_temp,641 __entry->dirty_shutdown_cnt, __entry->cor_vol_err_cnt,642 __entry->cor_per_err_cnt643 )644);645 646#define show_poison_trace_type(type) \647 __print_symbolic(type, \648 { CXL_POISON_TRACE_LIST, "List" }, \649 { CXL_POISON_TRACE_INJECT, "Inject" }, \650 { CXL_POISON_TRACE_CLEAR, "Clear" })651 652#define __show_poison_source(source) \653 __print_symbolic(source, \654 { CXL_POISON_SOURCE_UNKNOWN, "Unknown" }, \655 { CXL_POISON_SOURCE_EXTERNAL, "External" }, \656 { CXL_POISON_SOURCE_INTERNAL, "Internal" }, \657 { CXL_POISON_SOURCE_INJECTED, "Injected" }, \658 { CXL_POISON_SOURCE_VENDOR, "Vendor" })659 660#define show_poison_source(source) \661 (((source > CXL_POISON_SOURCE_INJECTED) && \662 (source != CXL_POISON_SOURCE_VENDOR)) ? "Reserved" \663 : __show_poison_source(source))664 665#define show_poison_flags(flags) \666 __print_flags(flags, "|", \667 { CXL_POISON_FLAG_MORE, "More" }, \668 { CXL_POISON_FLAG_OVERFLOW, "Overflow" }, \669 { CXL_POISON_FLAG_SCANNING, "Scanning" })670 671#define __cxl_poison_addr(record) \672 (le64_to_cpu(record->address))673#define cxl_poison_record_dpa(record) \674 (__cxl_poison_addr(record) & CXL_POISON_START_MASK)675#define cxl_poison_record_source(record) \676 (__cxl_poison_addr(record) & CXL_POISON_SOURCE_MASK)677#define cxl_poison_record_dpa_length(record) \678 (le32_to_cpu(record->length) * CXL_POISON_LEN_MULT)679#define cxl_poison_overflow(flags, time) \680 (flags & CXL_POISON_FLAG_OVERFLOW ? le64_to_cpu(time) : 0)681 682TRACE_EVENT(cxl_poison,683 684 TP_PROTO(struct cxl_memdev *cxlmd, struct cxl_region *cxlr,685 const struct cxl_poison_record *record, u8 flags,686 __le64 overflow_ts, enum cxl_poison_trace_type trace_type),687 688 TP_ARGS(cxlmd, cxlr, record, flags, overflow_ts, trace_type),689 690 TP_STRUCT__entry(691 __string(memdev, dev_name(&cxlmd->dev))692 __string(host, dev_name(cxlmd->dev.parent))693 __field(u64, serial)694 __field(u8, trace_type)695 __string(region, cxlr ? dev_name(&cxlr->dev) : "")696 __field(u64, overflow_ts)697 __field(u64, hpa)698 __field(u64, dpa)699 __field(u32, dpa_length)700 __array(char, uuid, 16)701 __field(u8, source)702 __field(u8, flags)703 ),704 705 TP_fast_assign(706 __assign_str(memdev);707 __assign_str(host);708 __entry->serial = cxlmd->cxlds->serial;709 __entry->overflow_ts = cxl_poison_overflow(flags, overflow_ts);710 __entry->dpa = cxl_poison_record_dpa(record);711 __entry->dpa_length = cxl_poison_record_dpa_length(record);712 __entry->source = cxl_poison_record_source(record);713 __entry->trace_type = trace_type;714 __entry->flags = flags;715 if (cxlr) {716 __assign_str(region);717 memcpy(__entry->uuid, &cxlr->params.uuid, 16);718 __entry->hpa = cxl_dpa_to_hpa(cxlr, cxlmd,719 __entry->dpa);720 } else {721 __assign_str(region);722 memset(__entry->uuid, 0, 16);723 __entry->hpa = ULLONG_MAX;724 }725 ),726 727 TP_printk("memdev=%s host=%s serial=%lld trace_type=%s region=%s " \728 "region_uuid=%pU hpa=0x%llx dpa=0x%llx dpa_length=0x%x " \729 "source=%s flags=%s overflow_time=%llu",730 __get_str(memdev),731 __get_str(host),732 __entry->serial,733 show_poison_trace_type(__entry->trace_type),734 __get_str(region),735 __entry->uuid,736 __entry->hpa,737 __entry->dpa,738 __entry->dpa_length,739 show_poison_source(__entry->source),740 show_poison_flags(__entry->flags),741 __entry->overflow_ts742 )743);744 745#endif /* _CXL_EVENTS_H */746 747#define TRACE_INCLUDE_FILE trace748#include <trace/define_trace.h>749