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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.4 * Synopsys DesignWare eDMA v0 core5 *6 * Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com>7 */8 9#ifndef _DW_EDMA_V0_REGS_H10#define _DW_EDMA_V0_REGS_H11 12#include <linux/dmaengine.h>13 14#define EDMA_V0_MAX_NR_CH 815#define EDMA_V0_VIEWPORT_MASK GENMASK(2, 0)16#define EDMA_V0_DONE_INT_MASK GENMASK(7, 0)17#define EDMA_V0_ABORT_INT_MASK GENMASK(23, 16)18#define EDMA_V0_WRITE_CH_COUNT_MASK GENMASK(3, 0)19#define EDMA_V0_READ_CH_COUNT_MASK GENMASK(19, 16)20#define EDMA_V0_CH_STATUS_MASK GENMASK(6, 5)21#define EDMA_V0_DOORBELL_CH_MASK GENMASK(2, 0)22#define EDMA_V0_LINKED_LIST_ERR_MASK GENMASK(7, 0)23 24#define EDMA_V0_CH_ODD_MSI_DATA_MASK GENMASK(31, 16)25#define EDMA_V0_CH_EVEN_MSI_DATA_MASK GENMASK(15, 0)26 27struct dw_edma_v0_ch_regs {28 u32 ch_control1; /* 0x0000 */29 u32 ch_control2; /* 0x0004 */30 u32 transfer_size; /* 0x0008 */31 union {32 u64 reg; /* 0x000c..0x0010 */33 struct {34 u32 lsb; /* 0x000c */35 u32 msb; /* 0x0010 */36 };37 } sar;38 union {39 u64 reg; /* 0x0014..0x0018 */40 struct {41 u32 lsb; /* 0x0014 */42 u32 msb; /* 0x0018 */43 };44 } dar;45 union {46 u64 reg; /* 0x001c..0x0020 */47 struct {48 u32 lsb; /* 0x001c */49 u32 msb; /* 0x0020 */50 };51 } llp;52} __packed;53 54struct dw_edma_v0_ch {55 struct dw_edma_v0_ch_regs wr; /* 0x0200 */56 u32 padding_1[55]; /* 0x0224..0x02fc */57 struct dw_edma_v0_ch_regs rd; /* 0x0300 */58 u32 padding_2[55]; /* 0x0324..0x03fc */59} __packed;60 61struct dw_edma_v0_unroll {62 u32 padding_1; /* 0x00f8 */63 u32 wr_engine_chgroup; /* 0x0100 */64 u32 rd_engine_chgroup; /* 0x0104 */65 union {66 u64 reg; /* 0x0108..0x010c */67 struct {68 u32 lsb; /* 0x0108 */69 u32 msb; /* 0x010c */70 };71 } wr_engine_hshake_cnt;72 u32 padding_2[2]; /* 0x0110..0x0114 */73 union {74 u64 reg; /* 0x0120..0x0124 */75 struct {76 u32 lsb; /* 0x0120 */77 u32 msb; /* 0x0124 */78 };79 } rd_engine_hshake_cnt;80 u32 padding_3[2]; /* 0x0120..0x0124 */81 u32 wr_ch0_pwr_en; /* 0x0128 */82 u32 wr_ch1_pwr_en; /* 0x012c */83 u32 wr_ch2_pwr_en; /* 0x0130 */84 u32 wr_ch3_pwr_en; /* 0x0134 */85 u32 wr_ch4_pwr_en; /* 0x0138 */86 u32 wr_ch5_pwr_en; /* 0x013c */87 u32 wr_ch6_pwr_en; /* 0x0140 */88 u32 wr_ch7_pwr_en; /* 0x0144 */89 u32 padding_4[8]; /* 0x0148..0x0164 */90 u32 rd_ch0_pwr_en; /* 0x0168 */91 u32 rd_ch1_pwr_en; /* 0x016c */92 u32 rd_ch2_pwr_en; /* 0x0170 */93 u32 rd_ch3_pwr_en; /* 0x0174 */94 u32 rd_ch4_pwr_en; /* 0x0178 */95 u32 rd_ch5_pwr_en; /* 0x018c */96 u32 rd_ch6_pwr_en; /* 0x0180 */97 u32 rd_ch7_pwr_en; /* 0x0184 */98 u32 padding_5[30]; /* 0x0188..0x01fc */99 struct dw_edma_v0_ch ch[EDMA_V0_MAX_NR_CH]; /* 0x0200..0x1120 */100} __packed;101 102struct dw_edma_v0_legacy {103 u32 viewport_sel; /* 0x00f8 */104 struct dw_edma_v0_ch_regs ch; /* 0x0100..0x0120 */105} __packed;106 107struct dw_edma_v0_regs {108 /* eDMA global registers */109 u32 ctrl_data_arb_prior; /* 0x0000 */110 u32 padding_1; /* 0x0004 */111 u32 ctrl; /* 0x0008 */112 u32 wr_engine_en; /* 0x000c */113 u32 wr_doorbell; /* 0x0010 */114 u32 padding_2; /* 0x0014 */115 union {116 u64 reg; /* 0x0018..0x001c */117 struct {118 u32 lsb; /* 0x0018 */119 u32 msb; /* 0x001c */120 };121 } wr_ch_arb_weight;122 u32 padding_3[3]; /* 0x0020..0x0028 */123 u32 rd_engine_en; /* 0x002c */124 u32 rd_doorbell; /* 0x0030 */125 u32 padding_4; /* 0x0034 */126 union {127 u64 reg; /* 0x0038..0x003c */128 struct {129 u32 lsb; /* 0x0038 */130 u32 msb; /* 0x003c */131 };132 } rd_ch_arb_weight;133 u32 padding_5[3]; /* 0x0040..0x0048 */134 /* eDMA interrupts registers */135 u32 wr_int_status; /* 0x004c */136 u32 padding_6; /* 0x0050 */137 u32 wr_int_mask; /* 0x0054 */138 u32 wr_int_clear; /* 0x0058 */139 u32 wr_err_status; /* 0x005c */140 union {141 u64 reg; /* 0x0060..0x0064 */142 struct {143 u32 lsb; /* 0x0060 */144 u32 msb; /* 0x0064 */145 };146 } wr_done_imwr;147 union {148 u64 reg; /* 0x0068..0x006c */149 struct {150 u32 lsb; /* 0x0068 */151 u32 msb; /* 0x006c */152 };153 } wr_abort_imwr;154 u32 wr_ch01_imwr_data; /* 0x0070 */155 u32 wr_ch23_imwr_data; /* 0x0074 */156 u32 wr_ch45_imwr_data; /* 0x0078 */157 u32 wr_ch67_imwr_data; /* 0x007c */158 u32 padding_7[4]; /* 0x0080..0x008c */159 u32 wr_linked_list_err_en; /* 0x0090 */160 u32 padding_8[3]; /* 0x0094..0x009c */161 u32 rd_int_status; /* 0x00a0 */162 u32 padding_9; /* 0x00a4 */163 u32 rd_int_mask; /* 0x00a8 */164 u32 rd_int_clear; /* 0x00ac */165 u32 padding_10; /* 0x00b0 */166 union {167 u64 reg; /* 0x00b4..0x00b8 */168 struct {169 u32 lsb; /* 0x00b4 */170 u32 msb; /* 0x00b8 */171 };172 } rd_err_status;173 u32 padding_11[2]; /* 0x00bc..0x00c0 */174 u32 rd_linked_list_err_en; /* 0x00c4 */175 u32 padding_12; /* 0x00c8 */176 union {177 u64 reg; /* 0x00cc..0x00d0 */178 struct {179 u32 lsb; /* 0x00cc */180 u32 msb; /* 0x00d0 */181 };182 } rd_done_imwr;183 union {184 u64 reg; /* 0x00d4..0x00d8 */185 struct {186 u32 lsb; /* 0x00d4 */187 u32 msb; /* 0x00d8 */188 };189 } rd_abort_imwr;190 u32 rd_ch01_imwr_data; /* 0x00dc */191 u32 rd_ch23_imwr_data; /* 0x00e0 */192 u32 rd_ch45_imwr_data; /* 0x00e4 */193 u32 rd_ch67_imwr_data; /* 0x00e8 */194 u32 padding_13[4]; /* 0x00ec..0x00f8 */195 /* eDMA channel context grouping */196 union dw_edma_v0_type {197 struct dw_edma_v0_legacy legacy; /* 0x00f8..0x0120 */198 struct dw_edma_v0_unroll unroll; /* 0x00f8..0x1120 */199 } type;200} __packed;201 202struct dw_edma_v0_lli {203 u32 control;204 u32 transfer_size;205 union {206 u64 reg;207 struct {208 u32 lsb;209 u32 msb;210 };211 } sar;212 union {213 u64 reg;214 struct {215 u32 lsb;216 u32 msb;217 };218 } dar;219} __packed;220 221struct dw_edma_v0_llp {222 u32 control;223 u32 reserved;224 union {225 u64 reg;226 struct {227 u32 lsb;228 u32 msb;229 };230 } llp;231} __packed;232 233#endif /* _DW_EDMA_V0_REGS_H */234