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1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * Driver for the Cirrus Logic EP93xx DMA Controller4 *5 * Copyright (C) 2011 Mika Westerberg6 *7 * DMA M2P implementation is based on the original8 * arch/arm/mach-ep93xx/dma-m2p.c which has following copyrights:9 *10 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>11 * Copyright (C) 2006 Applied Data Systems12 * Copyright (C) 2009 Ryan Mallon <rmallon@gmail.com>13 *14 * This driver is based on dw_dmac and amba-pl08x drivers.15 */16 17#include <linux/clk.h>18#include <linux/init.h>19#include <linux/interrupt.h>20#include <linux/dma-mapping.h>21#include <linux/dmaengine.h>22#include <linux/module.h>23#include <linux/mod_devicetable.h>24#include <linux/of_dma.h>25#include <linux/overflow.h>26#include <linux/platform_device.h>27#include <linux/slab.h>28 29#include "dmaengine.h"30 31/* M2P registers */32#define M2P_CONTROL 0x000033#define M2P_CONTROL_STALLINT BIT(0)34#define M2P_CONTROL_NFBINT BIT(1)35#define M2P_CONTROL_CH_ERROR_INT BIT(3)36#define M2P_CONTROL_ENABLE BIT(4)37#define M2P_CONTROL_ICE BIT(6)38 39#define M2P_INTERRUPT 0x000440#define M2P_INTERRUPT_STALL BIT(0)41#define M2P_INTERRUPT_NFB BIT(1)42#define M2P_INTERRUPT_ERROR BIT(3)43 44#define M2P_PPALLOC 0x000845#define M2P_STATUS 0x000c46 47#define M2P_MAXCNT0 0x002048#define M2P_BASE0 0x002449#define M2P_MAXCNT1 0x003050#define M2P_BASE1 0x003451 52#define M2P_STATE_IDLE 053#define M2P_STATE_STALL 154#define M2P_STATE_ON 255#define M2P_STATE_NEXT 356 57/* M2M registers */58#define M2M_CONTROL 0x000059#define M2M_CONTROL_DONEINT BIT(2)60#define M2M_CONTROL_ENABLE BIT(3)61#define M2M_CONTROL_START BIT(4)62#define M2M_CONTROL_DAH BIT(11)63#define M2M_CONTROL_SAH BIT(12)64#define M2M_CONTROL_PW_SHIFT 965#define M2M_CONTROL_PW_8 (0 << M2M_CONTROL_PW_SHIFT)66#define M2M_CONTROL_PW_16 (1 << M2M_CONTROL_PW_SHIFT)67#define M2M_CONTROL_PW_32 (2 << M2M_CONTROL_PW_SHIFT)68#define M2M_CONTROL_PW_MASK (3 << M2M_CONTROL_PW_SHIFT)69#define M2M_CONTROL_TM_SHIFT 1370#define M2M_CONTROL_TM_TX (1 << M2M_CONTROL_TM_SHIFT)71#define M2M_CONTROL_TM_RX (2 << M2M_CONTROL_TM_SHIFT)72#define M2M_CONTROL_NFBINT BIT(21)73#define M2M_CONTROL_RSS_SHIFT 2274#define M2M_CONTROL_RSS_SSPRX (1 << M2M_CONTROL_RSS_SHIFT)75#define M2M_CONTROL_RSS_SSPTX (2 << M2M_CONTROL_RSS_SHIFT)76#define M2M_CONTROL_RSS_IDE (3 << M2M_CONTROL_RSS_SHIFT)77#define M2M_CONTROL_NO_HDSK BIT(24)78#define M2M_CONTROL_PWSC_SHIFT 2579 80#define M2M_INTERRUPT 0x000481#define M2M_INTERRUPT_MASK 682 83#define M2M_STATUS 0x000c84#define M2M_STATUS_CTL_SHIFT 185#define M2M_STATUS_CTL_IDLE (0 << M2M_STATUS_CTL_SHIFT)86#define M2M_STATUS_CTL_STALL (1 << M2M_STATUS_CTL_SHIFT)87#define M2M_STATUS_CTL_MEMRD (2 << M2M_STATUS_CTL_SHIFT)88#define M2M_STATUS_CTL_MEMWR (3 << M2M_STATUS_CTL_SHIFT)89#define M2M_STATUS_CTL_BWCWAIT (4 << M2M_STATUS_CTL_SHIFT)90#define M2M_STATUS_CTL_MASK (7 << M2M_STATUS_CTL_SHIFT)91#define M2M_STATUS_BUF_SHIFT 492#define M2M_STATUS_BUF_NO (0 << M2M_STATUS_BUF_SHIFT)93#define M2M_STATUS_BUF_ON (1 << M2M_STATUS_BUF_SHIFT)94#define M2M_STATUS_BUF_NEXT (2 << M2M_STATUS_BUF_SHIFT)95#define M2M_STATUS_BUF_MASK (3 << M2M_STATUS_BUF_SHIFT)96#define M2M_STATUS_DONE BIT(6)97 98#define M2M_BCR0 0x001099#define M2M_BCR1 0x0014100#define M2M_SAR_BASE0 0x0018101#define M2M_SAR_BASE1 0x001c102#define M2M_DAR_BASE0 0x002c103#define M2M_DAR_BASE1 0x0030104 105#define DMA_MAX_CHAN_BYTES 0xffff106#define DMA_MAX_CHAN_DESCRIPTORS 32107 108/*109 * M2P channels.110 *111 * Note that these values are also directly used for setting the PPALLOC112 * register.113 */114#define EP93XX_DMA_I2S1 0115#define EP93XX_DMA_I2S2 1116#define EP93XX_DMA_AAC1 2117#define EP93XX_DMA_AAC2 3118#define EP93XX_DMA_AAC3 4119#define EP93XX_DMA_I2S3 5120#define EP93XX_DMA_UART1 6121#define EP93XX_DMA_UART2 7122#define EP93XX_DMA_UART3 8123#define EP93XX_DMA_IRDA 9124/* M2M channels */125#define EP93XX_DMA_SSP 10126#define EP93XX_DMA_IDE 11127 128enum ep93xx_dma_type {129 M2P_DMA,130 M2M_DMA,131};132 133struct ep93xx_dma_engine;134static int ep93xx_dma_slave_config_write(struct dma_chan *chan,135 enum dma_transfer_direction dir,136 struct dma_slave_config *config);137 138/**139 * struct ep93xx_dma_desc - EP93xx specific transaction descriptor140 * @src_addr: source address of the transaction141 * @dst_addr: destination address of the transaction142 * @size: size of the transaction (in bytes)143 * @complete: this descriptor is completed144 * @txd: dmaengine API descriptor145 * @tx_list: list of linked descriptors146 * @node: link used for putting this into a channel queue147 */148struct ep93xx_dma_desc {149 u32 src_addr;150 u32 dst_addr;151 size_t size;152 bool complete;153 struct dma_async_tx_descriptor txd;154 struct list_head tx_list;155 struct list_head node;156};157 158struct ep93xx_dma_chan_cfg {159 u8 port;160 enum dma_transfer_direction dir;161};162 163/**164 * struct ep93xx_dma_chan - an EP93xx DMA M2P/M2M channel165 * @chan: dmaengine API channel166 * @edma: pointer to the engine device167 * @regs: memory mapped registers168 * @dma_cfg: channel number, direction169 * @irq: interrupt number of the channel170 * @clk: clock used by this channel171 * @tasklet: channel specific tasklet used for callbacks172 * @lock: lock protecting the fields following173 * @flags: flags for the channel174 * @buffer: which buffer to use next (0/1)175 * @active: flattened chain of descriptors currently being processed176 * @queue: pending descriptors which are handled next177 * @free_list: list of free descriptors which can be used178 * @runtime_addr: physical address currently used as dest/src (M2M only). This179 * is set via .device_config before slave operation is180 * prepared181 * @runtime_ctrl: M2M runtime values for the control register.182 * @slave_config: slave configuration183 *184 * As EP93xx DMA controller doesn't support real chained DMA descriptors we185 * will have slightly different scheme here: @active points to a head of186 * flattened DMA descriptor chain.187 *188 * @queue holds pending transactions. These are linked through the first189 * descriptor in the chain. When a descriptor is moved to the @active queue,190 * the first and chained descriptors are flattened into a single list.191 *192 */193struct ep93xx_dma_chan {194 struct dma_chan chan;195 const struct ep93xx_dma_engine *edma;196 void __iomem *regs;197 struct ep93xx_dma_chan_cfg dma_cfg;198 int irq;199 struct clk *clk;200 struct tasklet_struct tasklet;201 /* protects the fields following */202 spinlock_t lock;203 unsigned long flags;204/* Channel is configured for cyclic transfers */205#define EP93XX_DMA_IS_CYCLIC 0206 207 int buffer;208 struct list_head active;209 struct list_head queue;210 struct list_head free_list;211 u32 runtime_addr;212 u32 runtime_ctrl;213 struct dma_slave_config slave_config;214};215 216/**217 * struct ep93xx_dma_engine - the EP93xx DMA engine instance218 * @dma_dev: holds the dmaengine device219 * @m2m: is this an M2M or M2P device220 * @hw_setup: method which sets the channel up for operation221 * @hw_synchronize: synchronizes DMA channel termination to current context222 * @hw_shutdown: shuts the channel down and flushes whatever is left223 * @hw_submit: pushes active descriptor(s) to the hardware224 * @hw_interrupt: handle the interrupt225 * @num_channels: number of channels for this instance226 * @channels: array of channels227 *228 * There is one instance of this struct for the M2P channels and one for the229 * M2M channels. hw_xxx() methods are used to perform operations which are230 * different on M2M and M2P channels. These methods are called with channel231 * lock held and interrupts disabled so they cannot sleep.232 */233struct ep93xx_dma_engine {234 struct dma_device dma_dev;235 bool m2m;236 int (*hw_setup)(struct ep93xx_dma_chan *);237 void (*hw_synchronize)(struct ep93xx_dma_chan *);238 void (*hw_shutdown)(struct ep93xx_dma_chan *);239 void (*hw_submit)(struct ep93xx_dma_chan *);240 int (*hw_interrupt)(struct ep93xx_dma_chan *);241#define INTERRUPT_UNKNOWN 0242#define INTERRUPT_DONE 1243#define INTERRUPT_NEXT_BUFFER 2244 245 size_t num_channels;246 struct ep93xx_dma_chan channels[] __counted_by(num_channels);247};248 249struct ep93xx_edma_data {250 u32 id;251 size_t num_channels;252};253 254static inline struct device *chan2dev(struct ep93xx_dma_chan *edmac)255{256 return &edmac->chan.dev->device;257}258 259static struct ep93xx_dma_chan *to_ep93xx_dma_chan(struct dma_chan *chan)260{261 return container_of(chan, struct ep93xx_dma_chan, chan);262}263 264static inline bool ep93xx_dma_chan_is_m2p(struct dma_chan *chan)265{266 if (device_is_compatible(chan->device->dev, "cirrus,ep9301-dma-m2p"))267 return true;268 269 return !strcmp(dev_name(chan->device->dev), "ep93xx-dma-m2p");270}271 272/*273 * ep93xx_dma_chan_direction - returns direction the channel can be used274 *275 * This function can be used in filter functions to find out whether the276 * channel supports given DMA direction. Only M2P channels have such277 * limitation, for M2M channels the direction is configurable.278 */279static inline enum dma_transfer_direction280ep93xx_dma_chan_direction(struct dma_chan *chan)281{282 if (!ep93xx_dma_chan_is_m2p(chan))283 return DMA_TRANS_NONE;284 285 /* even channels are for TX, odd for RX */286 return (chan->chan_id % 2 == 0) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;287}288 289/**290 * ep93xx_dma_set_active - set new active descriptor chain291 * @edmac: channel292 * @desc: head of the new active descriptor chain293 *294 * Sets @desc to be the head of the new active descriptor chain. This is the295 * chain which is processed next. The active list must be empty before calling296 * this function.297 *298 * Called with @edmac->lock held and interrupts disabled.299 */300static void ep93xx_dma_set_active(struct ep93xx_dma_chan *edmac,301 struct ep93xx_dma_desc *desc)302{303 BUG_ON(!list_empty(&edmac->active));304 305 list_add_tail(&desc->node, &edmac->active);306 307 /* Flatten the @desc->tx_list chain into @edmac->active list */308 while (!list_empty(&desc->tx_list)) {309 struct ep93xx_dma_desc *d = list_first_entry(&desc->tx_list,310 struct ep93xx_dma_desc, node);311 312 /*313 * We copy the callback parameters from the first descriptor314 * to all the chained descriptors. This way we can call the315 * callback without having to find out the first descriptor in316 * the chain. Useful for cyclic transfers.317 */318 d->txd.callback = desc->txd.callback;319 d->txd.callback_param = desc->txd.callback_param;320 321 list_move_tail(&d->node, &edmac->active);322 }323}324 325/* Called with @edmac->lock held and interrupts disabled */326static struct ep93xx_dma_desc *327ep93xx_dma_get_active(struct ep93xx_dma_chan *edmac)328{329 return list_first_entry_or_null(&edmac->active,330 struct ep93xx_dma_desc, node);331}332 333/**334 * ep93xx_dma_advance_active - advances to the next active descriptor335 * @edmac: channel336 *337 * Function advances active descriptor to the next in the @edmac->active and338 * returns %true if we still have descriptors in the chain to process.339 * Otherwise returns %false.340 *341 * When the channel is in cyclic mode always returns %true.342 *343 * Called with @edmac->lock held and interrupts disabled.344 */345static bool ep93xx_dma_advance_active(struct ep93xx_dma_chan *edmac)346{347 struct ep93xx_dma_desc *desc;348 349 list_rotate_left(&edmac->active);350 351 if (test_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags))352 return true;353 354 desc = ep93xx_dma_get_active(edmac);355 if (!desc)356 return false;357 358 /*359 * If txd.cookie is set it means that we are back in the first360 * descriptor in the chain and hence done with it.361 */362 return !desc->txd.cookie;363}364 365/*366 * M2P DMA implementation367 */368 369static void m2p_set_control(struct ep93xx_dma_chan *edmac, u32 control)370{371 writel(control, edmac->regs + M2P_CONTROL);372 /*373 * EP93xx User's Guide states that we must perform a dummy read after374 * write to the control register.375 */376 readl(edmac->regs + M2P_CONTROL);377}378 379static int m2p_hw_setup(struct ep93xx_dma_chan *edmac)380{381 u32 control;382 383 writel(edmac->dma_cfg.port & 0xf, edmac->regs + M2P_PPALLOC);384 385 control = M2P_CONTROL_CH_ERROR_INT | M2P_CONTROL_ICE386 | M2P_CONTROL_ENABLE;387 m2p_set_control(edmac, control);388 389 edmac->buffer = 0;390 391 return 0;392}393 394static inline u32 m2p_channel_state(struct ep93xx_dma_chan *edmac)395{396 return (readl(edmac->regs + M2P_STATUS) >> 4) & 0x3;397}398 399static void m2p_hw_synchronize(struct ep93xx_dma_chan *edmac)400{401 unsigned long flags;402 u32 control;403 404 spin_lock_irqsave(&edmac->lock, flags);405 control = readl(edmac->regs + M2P_CONTROL);406 control &= ~(M2P_CONTROL_STALLINT | M2P_CONTROL_NFBINT);407 m2p_set_control(edmac, control);408 spin_unlock_irqrestore(&edmac->lock, flags);409 410 while (m2p_channel_state(edmac) >= M2P_STATE_ON)411 schedule();412}413 414static void m2p_hw_shutdown(struct ep93xx_dma_chan *edmac)415{416 m2p_set_control(edmac, 0);417 418 while (m2p_channel_state(edmac) != M2P_STATE_IDLE)419 dev_warn(chan2dev(edmac), "M2P: Not yet IDLE\n");420}421 422static void m2p_fill_desc(struct ep93xx_dma_chan *edmac)423{424 struct ep93xx_dma_desc *desc;425 u32 bus_addr;426 427 desc = ep93xx_dma_get_active(edmac);428 if (!desc) {429 dev_warn(chan2dev(edmac), "M2P: empty descriptor list\n");430 return;431 }432 433 if (ep93xx_dma_chan_direction(&edmac->chan) == DMA_MEM_TO_DEV)434 bus_addr = desc->src_addr;435 else436 bus_addr = desc->dst_addr;437 438 if (edmac->buffer == 0) {439 writel(desc->size, edmac->regs + M2P_MAXCNT0);440 writel(bus_addr, edmac->regs + M2P_BASE0);441 } else {442 writel(desc->size, edmac->regs + M2P_MAXCNT1);443 writel(bus_addr, edmac->regs + M2P_BASE1);444 }445 446 edmac->buffer ^= 1;447}448 449static void m2p_hw_submit(struct ep93xx_dma_chan *edmac)450{451 u32 control = readl(edmac->regs + M2P_CONTROL);452 453 m2p_fill_desc(edmac);454 control |= M2P_CONTROL_STALLINT;455 456 if (ep93xx_dma_advance_active(edmac)) {457 m2p_fill_desc(edmac);458 control |= M2P_CONTROL_NFBINT;459 }460 461 m2p_set_control(edmac, control);462}463 464static int m2p_hw_interrupt(struct ep93xx_dma_chan *edmac)465{466 u32 irq_status = readl(edmac->regs + M2P_INTERRUPT);467 u32 control;468 469 if (irq_status & M2P_INTERRUPT_ERROR) {470 struct ep93xx_dma_desc *desc = ep93xx_dma_get_active(edmac);471 472 /* Clear the error interrupt */473 writel(1, edmac->regs + M2P_INTERRUPT);474 475 /*476 * It seems that there is no easy way of reporting errors back477 * to client so we just report the error here and continue as478 * usual.479 *480 * Revisit this when there is a mechanism to report back the481 * errors.482 */483 dev_err(chan2dev(edmac),484 "DMA transfer failed! Details:\n"485 "\tcookie : %d\n"486 "\tsrc_addr : 0x%08x\n"487 "\tdst_addr : 0x%08x\n"488 "\tsize : %zu\n",489 desc->txd.cookie, desc->src_addr, desc->dst_addr,490 desc->size);491 }492 493 /*494 * Even latest E2 silicon revision sometimes assert STALL interrupt495 * instead of NFB. Therefore we treat them equally, basing on the496 * amount of data we still have to transfer.497 */498 if (!(irq_status & (M2P_INTERRUPT_STALL | M2P_INTERRUPT_NFB)))499 return INTERRUPT_UNKNOWN;500 501 if (ep93xx_dma_advance_active(edmac)) {502 m2p_fill_desc(edmac);503 return INTERRUPT_NEXT_BUFFER;504 }505 506 /* Disable interrupts */507 control = readl(edmac->regs + M2P_CONTROL);508 control &= ~(M2P_CONTROL_STALLINT | M2P_CONTROL_NFBINT);509 m2p_set_control(edmac, control);510 511 return INTERRUPT_DONE;512}513 514/*515 * M2M DMA implementation516 */517 518static int m2m_hw_setup(struct ep93xx_dma_chan *edmac)519{520 u32 control = 0;521 522 if (edmac->dma_cfg.dir == DMA_MEM_TO_MEM) {523 /* This is memcpy channel, nothing to configure */524 writel(control, edmac->regs + M2M_CONTROL);525 return 0;526 }527 528 switch (edmac->dma_cfg.port) {529 case EP93XX_DMA_SSP:530 /*531 * This was found via experimenting - anything less than 5532 * causes the channel to perform only a partial transfer which533 * leads to problems since we don't get DONE interrupt then.534 */535 control = (5 << M2M_CONTROL_PWSC_SHIFT);536 control |= M2M_CONTROL_NO_HDSK;537 538 if (edmac->dma_cfg.dir == DMA_MEM_TO_DEV) {539 control |= M2M_CONTROL_DAH;540 control |= M2M_CONTROL_TM_TX;541 control |= M2M_CONTROL_RSS_SSPTX;542 } else {543 control |= M2M_CONTROL_SAH;544 control |= M2M_CONTROL_TM_RX;545 control |= M2M_CONTROL_RSS_SSPRX;546 }547 break;548 549 case EP93XX_DMA_IDE:550 /*551 * This IDE part is totally untested. Values below are taken552 * from the EP93xx Users's Guide and might not be correct.553 */554 if (edmac->dma_cfg.dir == DMA_MEM_TO_DEV) {555 /* Worst case from the UG */556 control = (3 << M2M_CONTROL_PWSC_SHIFT);557 control |= M2M_CONTROL_DAH;558 control |= M2M_CONTROL_TM_TX;559 } else {560 control = (2 << M2M_CONTROL_PWSC_SHIFT);561 control |= M2M_CONTROL_SAH;562 control |= M2M_CONTROL_TM_RX;563 }564 565 control |= M2M_CONTROL_NO_HDSK;566 control |= M2M_CONTROL_RSS_IDE;567 control |= M2M_CONTROL_PW_16;568 break;569 570 default:571 return -EINVAL;572 }573 574 writel(control, edmac->regs + M2M_CONTROL);575 return 0;576}577 578static void m2m_hw_shutdown(struct ep93xx_dma_chan *edmac)579{580 /* Just disable the channel */581 writel(0, edmac->regs + M2M_CONTROL);582}583 584static void m2m_fill_desc(struct ep93xx_dma_chan *edmac)585{586 struct ep93xx_dma_desc *desc;587 588 desc = ep93xx_dma_get_active(edmac);589 if (!desc) {590 dev_warn(chan2dev(edmac), "M2M: empty descriptor list\n");591 return;592 }593 594 if (edmac->buffer == 0) {595 writel(desc->src_addr, edmac->regs + M2M_SAR_BASE0);596 writel(desc->dst_addr, edmac->regs + M2M_DAR_BASE0);597 writel(desc->size, edmac->regs + M2M_BCR0);598 } else {599 writel(desc->src_addr, edmac->regs + M2M_SAR_BASE1);600 writel(desc->dst_addr, edmac->regs + M2M_DAR_BASE1);601 writel(desc->size, edmac->regs + M2M_BCR1);602 }603 604 edmac->buffer ^= 1;605}606 607static void m2m_hw_submit(struct ep93xx_dma_chan *edmac)608{609 u32 control = readl(edmac->regs + M2M_CONTROL);610 611 /*612 * Since we allow clients to configure PW (peripheral width) we always613 * clear PW bits here and then set them according what is given in614 * the runtime configuration.615 */616 control &= ~M2M_CONTROL_PW_MASK;617 control |= edmac->runtime_ctrl;618 619 m2m_fill_desc(edmac);620 control |= M2M_CONTROL_DONEINT;621 622 if (ep93xx_dma_advance_active(edmac)) {623 m2m_fill_desc(edmac);624 control |= M2M_CONTROL_NFBINT;625 }626 627 /*628 * Now we can finally enable the channel. For M2M channel this must be629 * done _after_ the BCRx registers are programmed.630 */631 control |= M2M_CONTROL_ENABLE;632 writel(control, edmac->regs + M2M_CONTROL);633 634 if (edmac->dma_cfg.dir == DMA_MEM_TO_MEM) {635 /*636 * For memcpy channels the software trigger must be asserted637 * in order to start the memcpy operation.638 */639 control |= M2M_CONTROL_START;640 writel(control, edmac->regs + M2M_CONTROL);641 }642}643 644/*645 * According to EP93xx User's Guide, we should receive DONE interrupt when all646 * M2M DMA controller transactions complete normally. This is not always the647 * case - sometimes EP93xx M2M DMA asserts DONE interrupt when the DMA channel648 * is still running (channel Buffer FSM in DMA_BUF_ON state, and channel649 * Control FSM in DMA_MEM_RD state, observed at least in IDE-DMA operation).650 * In effect, disabling the channel when only DONE bit is set could stop651 * currently running DMA transfer. To avoid this, we use Buffer FSM and652 * Control FSM to check current state of DMA channel.653 */654static int m2m_hw_interrupt(struct ep93xx_dma_chan *edmac)655{656 u32 status = readl(edmac->regs + M2M_STATUS);657 u32 ctl_fsm = status & M2M_STATUS_CTL_MASK;658 u32 buf_fsm = status & M2M_STATUS_BUF_MASK;659 bool done = status & M2M_STATUS_DONE;660 bool last_done;661 u32 control;662 struct ep93xx_dma_desc *desc;663 664 /* Accept only DONE and NFB interrupts */665 if (!(readl(edmac->regs + M2M_INTERRUPT) & M2M_INTERRUPT_MASK))666 return INTERRUPT_UNKNOWN;667 668 if (done) {669 /* Clear the DONE bit */670 writel(0, edmac->regs + M2M_INTERRUPT);671 }672 673 /*674 * Check whether we are done with descriptors or not. This, together675 * with DMA channel state, determines action to take in interrupt.676 */677 desc = ep93xx_dma_get_active(edmac);678 last_done = !desc || desc->txd.cookie;679 680 /*681 * Use M2M DMA Buffer FSM and Control FSM to check current state of682 * DMA channel. Using DONE and NFB bits from channel status register683 * or bits from channel interrupt register is not reliable.684 */685 if (!last_done &&686 (buf_fsm == M2M_STATUS_BUF_NO ||687 buf_fsm == M2M_STATUS_BUF_ON)) {688 /*689 * Two buffers are ready for update when Buffer FSM is in690 * DMA_NO_BUF state. Only one buffer can be prepared without691 * disabling the channel or polling the DONE bit.692 * To simplify things, always prepare only one buffer.693 */694 if (ep93xx_dma_advance_active(edmac)) {695 m2m_fill_desc(edmac);696 if (done && edmac->dma_cfg.dir == DMA_MEM_TO_MEM) {697 /* Software trigger for memcpy channel */698 control = readl(edmac->regs + M2M_CONTROL);699 control |= M2M_CONTROL_START;700 writel(control, edmac->regs + M2M_CONTROL);701 }702 return INTERRUPT_NEXT_BUFFER;703 } else {704 last_done = true;705 }706 }707 708 /*709 * Disable the channel only when Buffer FSM is in DMA_NO_BUF state710 * and Control FSM is in DMA_STALL state.711 */712 if (last_done &&713 buf_fsm == M2M_STATUS_BUF_NO &&714 ctl_fsm == M2M_STATUS_CTL_STALL) {715 /* Disable interrupts and the channel */716 control = readl(edmac->regs + M2M_CONTROL);717 control &= ~(M2M_CONTROL_DONEINT | M2M_CONTROL_NFBINT718 | M2M_CONTROL_ENABLE);719 writel(control, edmac->regs + M2M_CONTROL);720 return INTERRUPT_DONE;721 }722 723 /*724 * Nothing to do this time.725 */726 return INTERRUPT_NEXT_BUFFER;727}728 729/*730 * DMA engine API implementation731 */732 733static struct ep93xx_dma_desc *734ep93xx_dma_desc_get(struct ep93xx_dma_chan *edmac)735{736 struct ep93xx_dma_desc *desc, *_desc;737 struct ep93xx_dma_desc *ret = NULL;738 unsigned long flags;739 740 spin_lock_irqsave(&edmac->lock, flags);741 list_for_each_entry_safe(desc, _desc, &edmac->free_list, node) {742 if (async_tx_test_ack(&desc->txd)) {743 list_del_init(&desc->node);744 745 /* Re-initialize the descriptor */746 desc->src_addr = 0;747 desc->dst_addr = 0;748 desc->size = 0;749 desc->complete = false;750 desc->txd.cookie = 0;751 desc->txd.callback = NULL;752 desc->txd.callback_param = NULL;753 754 ret = desc;755 break;756 }757 }758 spin_unlock_irqrestore(&edmac->lock, flags);759 return ret;760}761 762static void ep93xx_dma_desc_put(struct ep93xx_dma_chan *edmac,763 struct ep93xx_dma_desc *desc)764{765 if (desc) {766 unsigned long flags;767 768 spin_lock_irqsave(&edmac->lock, flags);769 list_splice_init(&desc->tx_list, &edmac->free_list);770 list_add(&desc->node, &edmac->free_list);771 spin_unlock_irqrestore(&edmac->lock, flags);772 }773}774 775/**776 * ep93xx_dma_advance_work - start processing the next pending transaction777 * @edmac: channel778 *779 * If we have pending transactions queued and we are currently idling, this780 * function takes the next queued transaction from the @edmac->queue and781 * pushes it to the hardware for execution.782 */783static void ep93xx_dma_advance_work(struct ep93xx_dma_chan *edmac)784{785 struct ep93xx_dma_desc *new;786 unsigned long flags;787 788 spin_lock_irqsave(&edmac->lock, flags);789 if (!list_empty(&edmac->active) || list_empty(&edmac->queue)) {790 spin_unlock_irqrestore(&edmac->lock, flags);791 return;792 }793 794 /* Take the next descriptor from the pending queue */795 new = list_first_entry(&edmac->queue, struct ep93xx_dma_desc, node);796 list_del_init(&new->node);797 798 ep93xx_dma_set_active(edmac, new);799 800 /* Push it to the hardware */801 edmac->edma->hw_submit(edmac);802 spin_unlock_irqrestore(&edmac->lock, flags);803}804 805static void ep93xx_dma_tasklet(struct tasklet_struct *t)806{807 struct ep93xx_dma_chan *edmac = from_tasklet(edmac, t, tasklet);808 struct ep93xx_dma_desc *desc, *d;809 struct dmaengine_desc_callback cb;810 LIST_HEAD(list);811 812 memset(&cb, 0, sizeof(cb));813 spin_lock_irq(&edmac->lock);814 /*815 * If dma_terminate_all() was called before we get to run, the active816 * list has become empty. If that happens we aren't supposed to do817 * anything more than call ep93xx_dma_advance_work().818 */819 desc = ep93xx_dma_get_active(edmac);820 if (desc) {821 if (desc->complete) {822 /* mark descriptor complete for non cyclic case only */823 if (!test_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags))824 dma_cookie_complete(&desc->txd);825 list_splice_init(&edmac->active, &list);826 }827 dmaengine_desc_get_callback(&desc->txd, &cb);828 }829 spin_unlock_irq(&edmac->lock);830 831 /* Pick up the next descriptor from the queue */832 ep93xx_dma_advance_work(edmac);833 834 /* Now we can release all the chained descriptors */835 list_for_each_entry_safe(desc, d, &list, node) {836 dma_descriptor_unmap(&desc->txd);837 ep93xx_dma_desc_put(edmac, desc);838 }839 840 dmaengine_desc_callback_invoke(&cb, NULL);841}842 843static irqreturn_t ep93xx_dma_interrupt(int irq, void *dev_id)844{845 struct ep93xx_dma_chan *edmac = dev_id;846 struct ep93xx_dma_desc *desc;847 irqreturn_t ret = IRQ_HANDLED;848 849 spin_lock(&edmac->lock);850 851 desc = ep93xx_dma_get_active(edmac);852 if (!desc) {853 dev_warn(chan2dev(edmac),854 "got interrupt while active list is empty\n");855 spin_unlock(&edmac->lock);856 return IRQ_NONE;857 }858 859 switch (edmac->edma->hw_interrupt(edmac)) {860 case INTERRUPT_DONE:861 desc->complete = true;862 tasklet_schedule(&edmac->tasklet);863 break;864 865 case INTERRUPT_NEXT_BUFFER:866 if (test_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags))867 tasklet_schedule(&edmac->tasklet);868 break;869 870 default:871 dev_warn(chan2dev(edmac), "unknown interrupt!\n");872 ret = IRQ_NONE;873 break;874 }875 876 spin_unlock(&edmac->lock);877 return ret;878}879 880/**881 * ep93xx_dma_tx_submit - set the prepared descriptor(s) to be executed882 * @tx: descriptor to be executed883 *884 * Function will execute given descriptor on the hardware or if the hardware885 * is busy, queue the descriptor to be executed later on. Returns cookie which886 * can be used to poll the status of the descriptor.887 */888static dma_cookie_t ep93xx_dma_tx_submit(struct dma_async_tx_descriptor *tx)889{890 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(tx->chan);891 struct ep93xx_dma_desc *desc;892 dma_cookie_t cookie;893 unsigned long flags;894 895 spin_lock_irqsave(&edmac->lock, flags);896 cookie = dma_cookie_assign(tx);897 898 desc = container_of(tx, struct ep93xx_dma_desc, txd);899 900 /*901 * If nothing is currently processed, we push this descriptor902 * directly to the hardware. Otherwise we put the descriptor903 * to the pending queue.904 */905 if (list_empty(&edmac->active)) {906 ep93xx_dma_set_active(edmac, desc);907 edmac->edma->hw_submit(edmac);908 } else {909 list_add_tail(&desc->node, &edmac->queue);910 }911 912 spin_unlock_irqrestore(&edmac->lock, flags);913 return cookie;914}915 916/**917 * ep93xx_dma_alloc_chan_resources - allocate resources for the channel918 * @chan: channel to allocate resources919 *920 * Function allocates necessary resources for the given DMA channel and921 * returns number of allocated descriptors for the channel. Negative errno922 * is returned in case of failure.923 */924static int ep93xx_dma_alloc_chan_resources(struct dma_chan *chan)925{926 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);927 const char *name = dma_chan_name(chan);928 int ret, i;929 930 /* Sanity check the channel parameters */931 if (!edmac->edma->m2m) {932 if (edmac->dma_cfg.port < EP93XX_DMA_I2S1 ||933 edmac->dma_cfg.port > EP93XX_DMA_IRDA)934 return -EINVAL;935 if (edmac->dma_cfg.dir != ep93xx_dma_chan_direction(chan))936 return -EINVAL;937 } else {938 if (edmac->dma_cfg.dir != DMA_MEM_TO_MEM) {939 switch (edmac->dma_cfg.port) {940 case EP93XX_DMA_SSP:941 case EP93XX_DMA_IDE:942 if (!is_slave_direction(edmac->dma_cfg.dir))943 return -EINVAL;944 break;945 default:946 return -EINVAL;947 }948 }949 }950 951 ret = clk_prepare_enable(edmac->clk);952 if (ret)953 return ret;954 955 ret = request_irq(edmac->irq, ep93xx_dma_interrupt, 0, name, edmac);956 if (ret)957 goto fail_clk_disable;958 959 spin_lock_irq(&edmac->lock);960 dma_cookie_init(&edmac->chan);961 ret = edmac->edma->hw_setup(edmac);962 spin_unlock_irq(&edmac->lock);963 964 if (ret)965 goto fail_free_irq;966 967 for (i = 0; i < DMA_MAX_CHAN_DESCRIPTORS; i++) {968 struct ep93xx_dma_desc *desc;969 970 desc = kzalloc(sizeof(*desc), GFP_KERNEL);971 if (!desc) {972 dev_warn(chan2dev(edmac), "not enough descriptors\n");973 break;974 }975 976 INIT_LIST_HEAD(&desc->tx_list);977 978 dma_async_tx_descriptor_init(&desc->txd, chan);979 desc->txd.flags = DMA_CTRL_ACK;980 desc->txd.tx_submit = ep93xx_dma_tx_submit;981 982 ep93xx_dma_desc_put(edmac, desc);983 }984 985 return i;986 987fail_free_irq:988 free_irq(edmac->irq, edmac);989fail_clk_disable:990 clk_disable_unprepare(edmac->clk);991 992 return ret;993}994 995/**996 * ep93xx_dma_free_chan_resources - release resources for the channel997 * @chan: channel998 *999 * Function releases all the resources allocated for the given channel.1000 * The channel must be idle when this is called.1001 */1002static void ep93xx_dma_free_chan_resources(struct dma_chan *chan)1003{1004 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);1005 struct ep93xx_dma_desc *desc, *d;1006 unsigned long flags;1007 LIST_HEAD(list);1008 1009 BUG_ON(!list_empty(&edmac->active));1010 BUG_ON(!list_empty(&edmac->queue));1011 1012 spin_lock_irqsave(&edmac->lock, flags);1013 edmac->edma->hw_shutdown(edmac);1014 edmac->runtime_addr = 0;1015 edmac->runtime_ctrl = 0;1016 edmac->buffer = 0;1017 list_splice_init(&edmac->free_list, &list);1018 spin_unlock_irqrestore(&edmac->lock, flags);1019 1020 list_for_each_entry_safe(desc, d, &list, node)1021 kfree(desc);1022 1023 clk_disable_unprepare(edmac->clk);1024 free_irq(edmac->irq, edmac);1025}1026 1027/**1028 * ep93xx_dma_prep_dma_memcpy - prepare a memcpy DMA operation1029 * @chan: channel1030 * @dest: destination bus address1031 * @src: source bus address1032 * @len: size of the transaction1033 * @flags: flags for the descriptor1034 *1035 * Returns a valid DMA descriptor or %NULL in case of failure.1036 */1037static struct dma_async_tx_descriptor *1038ep93xx_dma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest,1039 dma_addr_t src, size_t len, unsigned long flags)1040{1041 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);1042 struct ep93xx_dma_desc *desc, *first;1043 size_t bytes, offset;1044 1045 first = NULL;1046 for (offset = 0; offset < len; offset += bytes) {1047 desc = ep93xx_dma_desc_get(edmac);1048 if (!desc) {1049 dev_warn(chan2dev(edmac), "couldn't get descriptor\n");1050 goto fail;1051 }1052 1053 bytes = min_t(size_t, len - offset, DMA_MAX_CHAN_BYTES);1054 1055 desc->src_addr = src + offset;1056 desc->dst_addr = dest + offset;1057 desc->size = bytes;1058 1059 if (!first)1060 first = desc;1061 else1062 list_add_tail(&desc->node, &first->tx_list);1063 }1064 1065 first->txd.cookie = -EBUSY;1066 first->txd.flags = flags;1067 1068 return &first->txd;1069fail:1070 ep93xx_dma_desc_put(edmac, first);1071 return NULL;1072}1073 1074/**1075 * ep93xx_dma_prep_slave_sg - prepare a slave DMA operation1076 * @chan: channel1077 * @sgl: list of buffers to transfer1078 * @sg_len: number of entries in @sgl1079 * @dir: direction of the DMA transfer1080 * @flags: flags for the descriptor1081 * @context: operation context (ignored)1082 *1083 * Returns a valid DMA descriptor or %NULL in case of failure.1084 */1085static struct dma_async_tx_descriptor *1086ep93xx_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,1087 unsigned int sg_len, enum dma_transfer_direction dir,1088 unsigned long flags, void *context)1089{1090 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);1091 struct ep93xx_dma_desc *desc, *first;1092 struct scatterlist *sg;1093 int i;1094 1095 if (!edmac->edma->m2m && dir != ep93xx_dma_chan_direction(chan)) {1096 dev_warn(chan2dev(edmac),1097 "channel was configured with different direction\n");1098 return NULL;1099 }1100 1101 if (test_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags)) {1102 dev_warn(chan2dev(edmac),1103 "channel is already used for cyclic transfers\n");1104 return NULL;1105 }1106 1107 ep93xx_dma_slave_config_write(chan, dir, &edmac->slave_config);1108 1109 first = NULL;1110 for_each_sg(sgl, sg, sg_len, i) {1111 size_t len = sg_dma_len(sg);1112 1113 if (len > DMA_MAX_CHAN_BYTES) {1114 dev_warn(chan2dev(edmac), "too big transfer size %zu\n",1115 len);1116 goto fail;1117 }1118 1119 desc = ep93xx_dma_desc_get(edmac);1120 if (!desc) {1121 dev_warn(chan2dev(edmac), "couldn't get descriptor\n");1122 goto fail;1123 }1124 1125 if (dir == DMA_MEM_TO_DEV) {1126 desc->src_addr = sg_dma_address(sg);1127 desc->dst_addr = edmac->runtime_addr;1128 } else {1129 desc->src_addr = edmac->runtime_addr;1130 desc->dst_addr = sg_dma_address(sg);1131 }1132 desc->size = len;1133 1134 if (!first)1135 first = desc;1136 else1137 list_add_tail(&desc->node, &first->tx_list);1138 }1139 1140 first->txd.cookie = -EBUSY;1141 first->txd.flags = flags;1142 1143 return &first->txd;1144 1145fail:1146 ep93xx_dma_desc_put(edmac, first);1147 return NULL;1148}1149 1150/**1151 * ep93xx_dma_prep_dma_cyclic - prepare a cyclic DMA operation1152 * @chan: channel1153 * @dma_addr: DMA mapped address of the buffer1154 * @buf_len: length of the buffer (in bytes)1155 * @period_len: length of a single period1156 * @dir: direction of the operation1157 * @flags: tx descriptor status flags1158 *1159 * Prepares a descriptor for cyclic DMA operation. This means that once the1160 * descriptor is submitted, we will be submitting in a @period_len sized1161 * buffers and calling callback once the period has been elapsed. Transfer1162 * terminates only when client calls dmaengine_terminate_all() for this1163 * channel.1164 *1165 * Returns a valid DMA descriptor or %NULL in case of failure.1166 */1167static struct dma_async_tx_descriptor *1168ep93xx_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,1169 size_t buf_len, size_t period_len,1170 enum dma_transfer_direction dir, unsigned long flags)1171{1172 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);1173 struct ep93xx_dma_desc *desc, *first;1174 size_t offset = 0;1175 1176 if (!edmac->edma->m2m && dir != ep93xx_dma_chan_direction(chan)) {1177 dev_warn(chan2dev(edmac),1178 "channel was configured with different direction\n");1179 return NULL;1180 }1181 1182 if (test_and_set_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags)) {1183 dev_warn(chan2dev(edmac),1184 "channel is already used for cyclic transfers\n");1185 return NULL;1186 }1187 1188 if (period_len > DMA_MAX_CHAN_BYTES) {1189 dev_warn(chan2dev(edmac), "too big period length %zu\n",1190 period_len);1191 return NULL;1192 }1193 1194 ep93xx_dma_slave_config_write(chan, dir, &edmac->slave_config);1195 1196 /* Split the buffer into period size chunks */1197 first = NULL;1198 for (offset = 0; offset < buf_len; offset += period_len) {1199 desc = ep93xx_dma_desc_get(edmac);1200 if (!desc) {1201 dev_warn(chan2dev(edmac), "couldn't get descriptor\n");1202 goto fail;1203 }1204 1205 if (dir == DMA_MEM_TO_DEV) {1206 desc->src_addr = dma_addr + offset;1207 desc->dst_addr = edmac->runtime_addr;1208 } else {1209 desc->src_addr = edmac->runtime_addr;1210 desc->dst_addr = dma_addr + offset;1211 }1212 1213 desc->size = period_len;1214 1215 if (!first)1216 first = desc;1217 else1218 list_add_tail(&desc->node, &first->tx_list);1219 }1220 1221 first->txd.cookie = -EBUSY;1222 1223 return &first->txd;1224 1225fail:1226 ep93xx_dma_desc_put(edmac, first);1227 return NULL;1228}1229 1230/**1231 * ep93xx_dma_synchronize - Synchronizes the termination of transfers to the1232 * current context.1233 * @chan: channel1234 *1235 * Synchronizes the DMA channel termination to the current context. When this1236 * function returns it is guaranteed that all transfers for previously issued1237 * descriptors have stopped and it is safe to free the memory associated1238 * with them. Furthermore it is guaranteed that all complete callback functions1239 * for a previously submitted descriptor have finished running and it is safe to1240 * free resources accessed from within the complete callbacks.1241 */1242static void ep93xx_dma_synchronize(struct dma_chan *chan)1243{1244 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);1245 1246 if (edmac->edma->hw_synchronize)1247 edmac->edma->hw_synchronize(edmac);1248}1249 1250/**1251 * ep93xx_dma_terminate_all - terminate all transactions1252 * @chan: channel1253 *1254 * Stops all DMA transactions. All descriptors are put back to the1255 * @edmac->free_list and callbacks are _not_ called.1256 */1257static int ep93xx_dma_terminate_all(struct dma_chan *chan)1258{1259 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);1260 struct ep93xx_dma_desc *desc, *_d;1261 unsigned long flags;1262 LIST_HEAD(list);1263 1264 spin_lock_irqsave(&edmac->lock, flags);1265 /* First we disable and flush the DMA channel */1266 edmac->edma->hw_shutdown(edmac);1267 clear_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags);1268 list_splice_init(&edmac->active, &list);1269 list_splice_init(&edmac->queue, &list);1270 /*1271 * We then re-enable the channel. This way we can continue submitting1272 * the descriptors by just calling ->hw_submit() again.1273 */1274 edmac->edma->hw_setup(edmac);1275 spin_unlock_irqrestore(&edmac->lock, flags);1276 1277 list_for_each_entry_safe(desc, _d, &list, node)1278 ep93xx_dma_desc_put(edmac, desc);1279 1280 return 0;1281}1282 1283static int ep93xx_dma_slave_config(struct dma_chan *chan,1284 struct dma_slave_config *config)1285{1286 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);1287 1288 memcpy(&edmac->slave_config, config, sizeof(*config));1289 1290 return 0;1291}1292 1293static int ep93xx_dma_slave_config_write(struct dma_chan *chan,1294 enum dma_transfer_direction dir,1295 struct dma_slave_config *config)1296{1297 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);1298 enum dma_slave_buswidth width;1299 unsigned long flags;1300 u32 addr, ctrl;1301 1302 if (!edmac->edma->m2m)1303 return -EINVAL;1304 1305 switch (dir) {1306 case DMA_DEV_TO_MEM:1307 width = config->src_addr_width;1308 addr = config->src_addr;1309 break;1310 1311 case DMA_MEM_TO_DEV:1312 width = config->dst_addr_width;1313 addr = config->dst_addr;1314 break;1315 1316 default:1317 return -EINVAL;1318 }1319 1320 switch (width) {1321 case DMA_SLAVE_BUSWIDTH_1_BYTE:1322 ctrl = 0;1323 break;1324 case DMA_SLAVE_BUSWIDTH_2_BYTES:1325 ctrl = M2M_CONTROL_PW_16;1326 break;1327 case DMA_SLAVE_BUSWIDTH_4_BYTES:1328 ctrl = M2M_CONTROL_PW_32;1329 break;1330 default:1331 return -EINVAL;1332 }1333 1334 spin_lock_irqsave(&edmac->lock, flags);1335 edmac->runtime_addr = addr;1336 edmac->runtime_ctrl = ctrl;1337 spin_unlock_irqrestore(&edmac->lock, flags);1338 1339 return 0;1340}1341 1342/**1343 * ep93xx_dma_tx_status - check if a transaction is completed1344 * @chan: channel1345 * @cookie: transaction specific cookie1346 * @state: state of the transaction is stored here if given1347 *1348 * This function can be used to query state of a given transaction.1349 */1350static enum dma_status ep93xx_dma_tx_status(struct dma_chan *chan,1351 dma_cookie_t cookie,1352 struct dma_tx_state *state)1353{1354 return dma_cookie_status(chan, cookie, state);1355}1356 1357/**1358 * ep93xx_dma_issue_pending - push pending transactions to the hardware1359 * @chan: channel1360 *1361 * When this function is called, all pending transactions are pushed to the1362 * hardware and executed.1363 */1364static void ep93xx_dma_issue_pending(struct dma_chan *chan)1365{1366 ep93xx_dma_advance_work(to_ep93xx_dma_chan(chan));1367}1368 1369static struct ep93xx_dma_engine *ep93xx_dma_of_probe(struct platform_device *pdev)1370{1371 const struct ep93xx_edma_data *data;1372 struct device *dev = &pdev->dev;1373 struct ep93xx_dma_engine *edma;1374 struct dma_device *dma_dev;1375 char dma_clk_name[5];1376 int i;1377 1378 data = device_get_match_data(dev);1379 if (!data)1380 return ERR_PTR(dev_err_probe(dev, -ENODEV, "No device match found\n"));1381 1382 edma = devm_kzalloc(dev, struct_size(edma, channels, data->num_channels),1383 GFP_KERNEL);1384 if (!edma)1385 return ERR_PTR(-ENOMEM);1386 1387 edma->m2m = data->id;1388 edma->num_channels = data->num_channels;1389 dma_dev = &edma->dma_dev;1390 1391 INIT_LIST_HEAD(&dma_dev->channels);1392 for (i = 0; i < edma->num_channels; i++) {1393 struct ep93xx_dma_chan *edmac = &edma->channels[i];1394 int len;1395 1396 edmac->chan.device = dma_dev;1397 edmac->regs = devm_platform_ioremap_resource(pdev, i);1398 if (IS_ERR(edmac->regs))1399 return ERR_CAST(edmac->regs);1400 1401 edmac->irq = fwnode_irq_get(dev_fwnode(dev), i);1402 if (edmac->irq < 0)1403 return ERR_PTR(edmac->irq);1404 1405 edmac->edma = edma;1406 1407 if (edma->m2m)1408 len = snprintf(dma_clk_name, sizeof(dma_clk_name), "m2m%u", i);1409 else1410 len = snprintf(dma_clk_name, sizeof(dma_clk_name), "m2p%u", i);1411 if (len >= sizeof(dma_clk_name))1412 return ERR_PTR(-ENOBUFS);1413 1414 edmac->clk = devm_clk_get(dev, dma_clk_name);1415 if (IS_ERR(edmac->clk)) {1416 dev_err_probe(dev, PTR_ERR(edmac->clk),1417 "no %s clock found\n", dma_clk_name);1418 return ERR_CAST(edmac->clk);1419 }1420 1421 spin_lock_init(&edmac->lock);1422 INIT_LIST_HEAD(&edmac->active);1423 INIT_LIST_HEAD(&edmac->queue);1424 INIT_LIST_HEAD(&edmac->free_list);1425 tasklet_setup(&edmac->tasklet, ep93xx_dma_tasklet);1426 1427 list_add_tail(&edmac->chan.device_node,1428 &dma_dev->channels);1429 }1430 1431 return edma;1432}1433 1434static bool ep93xx_m2p_dma_filter(struct dma_chan *chan, void *filter_param)1435{1436 struct ep93xx_dma_chan *echan = to_ep93xx_dma_chan(chan);1437 struct ep93xx_dma_chan_cfg *cfg = filter_param;1438 1439 if (cfg->dir != ep93xx_dma_chan_direction(chan))1440 return false;1441 1442 echan->dma_cfg = *cfg;1443 return true;1444}1445 1446static struct dma_chan *ep93xx_m2p_dma_of_xlate(struct of_phandle_args *dma_spec,1447 struct of_dma *ofdma)1448{1449 struct ep93xx_dma_engine *edma = ofdma->of_dma_data;1450 dma_cap_mask_t mask = edma->dma_dev.cap_mask;1451 struct ep93xx_dma_chan_cfg dma_cfg;1452 u8 port = dma_spec->args[0];1453 u8 direction = dma_spec->args[1];1454 1455 if (port > EP93XX_DMA_IRDA)1456 return NULL;1457 1458 if (!is_slave_direction(direction))1459 return NULL;1460 1461 dma_cfg.port = port;1462 dma_cfg.dir = direction;1463 1464 return __dma_request_channel(&mask, ep93xx_m2p_dma_filter, &dma_cfg, ofdma->of_node);1465}1466 1467static bool ep93xx_m2m_dma_filter(struct dma_chan *chan, void *filter_param)1468{1469 struct ep93xx_dma_chan *echan = to_ep93xx_dma_chan(chan);1470 struct ep93xx_dma_chan_cfg *cfg = filter_param;1471 1472 echan->dma_cfg = *cfg;1473 1474 return true;1475}1476 1477static struct dma_chan *ep93xx_m2m_dma_of_xlate(struct of_phandle_args *dma_spec,1478 struct of_dma *ofdma)1479{1480 struct ep93xx_dma_engine *edma = ofdma->of_dma_data;1481 dma_cap_mask_t mask = edma->dma_dev.cap_mask;1482 struct ep93xx_dma_chan_cfg dma_cfg;1483 u8 port = dma_spec->args[0];1484 u8 direction = dma_spec->args[1];1485 1486 if (!is_slave_direction(direction))1487 return NULL;1488 1489 switch (port) {1490 case EP93XX_DMA_SSP:1491 case EP93XX_DMA_IDE:1492 break;1493 default:1494 return NULL;1495 }1496 1497 dma_cfg.port = port;1498 dma_cfg.dir = direction;1499 1500 return __dma_request_channel(&mask, ep93xx_m2m_dma_filter, &dma_cfg, ofdma->of_node);1501}1502 1503static int ep93xx_dma_probe(struct platform_device *pdev)1504{1505 struct ep93xx_dma_engine *edma;1506 struct dma_device *dma_dev;1507 int ret;1508 1509 edma = ep93xx_dma_of_probe(pdev);1510 if (IS_ERR(edma))1511 return PTR_ERR(edma);1512 1513 dma_dev = &edma->dma_dev;1514 1515 dma_cap_zero(dma_dev->cap_mask);1516 dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);1517 dma_cap_set(DMA_CYCLIC, dma_dev->cap_mask);1518 1519 dma_dev->dev = &pdev->dev;1520 dma_dev->device_alloc_chan_resources = ep93xx_dma_alloc_chan_resources;1521 dma_dev->device_free_chan_resources = ep93xx_dma_free_chan_resources;1522 dma_dev->device_prep_slave_sg = ep93xx_dma_prep_slave_sg;1523 dma_dev->device_prep_dma_cyclic = ep93xx_dma_prep_dma_cyclic;1524 dma_dev->device_config = ep93xx_dma_slave_config;1525 dma_dev->device_synchronize = ep93xx_dma_synchronize;1526 dma_dev->device_terminate_all = ep93xx_dma_terminate_all;1527 dma_dev->device_issue_pending = ep93xx_dma_issue_pending;1528 dma_dev->device_tx_status = ep93xx_dma_tx_status;1529 1530 dma_set_max_seg_size(dma_dev->dev, DMA_MAX_CHAN_BYTES);1531 1532 if (edma->m2m) {1533 dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);1534 dma_dev->device_prep_dma_memcpy = ep93xx_dma_prep_dma_memcpy;1535 1536 edma->hw_setup = m2m_hw_setup;1537 edma->hw_shutdown = m2m_hw_shutdown;1538 edma->hw_submit = m2m_hw_submit;1539 edma->hw_interrupt = m2m_hw_interrupt;1540 } else {1541 dma_cap_set(DMA_PRIVATE, dma_dev->cap_mask);1542 1543 edma->hw_synchronize = m2p_hw_synchronize;1544 edma->hw_setup = m2p_hw_setup;1545 edma->hw_shutdown = m2p_hw_shutdown;1546 edma->hw_submit = m2p_hw_submit;1547 edma->hw_interrupt = m2p_hw_interrupt;1548 }1549 1550 ret = dma_async_device_register(dma_dev);1551 if (ret)1552 return ret;1553 1554 if (edma->m2m) {1555 ret = of_dma_controller_register(pdev->dev.of_node, ep93xx_m2m_dma_of_xlate,1556 edma);1557 } else {1558 ret = of_dma_controller_register(pdev->dev.of_node, ep93xx_m2p_dma_of_xlate,1559 edma);1560 }1561 if (ret)1562 goto err_dma_unregister;1563 1564 dev_info(dma_dev->dev, "EP93xx M2%s DMA ready\n", edma->m2m ? "M" : "P");1565 1566 return 0;1567 1568err_dma_unregister:1569 dma_async_device_unregister(dma_dev);1570 1571 return ret;1572}1573 1574static const struct ep93xx_edma_data edma_m2p = {1575 .id = M2P_DMA,1576 .num_channels = 10,1577};1578 1579static const struct ep93xx_edma_data edma_m2m = {1580 .id = M2M_DMA,1581 .num_channels = 2,1582};1583 1584static const struct of_device_id ep93xx_dma_of_ids[] = {1585 { .compatible = "cirrus,ep9301-dma-m2p", .data = &edma_m2p },1586 { .compatible = "cirrus,ep9301-dma-m2m", .data = &edma_m2m },1587 { /* sentinel */ }1588};1589MODULE_DEVICE_TABLE(of, ep93xx_dma_of_ids);1590 1591static const struct platform_device_id ep93xx_dma_driver_ids[] = {1592 { "ep93xx-dma-m2p", 0 },1593 { "ep93xx-dma-m2m", 1 },1594 { },1595};1596 1597static struct platform_driver ep93xx_dma_driver = {1598 .driver = {1599 .name = "ep93xx-dma",1600 .of_match_table = ep93xx_dma_of_ids,1601 },1602 .id_table = ep93xx_dma_driver_ids,1603 .probe = ep93xx_dma_probe,1604};1605 1606module_platform_driver(ep93xx_dma_driver);1607 1608MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");1609MODULE_DESCRIPTION("EP93xx DMA driver");1610