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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Driver for the Intel integrated DMA 64-bit4 *5 * Copyright (C) 2015 Intel Corporation6 */7 8#ifndef __DMA_IDMA64_H__9#define __DMA_IDMA64_H__10 11#include <linux/device.h>12#include <linux/io.h>13#include <linux/spinlock.h>14#include <linux/types.h>15 16#include <linux/io-64-nonatomic-lo-hi.h>17 18#include "virt-dma.h"19 20/* Channel registers */21 22#define IDMA64_CH_SAR 0x00 /* Source Address Register */23#define IDMA64_CH_DAR 0x08 /* Destination Address Register */24#define IDMA64_CH_LLP 0x10 /* Linked List Pointer */25#define IDMA64_CH_CTL_LO 0x18 /* Control Register Low */26#define IDMA64_CH_CTL_HI 0x1c /* Control Register High */27#define IDMA64_CH_SSTAT 0x2028#define IDMA64_CH_DSTAT 0x2829#define IDMA64_CH_SSTATAR 0x3030#define IDMA64_CH_DSTATAR 0x3831#define IDMA64_CH_CFG_LO 0x40 /* Configuration Register Low */32#define IDMA64_CH_CFG_HI 0x44 /* Configuration Register High */33#define IDMA64_CH_SGR 0x4834#define IDMA64_CH_DSR 0x5035 36#define IDMA64_CH_LENGTH 0x5837 38/* Bitfields in CTL_LO */39#define IDMA64C_CTLL_INT_EN (1 << 0) /* irqs enabled? */40#define IDMA64C_CTLL_DST_WIDTH(x) ((x) << 1) /* bytes per element */41#define IDMA64C_CTLL_SRC_WIDTH(x) ((x) << 4)42#define IDMA64C_CTLL_DST_INC (0 << 8) /* DAR update/not */43#define IDMA64C_CTLL_DST_FIX (1 << 8)44#define IDMA64C_CTLL_SRC_INC (0 << 10) /* SAR update/not */45#define IDMA64C_CTLL_SRC_FIX (1 << 10)46#define IDMA64C_CTLL_DST_MSIZE(x) ((x) << 11) /* burst, #elements */47#define IDMA64C_CTLL_SRC_MSIZE(x) ((x) << 14)48#define IDMA64C_CTLL_FC_M2P (1 << 20) /* mem-to-periph */49#define IDMA64C_CTLL_FC_P2M (2 << 20) /* periph-to-mem */50#define IDMA64C_CTLL_LLP_D_EN (1 << 27) /* dest block chain */51#define IDMA64C_CTLL_LLP_S_EN (1 << 28) /* src block chain */52 53/* Bitfields in CTL_HI */54#define IDMA64C_CTLH_BLOCK_TS_MASK ((1 << 17) - 1)55#define IDMA64C_CTLH_BLOCK_TS(x) ((x) & IDMA64C_CTLH_BLOCK_TS_MASK)56#define IDMA64C_CTLH_DONE (1 << 17)57 58/* Bitfields in CFG_LO */59#define IDMA64C_CFGL_DST_BURST_ALIGN (1 << 0) /* dst burst align */60#define IDMA64C_CFGL_SRC_BURST_ALIGN (1 << 1) /* src burst align */61#define IDMA64C_CFGL_CH_SUSP (1 << 8)62#define IDMA64C_CFGL_FIFO_EMPTY (1 << 9)63#define IDMA64C_CFGL_CH_DRAIN (1 << 10) /* drain FIFO */64#define IDMA64C_CFGL_DST_OPT_BL (1 << 20) /* optimize dst burst length */65#define IDMA64C_CFGL_SRC_OPT_BL (1 << 21) /* optimize src burst length */66 67/* Bitfields in CFG_HI */68#define IDMA64C_CFGH_SRC_PER(x) ((x) << 0) /* src peripheral */69#define IDMA64C_CFGH_DST_PER(x) ((x) << 4) /* dst peripheral */70#define IDMA64C_CFGH_RD_ISSUE_THD(x) ((x) << 8)71#define IDMA64C_CFGH_WR_ISSUE_THD(x) ((x) << 18)72 73/* Interrupt registers */74 75#define IDMA64_INT_XFER 0x0076#define IDMA64_INT_BLOCK 0x0877#define IDMA64_INT_SRC_TRAN 0x1078#define IDMA64_INT_DST_TRAN 0x1879#define IDMA64_INT_ERROR 0x2080 81#define IDMA64_RAW(x) (0x2c0 + IDMA64_INT_##x) /* r */82#define IDMA64_STATUS(x) (0x2e8 + IDMA64_INT_##x) /* r (raw & mask) */83#define IDMA64_MASK(x) (0x310 + IDMA64_INT_##x) /* rw (set = irq enabled) */84#define IDMA64_CLEAR(x) (0x338 + IDMA64_INT_##x) /* w (ack, affects "raw") */85 86/* Common registers */87 88#define IDMA64_STATUS_INT 0x360 /* r */89#define IDMA64_CFG 0x39890#define IDMA64_CH_EN 0x3a091 92/* Bitfields in CFG */93#define IDMA64_CFG_DMA_EN (1 << 0)94 95/* Hardware descriptor for Linked LIst transfers */96struct idma64_lli {97 u64 sar;98 u64 dar;99 u64 llp;100 u32 ctllo;101 u32 ctlhi;102 u32 sstat;103 u32 dstat;104};105 106struct idma64_hw_desc {107 struct idma64_lli *lli;108 dma_addr_t llp;109 dma_addr_t phys;110 unsigned int len;111};112 113struct idma64_desc {114 struct virt_dma_desc vdesc;115 enum dma_transfer_direction direction;116 struct idma64_hw_desc *hw;117 unsigned int ndesc;118 size_t length;119 enum dma_status status;120};121 122static inline struct idma64_desc *to_idma64_desc(struct virt_dma_desc *vdesc)123{124 return container_of(vdesc, struct idma64_desc, vdesc);125}126 127struct idma64_chan {128 struct virt_dma_chan vchan;129 130 void __iomem *regs;131 132 /* hardware configuration */133 enum dma_transfer_direction direction;134 unsigned int mask;135 struct dma_slave_config config;136 137 void *pool;138 struct idma64_desc *desc;139};140 141static inline struct idma64_chan *to_idma64_chan(struct dma_chan *chan)142{143 return container_of(chan, struct idma64_chan, vchan.chan);144}145 146#define channel_set_bit(idma64, reg, mask) \147 dma_writel(idma64, reg, ((mask) << 8) | (mask))148#define channel_clear_bit(idma64, reg, mask) \149 dma_writel(idma64, reg, ((mask) << 8) | 0)150 151static inline u32 idma64c_readl(struct idma64_chan *idma64c, int offset)152{153 return readl(idma64c->regs + offset);154}155 156static inline void idma64c_writel(struct idma64_chan *idma64c, int offset,157 u32 value)158{159 writel(value, idma64c->regs + offset);160}161 162#define channel_readl(idma64c, reg) \163 idma64c_readl(idma64c, IDMA64_CH_##reg)164#define channel_writel(idma64c, reg, value) \165 idma64c_writel(idma64c, IDMA64_CH_##reg, (value))166 167static inline u64 idma64c_readq(struct idma64_chan *idma64c, int offset)168{169 return lo_hi_readq(idma64c->regs + offset);170}171 172static inline void idma64c_writeq(struct idma64_chan *idma64c, int offset,173 u64 value)174{175 lo_hi_writeq(value, idma64c->regs + offset);176}177 178#define channel_readq(idma64c, reg) \179 idma64c_readq(idma64c, IDMA64_CH_##reg)180#define channel_writeq(idma64c, reg, value) \181 idma64c_writeq(idma64c, IDMA64_CH_##reg, (value))182 183struct idma64 {184 struct dma_device dma;185 186 void __iomem *regs;187 188 /* channels */189 unsigned short all_chan_mask;190 struct idma64_chan *chan;191};192 193static inline struct idma64 *to_idma64(struct dma_device *ddev)194{195 return container_of(ddev, struct idma64, dma);196}197 198static inline u32 idma64_readl(struct idma64 *idma64, int offset)199{200 return readl(idma64->regs + offset);201}202 203static inline void idma64_writel(struct idma64 *idma64, int offset, u32 value)204{205 writel(value, idma64->regs + offset);206}207 208#define dma_readl(idma64, reg) \209 idma64_readl(idma64, IDMA64_##reg)210#define dma_writel(idma64, reg, value) \211 idma64_writel(idma64, IDMA64_##reg, (value))212 213/**214 * struct idma64_chip - representation of iDMA 64-bit controller hardware215 * @dev: struct device of the DMA controller216 * @sysdev: struct device of the physical device that does DMA217 * @irq: irq line218 * @regs: memory mapped I/O space219 * @idma64: struct idma64 that is filed by idma64_probe()220 */221struct idma64_chip {222 struct device *dev;223 struct device *sysdev;224 int irq;225 void __iomem *regs;226 struct idma64 *idma64;227};228 229#endif /* __DMA_IDMA64_H__ */230