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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.4 */5#ifndef _IOAT_REGISTERS_H_6#define _IOAT_REGISTERS_H_7 8#define IOAT_PCI_DMACTRL_OFFSET 0x489#define IOAT_PCI_DMACTRL_DMA_EN 0x0000000110#define IOAT_PCI_DMACTRL_MSI_EN 0x0000000211 12#define IOAT_PCI_DEVICE_ID_OFFSET 0x0213#define IOAT_PCI_DMAUNCERRSTS_OFFSET 0x14814#define IOAT_PCI_CHANERR_INT_OFFSET 0x18015#define IOAT_PCI_CHANERRMASK_INT_OFFSET 0x18416 17/* MMIO Device Registers */18#define IOAT_CHANCNT_OFFSET 0x00 /* 8-bit */19 20#define IOAT_XFERCAP_OFFSET 0x01 /* 8-bit */21#define IOAT_XFERCAP_4KB 1222#define IOAT_XFERCAP_8KB 1323#define IOAT_XFERCAP_16KB 1424#define IOAT_XFERCAP_32KB 1525#define IOAT_XFERCAP_32GB 026 27#define IOAT_GENCTRL_OFFSET 0x02 /* 8-bit */28#define IOAT_GENCTRL_DEBUG_EN 0x0129 30#define IOAT_INTRCTRL_OFFSET 0x03 /* 8-bit */31#define IOAT_INTRCTRL_MASTER_INT_EN 0x01 /* Master Interrupt Enable */32#define IOAT_INTRCTRL_INT_STATUS 0x02 /* ATTNSTATUS -or- Channel Int */33#define IOAT_INTRCTRL_INT 0x04 /* INT_STATUS -and- MASTER_INT_EN */34#define IOAT_INTRCTRL_MSIX_VECTOR_CONTROL 0x08 /* Enable all MSI-X vectors */35 36#define IOAT_ATTNSTATUS_OFFSET 0x04 /* Each bit is a channel */37 38#define IOAT_VER_OFFSET 0x08 /* 8-bit */39#define IOAT_VER_MAJOR_MASK 0xF040#define IOAT_VER_MINOR_MASK 0x0F41#define GET_IOAT_VER_MAJOR(x) (((x) & IOAT_VER_MAJOR_MASK) >> 4)42#define GET_IOAT_VER_MINOR(x) ((x) & IOAT_VER_MINOR_MASK)43 44#define IOAT_PERPORTOFFSET_OFFSET 0x0A /* 16-bit */45 46#define IOAT_INTRDELAY_OFFSET 0x0C /* 16-bit */47#define IOAT_INTRDELAY_MASK 0x3FFF /* Interrupt Delay Time */48#define IOAT_INTRDELAY_COALESE_SUPPORT 0x8000 /* Interrupt Coalescing Supported */49 50#define IOAT_DEVICE_STATUS_OFFSET 0x0E /* 16-bit */51#define IOAT_DEVICE_STATUS_DEGRADED_MODE 0x000152#define IOAT_DEVICE_MMIO_RESTRICTED 0x000253#define IOAT_DEVICE_MEMORY_BYPASS 0x000454#define IOAT_DEVICE_ADDRESS_REMAPPING 0x000855 56#define IOAT_DMA_CAP_OFFSET 0x10 /* 32-bit */57#define IOAT_CAP_PAGE_BREAK 0x0000000158#define IOAT_CAP_CRC 0x0000000259#define IOAT_CAP_SKIP_MARKER 0x0000000460#define IOAT_CAP_DCA 0x0000001061#define IOAT_CAP_CRC_MOVE 0x0000002062#define IOAT_CAP_FILL_BLOCK 0x0000004063#define IOAT_CAP_APIC 0x0000008064#define IOAT_CAP_XOR 0x0000010065#define IOAT_CAP_PQ 0x0000020066#define IOAT_CAP_DWBES 0x0000200067#define IOAT_CAP_RAID16SS 0x0002000068#define IOAT_CAP_DPS 0x0080000069 70#define IOAT_PREFETCH_LIMIT_OFFSET 0x4C /* CHWPREFLMT */71 72#define IOAT_CHANNEL_MMIO_SIZE 0x80 /* Each Channel MMIO space is this size */73 74/* DMA Channel Registers */75#define IOAT_CHANCTRL_OFFSET 0x00 /* 16-bit Channel Control Register */76#define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF00077#define IOAT3_CHANCTRL_COMPL_DCA_EN 0x020078#define IOAT_CHANCTRL_CHANNEL_IN_USE 0x010079#define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x002080#define IOAT_CHANCTRL_ERR_INT_EN 0x001081#define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x000882#define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x000483#define IOAT_CHANCTRL_INT_REARM 0x000184#define IOAT_CHANCTRL_RUN (IOAT_CHANCTRL_INT_REARM |\85 IOAT_CHANCTRL_ERR_INT_EN |\86 IOAT_CHANCTRL_ERR_COMPLETION_EN |\87 IOAT_CHANCTRL_ANY_ERR_ABORT_EN)88 89#define IOAT_DMA_COMP_OFFSET 0x02 /* 16-bit DMA channel compatibility */90#define IOAT_DMA_COMP_V1 0x0001 /* Compatibility with DMA version 1 */91#define IOAT_DMA_COMP_V2 0x0002 /* Compatibility with DMA version 2 */92 93#define IOAT_CHANSTS_OFFSET 0x08 /* 64-bit Channel Status Register */94#define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR (~0x3fULL)95#define IOAT_CHANSTS_SOFT_ERR 0x10ULL96#define IOAT_CHANSTS_UNAFFILIATED_ERR 0x8ULL97#define IOAT_CHANSTS_STATUS 0x7ULL98#define IOAT_CHANSTS_ACTIVE 0x099#define IOAT_CHANSTS_DONE 0x1100#define IOAT_CHANSTS_SUSPENDED 0x2101#define IOAT_CHANSTS_HALTED 0x3102 103 104 105#define IOAT_CHAN_DMACOUNT_OFFSET 0x06 /* 16-bit DMA Count register */106 107#define IOAT_DCACTRL_OFFSET 0x30 /* 32 bit Direct Cache Access Control Register */108#define IOAT_DCACTRL_CMPL_WRITE_ENABLE 0x10000109#define IOAT_DCACTRL_TARGET_CPU_MASK 0xFFFF /* APIC ID */110 111/* CB DCA Memory Space Registers */112#define IOAT_DCAOFFSET_OFFSET 0x14113/* CB_BAR + IOAT_DCAOFFSET value */114#define IOAT_DCA_VER_OFFSET 0x00115#define IOAT_DCA_VER_MAJOR_MASK 0xF0116#define IOAT_DCA_VER_MINOR_MASK 0x0F117 118#define IOAT_DCA_COMP_OFFSET 0x02119#define IOAT_DCA_COMP_V1 0x1120 121#define IOAT_FSB_CAPABILITY_OFFSET 0x04122#define IOAT_FSB_CAPABILITY_PREFETCH 0x1123 124#define IOAT_PCI_CAPABILITY_OFFSET 0x06125#define IOAT_PCI_CAPABILITY_MEMWR 0x1126 127#define IOAT_FSB_CAP_ENABLE_OFFSET 0x08128#define IOAT_FSB_CAP_ENABLE_PREFETCH 0x1129 130#define IOAT_PCI_CAP_ENABLE_OFFSET 0x0A131#define IOAT_PCI_CAP_ENABLE_MEMWR 0x1132 133#define IOAT_APICID_TAG_MAP_OFFSET 0x0C134#define IOAT_APICID_TAG_MAP_TAG0 0x0000000F135#define IOAT_APICID_TAG_MAP_TAG0_SHIFT 0136#define IOAT_APICID_TAG_MAP_TAG1 0x000000F0137#define IOAT_APICID_TAG_MAP_TAG1_SHIFT 4138#define IOAT_APICID_TAG_MAP_TAG2 0x00000F00139#define IOAT_APICID_TAG_MAP_TAG2_SHIFT 8140#define IOAT_APICID_TAG_MAP_TAG3 0x0000F000141#define IOAT_APICID_TAG_MAP_TAG3_SHIFT 12142#define IOAT_APICID_TAG_MAP_TAG4 0x000F0000143#define IOAT_APICID_TAG_MAP_TAG4_SHIFT 16144#define IOAT_APICID_TAG_CB2_VALID 0x8080808080145 146#define IOAT_DCA_GREQID_OFFSET 0x10147#define IOAT_DCA_GREQID_SIZE 0x04148#define IOAT_DCA_GREQID_MASK 0xFFFF149#define IOAT_DCA_GREQID_IGNOREFUN 0x10000000150#define IOAT_DCA_GREQID_VALID 0x20000000151#define IOAT_DCA_GREQID_LASTID 0x80000000152 153#define IOAT3_CSI_CAPABILITY_OFFSET 0x08154#define IOAT3_CSI_CAPABILITY_PREFETCH 0x1155 156#define IOAT3_PCI_CAPABILITY_OFFSET 0x0A157#define IOAT3_PCI_CAPABILITY_MEMWR 0x1158 159#define IOAT3_CSI_CONTROL_OFFSET 0x0C160#define IOAT3_CSI_CONTROL_PREFETCH 0x1161 162#define IOAT3_PCI_CONTROL_OFFSET 0x0E163#define IOAT3_PCI_CONTROL_MEMWR 0x1164 165#define IOAT3_APICID_TAG_MAP_OFFSET 0x10166#define IOAT3_APICID_TAG_MAP_OFFSET_LOW 0x10167#define IOAT3_APICID_TAG_MAP_OFFSET_HIGH 0x14168 169#define IOAT3_DCA_GREQID_OFFSET 0x02170 171#define IOAT1_CHAINADDR_OFFSET 0x0C /* 64-bit Descriptor Chain Address Register */172#define IOAT2_CHAINADDR_OFFSET 0x10 /* 64-bit Descriptor Chain Address Register */173#define IOAT_CHAINADDR_OFFSET(ver) ((ver) < IOAT_VER_2_0 \174 ? IOAT1_CHAINADDR_OFFSET : IOAT2_CHAINADDR_OFFSET)175#define IOAT1_CHAINADDR_OFFSET_LOW 0x0C176#define IOAT2_CHAINADDR_OFFSET_LOW 0x10177#define IOAT_CHAINADDR_OFFSET_LOW(ver) ((ver) < IOAT_VER_2_0 \178 ? IOAT1_CHAINADDR_OFFSET_LOW : IOAT2_CHAINADDR_OFFSET_LOW)179#define IOAT1_CHAINADDR_OFFSET_HIGH 0x10180#define IOAT2_CHAINADDR_OFFSET_HIGH 0x14181#define IOAT_CHAINADDR_OFFSET_HIGH(ver) ((ver) < IOAT_VER_2_0 \182 ? IOAT1_CHAINADDR_OFFSET_HIGH : IOAT2_CHAINADDR_OFFSET_HIGH)183 184#define IOAT1_CHANCMD_OFFSET 0x14 /* 8-bit DMA Channel Command Register */185#define IOAT2_CHANCMD_OFFSET 0x04 /* 8-bit DMA Channel Command Register */186#define IOAT_CHANCMD_OFFSET(ver) ((ver) < IOAT_VER_2_0 \187 ? IOAT1_CHANCMD_OFFSET : IOAT2_CHANCMD_OFFSET)188#define IOAT_CHANCMD_RESET 0x20189#define IOAT_CHANCMD_RESUME 0x10190#define IOAT_CHANCMD_ABORT 0x08191#define IOAT_CHANCMD_SUSPEND 0x04192#define IOAT_CHANCMD_APPEND 0x02193#define IOAT_CHANCMD_START 0x01194 195#define IOAT_CHANCMP_OFFSET 0x18 /* 64-bit Channel Completion Address Register */196#define IOAT_CHANCMP_OFFSET_LOW 0x18197#define IOAT_CHANCMP_OFFSET_HIGH 0x1C198 199#define IOAT_CDAR_OFFSET 0x20 /* 64-bit Current Descriptor Address Register */200#define IOAT_CDAR_OFFSET_LOW 0x20201#define IOAT_CDAR_OFFSET_HIGH 0x24202 203#define IOAT_CHANERR_OFFSET 0x28 /* 32-bit Channel Error Register */204#define IOAT_CHANERR_SRC_ADDR_ERR 0x0001205#define IOAT_CHANERR_DEST_ADDR_ERR 0x0002206#define IOAT_CHANERR_NEXT_ADDR_ERR 0x0004207#define IOAT_CHANERR_NEXT_DESC_ALIGN_ERR 0x0008208#define IOAT_CHANERR_CHAIN_ADDR_VALUE_ERR 0x0010209#define IOAT_CHANERR_CHANCMD_ERR 0x0020210#define IOAT_CHANERR_CHIPSET_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0040211#define IOAT_CHANERR_DMA_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0080212#define IOAT_CHANERR_READ_DATA_ERR 0x0100213#define IOAT_CHANERR_WRITE_DATA_ERR 0x0200214#define IOAT_CHANERR_CONTROL_ERR 0x0400215#define IOAT_CHANERR_LENGTH_ERR 0x0800216#define IOAT_CHANERR_COMPLETION_ADDR_ERR 0x1000217#define IOAT_CHANERR_INT_CONFIGURATION_ERR 0x2000218#define IOAT_CHANERR_SOFT_ERR 0x4000219#define IOAT_CHANERR_UNAFFILIATED_ERR 0x8000220#define IOAT_CHANERR_XOR_P_OR_CRC_ERR 0x10000221#define IOAT_CHANERR_XOR_Q_ERR 0x20000222#define IOAT_CHANERR_DESCRIPTOR_COUNT_ERR 0x40000223 224#define IOAT_CHANERR_HANDLE_MASK (IOAT_CHANERR_XOR_P_OR_CRC_ERR | IOAT_CHANERR_XOR_Q_ERR)225#define IOAT_CHANERR_RECOVER_MASK (IOAT_CHANERR_READ_DATA_ERR | \226 IOAT_CHANERR_WRITE_DATA_ERR)227 228#define IOAT_CHANERR_MASK_OFFSET 0x2C /* 32-bit Channel Error Register */229 230#define IOAT_CHAN_DRSCTL_OFFSET 0xB6231#define IOAT_CHAN_DRSZ_4KB 0x0000232#define IOAT_CHAN_DRSZ_8KB 0x0001233#define IOAT_CHAN_DRSZ_2MB 0x0009234#define IOAT_CHAN_DRS_EN 0x0100235#define IOAT_CHAN_DRS_AUTOWRAP 0x0200236 237#define IOAT_CHAN_LTR_SWSEL_OFFSET 0xBC238#define IOAT_CHAN_LTR_SWSEL_ACTIVE 0x0239#define IOAT_CHAN_LTR_SWSEL_IDLE 0x1240 241#define IOAT_CHAN_LTR_ACTIVE_OFFSET 0xC0242#define IOAT_CHAN_LTR_ACTIVE_SNVAL 0x0000 /* 0 us */243#define IOAT_CHAN_LTR_ACTIVE_SNLATSCALE 0x0800 /* 1us scale */244#define IOAT_CHAN_LTR_ACTIVE_SNREQMNT 0x8000 /* snoop req enable */245 246#define IOAT_CHAN_LTR_IDLE_OFFSET 0xC4247#define IOAT_CHAN_LTR_IDLE_SNVAL 0x0258 /* 600 us */248#define IOAT_CHAN_LTR_IDLE_SNLATSCALE 0x0800 /* 1us scale */249#define IOAT_CHAN_LTR_IDLE_SNREQMNT 0x8000 /* snoop req enable */250 251#endif /* _IOAT_REGISTERS_H_ */252