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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * 2006-2009 (C) DENX Software Engineering.4 *5 * Author: Yuri Tikhonov <yur@emcraft.com>6 */7 8#ifndef _PPC440SPE_ADMA_H9#define _PPC440SPE_ADMA_H10 11#include <linux/types.h>12#include "dma.h"13#include "xor.h"14 15#define to_ppc440spe_adma_chan(chan) \16 container_of(chan, struct ppc440spe_adma_chan, common)17#define to_ppc440spe_adma_device(dev) \18 container_of(dev, struct ppc440spe_adma_device, common)19#define tx_to_ppc440spe_adma_slot(tx) \20 container_of(tx, struct ppc440spe_adma_desc_slot, async_tx)21 22/* Default polynomial (for 440SP is only available) */23#define PPC440SPE_DEFAULT_POLY 0x4d24 25#define PPC440SPE_ADMA_ENGINES_NUM (XOR_ENGINES_NUM + DMA_ENGINES_NUM)26 27#define PPC440SPE_ADMA_WATCHDOG_MSEC 328#define PPC440SPE_ADMA_THRESHOLD 129 30#define PPC440SPE_DMA0_ID 031#define PPC440SPE_DMA1_ID 132#define PPC440SPE_XOR_ID 233 34#define PPC440SPE_ADMA_DMA_MAX_BYTE_COUNT 0xFFFFFFUL35/* this is the XOR_CBBCR width */36#define PPC440SPE_ADMA_XOR_MAX_BYTE_COUNT (1 << 31)37#define PPC440SPE_ADMA_ZERO_SUM_MAX_BYTE_COUNT PPC440SPE_ADMA_XOR_MAX_BYTE_COUNT38 39#define PPC440SPE_RXOR_RUN 040 41#define MQ0_CF2H_RXOR_BS_MASK 0x1FF42 43#undef ADMA_LL_DEBUG44 45/**46 * struct ppc440spe_adma_device - internal representation of an ADMA device47 * @dev: device48 * @dma_reg: base for DMAx register access49 * @xor_reg: base for XOR register access50 * @i2o_reg: base for I2O register access51 * @id: HW ADMA Device selector52 * @dma_desc_pool_virt: base of DMA descriptor region (CPU address)53 * @dma_desc_pool: base of DMA descriptor region (DMA address)54 * @pool_size: size of the pool55 * @irq: DMAx or XOR irq number56 * @err_irq: DMAx error irq number57 * @common: embedded struct dma_device58 */59struct ppc440spe_adma_device {60 struct device *dev;61 struct dma_regs __iomem *dma_reg;62 struct xor_regs __iomem *xor_reg;63 struct i2o_regs __iomem *i2o_reg;64 int id;65 void *dma_desc_pool_virt;66 dma_addr_t dma_desc_pool;67 size_t pool_size;68 int irq;69 int err_irq;70 struct dma_device common;71};72 73/**74 * struct ppc440spe_adma_chan - internal representation of an ADMA channel75 * @lock: serializes enqueue/dequeue operations to the slot pool76 * @device: parent device77 * @chain: device chain view of the descriptors78 * @common: common dmaengine channel object members79 * @all_slots: complete domain of slots usable by the channel80 * @pending: allows batching of hardware operations81 * @slots_allocated: records the actual size of the descriptor slot pool82 * @hw_chain_inited: h/w descriptor chain initialization flag83 * @irq_tasklet: bottom half where ppc440spe_adma_slot_cleanup runs84 * @needs_unmap: if buffers should not be unmapped upon final processing85 * @pdest_page: P destination page for async validate operation86 * @qdest_page: Q destination page for async validate operation87 * @pdest: P dma addr for async validate operation88 * @qdest: Q dma addr for async validate operation89 */90struct ppc440spe_adma_chan {91 spinlock_t lock;92 struct ppc440spe_adma_device *device;93 struct list_head chain;94 struct dma_chan common;95 struct list_head all_slots;96 struct ppc440spe_adma_desc_slot *last_used;97 int pending;98 int slots_allocated;99 int hw_chain_inited;100 struct tasklet_struct irq_tasklet;101 u8 needs_unmap;102 struct page *pdest_page;103 struct page *qdest_page;104 dma_addr_t pdest;105 dma_addr_t qdest;106};107 108struct ppc440spe_rxor {109 u32 addrl;110 u32 addrh;111 int len;112 int xor_count;113 int addr_count;114 int desc_count;115 int state;116};117 118/**119 * struct ppc440spe_adma_desc_slot - PPC440SPE-ADMA software descriptor120 * @phys: hardware address of the hardware descriptor chain121 * @group_head: first operation in a transaction122 * @hw_next: pointer to the next descriptor in chain123 * @async_tx: support for the async_tx api124 * @slot_node: node on the iop_adma_chan.all_slots list125 * @chain_node: node on the op_adma_chan.chain list126 * @group_list: list of slots that make up a multi-descriptor transaction127 * for example transfer lengths larger than the supported hw max128 * @unmap_len: transaction bytecount129 * @hw_desc: virtual address of the hardware descriptor chain130 * @stride: currently chained or not131 * @idx: pool index132 * @slot_cnt: total slots used in an transaction (group of operations)133 * @src_cnt: number of sources set in this descriptor134 * @dst_cnt: number of destinations set in the descriptor135 * @slots_per_op: number of slots per operation136 * @descs_per_op: number of slot per P/Q operation see comment137 * for ppc440spe_prep_dma_pqxor function138 * @flags: desc state/type139 * @reverse_flags: 1 if a corresponding rxor address uses reversed address order140 * @xor_check_result: result of zero sum141 * @crc32_result: result crc calculation142 */143struct ppc440spe_adma_desc_slot {144 dma_addr_t phys;145 struct ppc440spe_adma_desc_slot *group_head;146 struct ppc440spe_adma_desc_slot *hw_next;147 struct dma_async_tx_descriptor async_tx;148 struct list_head slot_node;149 struct list_head chain_node; /* node in channel ops list */150 struct list_head group_list; /* list */151 unsigned int unmap_len;152 void *hw_desc;153 u16 stride;154 u16 idx;155 u16 slot_cnt;156 u8 src_cnt;157 u8 dst_cnt;158 u8 slots_per_op;159 u8 descs_per_op;160 unsigned long flags;161 unsigned long reverse_flags[8];162 163#define PPC440SPE_DESC_INT 0 /* generate interrupt on complete */164#define PPC440SPE_ZERO_P 1 /* clear P destionaion */165#define PPC440SPE_ZERO_Q 2 /* clear Q destination */166#define PPC440SPE_COHERENT 3 /* src/dst are coherent */167 168#define PPC440SPE_DESC_WXOR 4 /* WXORs are in chain */169#define PPC440SPE_DESC_RXOR 5 /* RXOR is in chain */170 171#define PPC440SPE_DESC_RXOR123 8 /* CDB for RXOR123 operation */172#define PPC440SPE_DESC_RXOR124 9 /* CDB for RXOR124 operation */173#define PPC440SPE_DESC_RXOR125 10 /* CDB for RXOR125 operation */174#define PPC440SPE_DESC_RXOR12 11 /* CDB for RXOR12 operation */175#define PPC440SPE_DESC_RXOR_REV 12 /* CDB has srcs in reversed order */176 177#define PPC440SPE_DESC_PCHECK 13178#define PPC440SPE_DESC_QCHECK 14179 180#define PPC440SPE_DESC_RXOR_MSK 0x3181 182 struct ppc440spe_rxor rxor_cursor;183 184 union {185 u32 *xor_check_result;186 u32 *crc32_result;187 };188};189 190#endif /* _PPC440SPE_ADMA_H */191