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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright 2015 Robert Jarzmik <robert.jarzmik@free.fr>4 */5 6#include <linux/err.h>7#include <linux/module.h>8#include <linux/init.h>9#include <linux/types.h>10#include <linux/interrupt.h>11#include <linux/dma-mapping.h>12#include <linux/slab.h>13#include <linux/dmaengine.h>14#include <linux/platform_device.h>15#include <linux/device.h>16#include <linux/platform_data/mmp_dma.h>17#include <linux/dmapool.h>18#include <linux/of.h>19#include <linux/of_dma.h>20#include <linux/wait.h>21#include <linux/dma/pxa-dma.h>22 23#include "dmaengine.h"24#include "virt-dma.h"25 26#define DCSR(n) (0x0000 + ((n) << 2))27#define DALGN(n) 0x00a028#define DINT 0x00f029#define DDADR(n) (0x0200 + ((n) << 4))30#define DSADR(n) (0x0204 + ((n) << 4))31#define DTADR(n) (0x0208 + ((n) << 4))32#define DCMD(n) (0x020c + ((n) << 4))33 34#define PXA_DCSR_RUN BIT(31) /* Run Bit (read / write) */35#define PXA_DCSR_NODESC BIT(30) /* No-Descriptor Fetch (read / write) */36#define PXA_DCSR_STOPIRQEN BIT(29) /* Stop Interrupt Enable (R/W) */37#define PXA_DCSR_REQPEND BIT(8) /* Request Pending (read-only) */38#define PXA_DCSR_STOPSTATE BIT(3) /* Stop State (read-only) */39#define PXA_DCSR_ENDINTR BIT(2) /* End Interrupt (read / write) */40#define PXA_DCSR_STARTINTR BIT(1) /* Start Interrupt (read / write) */41#define PXA_DCSR_BUSERR BIT(0) /* Bus Error Interrupt (read / write) */42 43#define PXA_DCSR_EORIRQEN BIT(28) /* End of Receive IRQ Enable (R/W) */44#define PXA_DCSR_EORJMPEN BIT(27) /* Jump to next descriptor on EOR */45#define PXA_DCSR_EORSTOPEN BIT(26) /* STOP on an EOR */46#define PXA_DCSR_SETCMPST BIT(25) /* Set Descriptor Compare Status */47#define PXA_DCSR_CLRCMPST BIT(24) /* Clear Descriptor Compare Status */48#define PXA_DCSR_CMPST BIT(10) /* The Descriptor Compare Status */49#define PXA_DCSR_EORINTR BIT(9) /* The end of Receive */50 51#define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */52#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */53 54#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */55#define DDADR_STOP BIT(0) /* Stop (read / write) */56 57#define PXA_DCMD_INCSRCADDR BIT(31) /* Source Address Increment Setting. */58#define PXA_DCMD_INCTRGADDR BIT(30) /* Target Address Increment Setting. */59#define PXA_DCMD_FLOWSRC BIT(29) /* Flow Control by the source. */60#define PXA_DCMD_FLOWTRG BIT(28) /* Flow Control by the target. */61#define PXA_DCMD_STARTIRQEN BIT(22) /* Start Interrupt Enable */62#define PXA_DCMD_ENDIRQEN BIT(21) /* End Interrupt Enable */63#define PXA_DCMD_ENDIAN BIT(18) /* Device Endian-ness. */64#define PXA_DCMD_BURST8 (1 << 16) /* 8 byte burst */65#define PXA_DCMD_BURST16 (2 << 16) /* 16 byte burst */66#define PXA_DCMD_BURST32 (3 << 16) /* 32 byte burst */67#define PXA_DCMD_WIDTH1 (1 << 14) /* 1 byte width */68#define PXA_DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */69#define PXA_DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */70#define PXA_DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */71 72#define PDMA_ALIGNMENT 373#define PDMA_MAX_DESC_BYTES (PXA_DCMD_LENGTH & ~((1 << PDMA_ALIGNMENT) - 1))74 75struct pxad_desc_hw {76 u32 ddadr; /* Points to the next descriptor + flags */77 u32 dsadr; /* DSADR value for the current transfer */78 u32 dtadr; /* DTADR value for the current transfer */79 u32 dcmd; /* DCMD value for the current transfer */80} __aligned(16);81 82struct pxad_desc_sw {83 struct virt_dma_desc vd; /* Virtual descriptor */84 int nb_desc; /* Number of hw. descriptors */85 size_t len; /* Number of bytes xfered */86 dma_addr_t first; /* First descriptor's addr */87 88 /* At least one descriptor has an src/dst address not multiple of 8 */89 bool misaligned;90 bool cyclic;91 struct dma_pool *desc_pool; /* Channel's used allocator */92 93 struct pxad_desc_hw *hw_desc[] __counted_by(nb_desc);94 /* DMA coherent descriptors */95};96 97struct pxad_phy {98 int idx;99 void __iomem *base;100 struct pxad_chan *vchan;101};102 103struct pxad_chan {104 struct virt_dma_chan vc; /* Virtual channel */105 u32 drcmr; /* Requestor of the channel */106 enum pxad_chan_prio prio; /* Required priority of phy */107 /*108 * At least one desc_sw in submitted or issued transfers on this channel109 * has one address such as: addr % 8 != 0. This implies the DALGN110 * setting on the phy.111 */112 bool misaligned;113 struct dma_slave_config cfg; /* Runtime config */114 115 /* protected by vc->lock */116 struct pxad_phy *phy;117 struct dma_pool *desc_pool; /* Descriptors pool */118 dma_cookie_t bus_error;119 120 wait_queue_head_t wq_state;121};122 123struct pxad_device {124 struct dma_device slave;125 int nr_chans;126 int nr_requestors;127 void __iomem *base;128 struct pxad_phy *phys;129 spinlock_t phy_lock; /* Phy association */130#ifdef CONFIG_DEBUG_FS131 struct dentry *dbgfs_root;132 struct dentry **dbgfs_chan;133#endif134};135 136#define tx_to_pxad_desc(tx) \137 container_of(tx, struct pxad_desc_sw, async_tx)138#define to_pxad_chan(dchan) \139 container_of(dchan, struct pxad_chan, vc.chan)140#define to_pxad_dev(dmadev) \141 container_of(dmadev, struct pxad_device, slave)142#define to_pxad_sw_desc(_vd) \143 container_of((_vd), struct pxad_desc_sw, vd)144 145#define _phy_readl_relaxed(phy, _reg) \146 readl_relaxed((phy)->base + _reg((phy)->idx))147#define phy_readl_relaxed(phy, _reg) \148 ({ \149 u32 _v; \150 _v = readl_relaxed((phy)->base + _reg((phy)->idx)); \151 dev_vdbg(&phy->vchan->vc.chan.dev->device, \152 "%s(): readl(%s): 0x%08x\n", __func__, #_reg, \153 _v); \154 _v; \155 })156#define phy_writel(phy, val, _reg) \157 do { \158 writel((val), (phy)->base + _reg((phy)->idx)); \159 dev_vdbg(&phy->vchan->vc.chan.dev->device, \160 "%s(): writel(0x%08x, %s)\n", \161 __func__, (u32)(val), #_reg); \162 } while (0)163#define phy_writel_relaxed(phy, val, _reg) \164 do { \165 writel_relaxed((val), (phy)->base + _reg((phy)->idx)); \166 dev_vdbg(&phy->vchan->vc.chan.dev->device, \167 "%s(): writel_relaxed(0x%08x, %s)\n", \168 __func__, (u32)(val), #_reg); \169 } while (0)170 171static unsigned int pxad_drcmr(unsigned int line)172{173 if (line < 64)174 return 0x100 + line * 4;175 return 0x1000 + line * 4;176}177 178static bool pxad_filter_fn(struct dma_chan *chan, void *param);179 180/*181 * Debug fs182 */183#ifdef CONFIG_DEBUG_FS184#include <linux/debugfs.h>185#include <linux/uaccess.h>186#include <linux/seq_file.h>187 188static int requester_chan_show(struct seq_file *s, void *p)189{190 struct pxad_phy *phy = s->private;191 int i;192 u32 drcmr;193 194 seq_printf(s, "DMA channel %d requester :\n", phy->idx);195 for (i = 0; i < 70; i++) {196 drcmr = readl_relaxed(phy->base + pxad_drcmr(i));197 if ((drcmr & DRCMR_CHLNUM) == phy->idx)198 seq_printf(s, "\tRequester %d (MAPVLD=%d)\n", i,199 !!(drcmr & DRCMR_MAPVLD));200 }201 return 0;202}203 204static inline int dbg_burst_from_dcmd(u32 dcmd)205{206 int burst = (dcmd >> 16) & 0x3;207 208 return burst ? 4 << burst : 0;209}210 211static int is_phys_valid(unsigned long addr)212{213 return pfn_valid(__phys_to_pfn(addr));214}215 216#define PXA_DCSR_STR(flag) (dcsr & PXA_DCSR_##flag ? #flag" " : "")217#define PXA_DCMD_STR(flag) (dcmd & PXA_DCMD_##flag ? #flag" " : "")218 219static int descriptors_show(struct seq_file *s, void *p)220{221 struct pxad_phy *phy = s->private;222 int i, max_show = 20, burst, width;223 u32 dcmd;224 unsigned long phys_desc, ddadr;225 struct pxad_desc_hw *desc;226 227 phys_desc = ddadr = _phy_readl_relaxed(phy, DDADR);228 229 seq_printf(s, "DMA channel %d descriptors :\n", phy->idx);230 seq_printf(s, "[%03d] First descriptor unknown\n", 0);231 for (i = 1; i < max_show && is_phys_valid(phys_desc); i++) {232 desc = phys_to_virt(phys_desc);233 dcmd = desc->dcmd;234 burst = dbg_burst_from_dcmd(dcmd);235 width = (1 << ((dcmd >> 14) & 0x3)) >> 1;236 237 seq_printf(s, "[%03d] Desc at %08lx(virt %p)\n",238 i, phys_desc, desc);239 seq_printf(s, "\tDDADR = %08x\n", desc->ddadr);240 seq_printf(s, "\tDSADR = %08x\n", desc->dsadr);241 seq_printf(s, "\tDTADR = %08x\n", desc->dtadr);242 seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n",243 dcmd,244 PXA_DCMD_STR(INCSRCADDR), PXA_DCMD_STR(INCTRGADDR),245 PXA_DCMD_STR(FLOWSRC), PXA_DCMD_STR(FLOWTRG),246 PXA_DCMD_STR(STARTIRQEN), PXA_DCMD_STR(ENDIRQEN),247 PXA_DCMD_STR(ENDIAN), burst, width,248 dcmd & PXA_DCMD_LENGTH);249 phys_desc = desc->ddadr;250 }251 if (i == max_show)252 seq_printf(s, "[%03d] Desc at %08lx ... max display reached\n",253 i, phys_desc);254 else255 seq_printf(s, "[%03d] Desc at %08lx is %s\n",256 i, phys_desc, phys_desc == DDADR_STOP ?257 "DDADR_STOP" : "invalid");258 259 return 0;260}261 262static int chan_state_show(struct seq_file *s, void *p)263{264 struct pxad_phy *phy = s->private;265 u32 dcsr, dcmd;266 int burst, width;267 static const char * const str_prio[] = {268 "high", "normal", "low", "invalid"269 };270 271 dcsr = _phy_readl_relaxed(phy, DCSR);272 dcmd = _phy_readl_relaxed(phy, DCMD);273 burst = dbg_burst_from_dcmd(dcmd);274 width = (1 << ((dcmd >> 14) & 0x3)) >> 1;275 276 seq_printf(s, "DMA channel %d\n", phy->idx);277 seq_printf(s, "\tPriority : %s\n",278 str_prio[(phy->idx & 0xf) / 4]);279 seq_printf(s, "\tUnaligned transfer bit: %s\n",280 _phy_readl_relaxed(phy, DALGN) & BIT(phy->idx) ?281 "yes" : "no");282 seq_printf(s, "\tDCSR = %08x (%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",283 dcsr, PXA_DCSR_STR(RUN), PXA_DCSR_STR(NODESC),284 PXA_DCSR_STR(STOPIRQEN), PXA_DCSR_STR(EORIRQEN),285 PXA_DCSR_STR(EORJMPEN), PXA_DCSR_STR(EORSTOPEN),286 PXA_DCSR_STR(SETCMPST), PXA_DCSR_STR(CLRCMPST),287 PXA_DCSR_STR(CMPST), PXA_DCSR_STR(EORINTR),288 PXA_DCSR_STR(REQPEND), PXA_DCSR_STR(STOPSTATE),289 PXA_DCSR_STR(ENDINTR), PXA_DCSR_STR(STARTINTR),290 PXA_DCSR_STR(BUSERR));291 292 seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n",293 dcmd,294 PXA_DCMD_STR(INCSRCADDR), PXA_DCMD_STR(INCTRGADDR),295 PXA_DCMD_STR(FLOWSRC), PXA_DCMD_STR(FLOWTRG),296 PXA_DCMD_STR(STARTIRQEN), PXA_DCMD_STR(ENDIRQEN),297 PXA_DCMD_STR(ENDIAN), burst, width, dcmd & PXA_DCMD_LENGTH);298 seq_printf(s, "\tDSADR = %08x\n", _phy_readl_relaxed(phy, DSADR));299 seq_printf(s, "\tDTADR = %08x\n", _phy_readl_relaxed(phy, DTADR));300 seq_printf(s, "\tDDADR = %08x\n", _phy_readl_relaxed(phy, DDADR));301 302 return 0;303}304 305static int state_show(struct seq_file *s, void *p)306{307 struct pxad_device *pdev = s->private;308 309 /* basic device status */310 seq_puts(s, "DMA engine status\n");311 seq_printf(s, "\tChannel number: %d\n", pdev->nr_chans);312 313 return 0;314}315 316DEFINE_SHOW_ATTRIBUTE(state);317DEFINE_SHOW_ATTRIBUTE(chan_state);318DEFINE_SHOW_ATTRIBUTE(descriptors);319DEFINE_SHOW_ATTRIBUTE(requester_chan);320 321static struct dentry *pxad_dbg_alloc_chan(struct pxad_device *pdev,322 int ch, struct dentry *chandir)323{324 char chan_name[11];325 struct dentry *chan;326 void *dt;327 328 scnprintf(chan_name, sizeof(chan_name), "%d", ch);329 chan = debugfs_create_dir(chan_name, chandir);330 dt = (void *)&pdev->phys[ch];331 332 debugfs_create_file("state", 0400, chan, dt, &chan_state_fops);333 debugfs_create_file("descriptors", 0400, chan, dt, &descriptors_fops);334 debugfs_create_file("requesters", 0400, chan, dt, &requester_chan_fops);335 336 return chan;337}338 339static void pxad_init_debugfs(struct pxad_device *pdev)340{341 int i;342 struct dentry *chandir;343 344 pdev->dbgfs_chan =345 kmalloc_array(pdev->nr_chans, sizeof(struct dentry *),346 GFP_KERNEL);347 if (!pdev->dbgfs_chan)348 return;349 350 pdev->dbgfs_root = debugfs_create_dir(dev_name(pdev->slave.dev), NULL);351 352 debugfs_create_file("state", 0400, pdev->dbgfs_root, pdev, &state_fops);353 354 chandir = debugfs_create_dir("channels", pdev->dbgfs_root);355 356 for (i = 0; i < pdev->nr_chans; i++)357 pdev->dbgfs_chan[i] = pxad_dbg_alloc_chan(pdev, i, chandir);358}359 360static void pxad_cleanup_debugfs(struct pxad_device *pdev)361{362 debugfs_remove_recursive(pdev->dbgfs_root);363}364#else365static inline void pxad_init_debugfs(struct pxad_device *pdev) {}366static inline void pxad_cleanup_debugfs(struct pxad_device *pdev) {}367#endif368 369static struct pxad_phy *lookup_phy(struct pxad_chan *pchan)370{371 int prio, i;372 struct pxad_device *pdev = to_pxad_dev(pchan->vc.chan.device);373 struct pxad_phy *phy, *found = NULL;374 unsigned long flags;375 376 /*377 * dma channel priorities378 * ch 0 - 3, 16 - 19 <--> (0)379 * ch 4 - 7, 20 - 23 <--> (1)380 * ch 8 - 11, 24 - 27 <--> (2)381 * ch 12 - 15, 28 - 31 <--> (3)382 */383 384 spin_lock_irqsave(&pdev->phy_lock, flags);385 for (prio = pchan->prio; prio >= PXAD_PRIO_HIGHEST; prio--) {386 for (i = 0; i < pdev->nr_chans; i++) {387 if (prio != (i & 0xf) >> 2)388 continue;389 phy = &pdev->phys[i];390 if (!phy->vchan) {391 phy->vchan = pchan;392 found = phy;393 goto out_unlock;394 }395 }396 }397 398out_unlock:399 spin_unlock_irqrestore(&pdev->phy_lock, flags);400 dev_dbg(&pchan->vc.chan.dev->device,401 "%s(): phy=%p(%d)\n", __func__, found,402 found ? found->idx : -1);403 404 return found;405}406 407static void pxad_free_phy(struct pxad_chan *chan)408{409 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device);410 unsigned long flags;411 u32 reg;412 413 dev_dbg(&chan->vc.chan.dev->device,414 "%s(): freeing\n", __func__);415 if (!chan->phy)416 return;417 418 /* clear the channel mapping in DRCMR */419 if (chan->drcmr <= pdev->nr_requestors) {420 reg = pxad_drcmr(chan->drcmr);421 writel_relaxed(0, chan->phy->base + reg);422 }423 424 spin_lock_irqsave(&pdev->phy_lock, flags);425 chan->phy->vchan = NULL;426 chan->phy = NULL;427 spin_unlock_irqrestore(&pdev->phy_lock, flags);428}429 430static bool is_chan_running(struct pxad_chan *chan)431{432 u32 dcsr;433 struct pxad_phy *phy = chan->phy;434 435 if (!phy)436 return false;437 dcsr = phy_readl_relaxed(phy, DCSR);438 return dcsr & PXA_DCSR_RUN;439}440 441static bool is_running_chan_misaligned(struct pxad_chan *chan)442{443 u32 dalgn;444 445 BUG_ON(!chan->phy);446 dalgn = phy_readl_relaxed(chan->phy, DALGN);447 return dalgn & (BIT(chan->phy->idx));448}449 450static void phy_enable(struct pxad_phy *phy, bool misaligned)451{452 struct pxad_device *pdev;453 u32 reg, dalgn;454 455 if (!phy->vchan)456 return;457 458 dev_dbg(&phy->vchan->vc.chan.dev->device,459 "%s(); phy=%p(%d) misaligned=%d\n", __func__,460 phy, phy->idx, misaligned);461 462 pdev = to_pxad_dev(phy->vchan->vc.chan.device);463 if (phy->vchan->drcmr <= pdev->nr_requestors) {464 reg = pxad_drcmr(phy->vchan->drcmr);465 writel_relaxed(DRCMR_MAPVLD | phy->idx, phy->base + reg);466 }467 468 dalgn = phy_readl_relaxed(phy, DALGN);469 if (misaligned)470 dalgn |= BIT(phy->idx);471 else472 dalgn &= ~BIT(phy->idx);473 phy_writel_relaxed(phy, dalgn, DALGN);474 475 phy_writel(phy, PXA_DCSR_STOPIRQEN | PXA_DCSR_ENDINTR |476 PXA_DCSR_BUSERR | PXA_DCSR_RUN, DCSR);477}478 479static void phy_disable(struct pxad_phy *phy)480{481 u32 dcsr;482 483 if (!phy)484 return;485 486 dcsr = phy_readl_relaxed(phy, DCSR);487 dev_dbg(&phy->vchan->vc.chan.dev->device,488 "%s(): phy=%p(%d)\n", __func__, phy, phy->idx);489 phy_writel(phy, dcsr & ~PXA_DCSR_RUN & ~PXA_DCSR_STOPIRQEN, DCSR);490}491 492static void pxad_launch_chan(struct pxad_chan *chan,493 struct pxad_desc_sw *desc)494{495 dev_dbg(&chan->vc.chan.dev->device,496 "%s(): desc=%p\n", __func__, desc);497 if (!chan->phy) {498 chan->phy = lookup_phy(chan);499 if (!chan->phy) {500 dev_dbg(&chan->vc.chan.dev->device,501 "%s(): no free dma channel\n", __func__);502 return;503 }504 }505 chan->bus_error = 0;506 507 /*508 * Program the descriptor's address into the DMA controller,509 * then start the DMA transaction510 */511 phy_writel(chan->phy, desc->first, DDADR);512 phy_enable(chan->phy, chan->misaligned);513 wake_up(&chan->wq_state);514}515 516static void set_updater_desc(struct pxad_desc_sw *sw_desc,517 unsigned long flags)518{519 struct pxad_desc_hw *updater =520 sw_desc->hw_desc[sw_desc->nb_desc - 1];521 dma_addr_t dma = sw_desc->hw_desc[sw_desc->nb_desc - 2]->ddadr;522 523 updater->ddadr = DDADR_STOP;524 updater->dsadr = dma;525 updater->dtadr = dma + 8;526 updater->dcmd = PXA_DCMD_WIDTH4 | PXA_DCMD_BURST32 |527 (PXA_DCMD_LENGTH & sizeof(u32));528 if (flags & DMA_PREP_INTERRUPT)529 updater->dcmd |= PXA_DCMD_ENDIRQEN;530 if (sw_desc->cyclic)531 sw_desc->hw_desc[sw_desc->nb_desc - 2]->ddadr = sw_desc->first;532}533 534static bool is_desc_completed(struct virt_dma_desc *vd)535{536 struct pxad_desc_sw *sw_desc = to_pxad_sw_desc(vd);537 struct pxad_desc_hw *updater =538 sw_desc->hw_desc[sw_desc->nb_desc - 1];539 540 return updater->dtadr != (updater->dsadr + 8);541}542 543static void pxad_desc_chain(struct virt_dma_desc *vd1,544 struct virt_dma_desc *vd2)545{546 struct pxad_desc_sw *desc1 = to_pxad_sw_desc(vd1);547 struct pxad_desc_sw *desc2 = to_pxad_sw_desc(vd2);548 dma_addr_t dma_to_chain;549 550 dma_to_chain = desc2->first;551 desc1->hw_desc[desc1->nb_desc - 1]->ddadr = dma_to_chain;552}553 554static bool pxad_try_hotchain(struct virt_dma_chan *vc,555 struct virt_dma_desc *vd)556{557 struct virt_dma_desc *vd_last_issued = NULL;558 struct pxad_chan *chan = to_pxad_chan(&vc->chan);559 560 /*561 * Attempt to hot chain the tx if the phy is still running. This is562 * considered successful only if either the channel is still running563 * after the chaining, or if the chained transfer is completed after564 * having been hot chained.565 * A change of alignment is not allowed, and forbids hotchaining.566 */567 if (is_chan_running(chan)) {568 BUG_ON(list_empty(&vc->desc_issued));569 570 if (!is_running_chan_misaligned(chan) &&571 to_pxad_sw_desc(vd)->misaligned)572 return false;573 574 vd_last_issued = list_entry(vc->desc_issued.prev,575 struct virt_dma_desc, node);576 pxad_desc_chain(vd_last_issued, vd);577 if (is_chan_running(chan) || is_desc_completed(vd))578 return true;579 }580 581 return false;582}583 584static unsigned int clear_chan_irq(struct pxad_phy *phy)585{586 u32 dcsr;587 u32 dint = readl(phy->base + DINT);588 589 if (!(dint & BIT(phy->idx)))590 return PXA_DCSR_RUN;591 592 /* clear irq */593 dcsr = phy_readl_relaxed(phy, DCSR);594 phy_writel(phy, dcsr, DCSR);595 if ((dcsr & PXA_DCSR_BUSERR) && (phy->vchan))596 dev_warn(&phy->vchan->vc.chan.dev->device,597 "%s(chan=%p): PXA_DCSR_BUSERR\n",598 __func__, &phy->vchan);599 600 return dcsr & ~PXA_DCSR_RUN;601}602 603static irqreturn_t pxad_chan_handler(int irq, void *dev_id)604{605 struct pxad_phy *phy = dev_id;606 struct pxad_chan *chan = phy->vchan;607 struct virt_dma_desc *vd, *tmp;608 unsigned int dcsr;609 bool vd_completed;610 dma_cookie_t last_started = 0;611 612 BUG_ON(!chan);613 614 dcsr = clear_chan_irq(phy);615 if (dcsr & PXA_DCSR_RUN)616 return IRQ_NONE;617 618 spin_lock(&chan->vc.lock);619 list_for_each_entry_safe(vd, tmp, &chan->vc.desc_issued, node) {620 vd_completed = is_desc_completed(vd);621 dev_dbg(&chan->vc.chan.dev->device,622 "%s(): checking txd %p[%x]: completed=%d dcsr=0x%x\n",623 __func__, vd, vd->tx.cookie, vd_completed,624 dcsr);625 last_started = vd->tx.cookie;626 if (to_pxad_sw_desc(vd)->cyclic) {627 vchan_cyclic_callback(vd);628 break;629 }630 if (vd_completed) {631 list_del(&vd->node);632 vchan_cookie_complete(vd);633 } else {634 break;635 }636 }637 638 if (dcsr & PXA_DCSR_BUSERR) {639 chan->bus_error = last_started;640 phy_disable(phy);641 }642 643 if (!chan->bus_error && dcsr & PXA_DCSR_STOPSTATE) {644 dev_dbg(&chan->vc.chan.dev->device,645 "%s(): channel stopped, submitted_empty=%d issued_empty=%d",646 __func__,647 list_empty(&chan->vc.desc_submitted),648 list_empty(&chan->vc.desc_issued));649 phy_writel_relaxed(phy, dcsr & ~PXA_DCSR_STOPIRQEN, DCSR);650 651 if (list_empty(&chan->vc.desc_issued)) {652 chan->misaligned =653 !list_empty(&chan->vc.desc_submitted);654 } else {655 vd = list_first_entry(&chan->vc.desc_issued,656 struct virt_dma_desc, node);657 pxad_launch_chan(chan, to_pxad_sw_desc(vd));658 }659 }660 spin_unlock(&chan->vc.lock);661 wake_up(&chan->wq_state);662 663 return IRQ_HANDLED;664}665 666static irqreturn_t pxad_int_handler(int irq, void *dev_id)667{668 struct pxad_device *pdev = dev_id;669 struct pxad_phy *phy;670 u32 dint = readl(pdev->base + DINT);671 int i, ret = IRQ_NONE;672 673 while (dint) {674 i = __ffs(dint);675 dint &= (dint - 1);676 phy = &pdev->phys[i];677 if (pxad_chan_handler(irq, phy) == IRQ_HANDLED)678 ret = IRQ_HANDLED;679 }680 681 return ret;682}683 684static int pxad_alloc_chan_resources(struct dma_chan *dchan)685{686 struct pxad_chan *chan = to_pxad_chan(dchan);687 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device);688 689 if (chan->desc_pool)690 return 1;691 692 chan->desc_pool = dma_pool_create(dma_chan_name(dchan),693 pdev->slave.dev,694 sizeof(struct pxad_desc_hw),695 __alignof__(struct pxad_desc_hw),696 0);697 if (!chan->desc_pool) {698 dev_err(&chan->vc.chan.dev->device,699 "%s(): unable to allocate descriptor pool\n",700 __func__);701 return -ENOMEM;702 }703 704 return 1;705}706 707static void pxad_free_chan_resources(struct dma_chan *dchan)708{709 struct pxad_chan *chan = to_pxad_chan(dchan);710 711 vchan_free_chan_resources(&chan->vc);712 dma_pool_destroy(chan->desc_pool);713 chan->desc_pool = NULL;714 715 chan->drcmr = U32_MAX;716 chan->prio = PXAD_PRIO_LOWEST;717}718 719static void pxad_free_desc(struct virt_dma_desc *vd)720{721 int i;722 dma_addr_t dma;723 struct pxad_desc_sw *sw_desc = to_pxad_sw_desc(vd);724 725 for (i = sw_desc->nb_desc - 1; i >= 0; i--) {726 if (i > 0)727 dma = sw_desc->hw_desc[i - 1]->ddadr;728 else729 dma = sw_desc->first;730 dma_pool_free(sw_desc->desc_pool,731 sw_desc->hw_desc[i], dma);732 }733 sw_desc->nb_desc = 0;734 kfree(sw_desc);735}736 737static struct pxad_desc_sw *738pxad_alloc_desc(struct pxad_chan *chan, unsigned int nb_hw_desc)739{740 struct pxad_desc_sw *sw_desc;741 dma_addr_t dma;742 void *desc;743 int i;744 745 sw_desc = kzalloc(struct_size(sw_desc, hw_desc, nb_hw_desc),746 GFP_NOWAIT);747 if (!sw_desc)748 return NULL;749 sw_desc->desc_pool = chan->desc_pool;750 751 for (i = 0; i < nb_hw_desc; i++) {752 desc = dma_pool_alloc(sw_desc->desc_pool, GFP_NOWAIT, &dma);753 if (!desc) {754 dev_err(&chan->vc.chan.dev->device,755 "%s(): Couldn't allocate the %dth hw_desc from dma_pool %p\n",756 __func__, i, sw_desc->desc_pool);757 goto err;758 }759 760 sw_desc->nb_desc++;761 sw_desc->hw_desc[i] = desc;762 763 if (i == 0)764 sw_desc->first = dma;765 else766 sw_desc->hw_desc[i - 1]->ddadr = dma;767 }768 769 return sw_desc;770err:771 pxad_free_desc(&sw_desc->vd);772 return NULL;773}774 775static dma_cookie_t pxad_tx_submit(struct dma_async_tx_descriptor *tx)776{777 struct virt_dma_chan *vc = to_virt_chan(tx->chan);778 struct pxad_chan *chan = to_pxad_chan(&vc->chan);779 struct virt_dma_desc *vd_chained = NULL,780 *vd = container_of(tx, struct virt_dma_desc, tx);781 dma_cookie_t cookie;782 unsigned long flags;783 784 set_updater_desc(to_pxad_sw_desc(vd), tx->flags);785 786 spin_lock_irqsave(&vc->lock, flags);787 cookie = dma_cookie_assign(tx);788 789 if (list_empty(&vc->desc_submitted) && pxad_try_hotchain(vc, vd)) {790 list_move_tail(&vd->node, &vc->desc_issued);791 dev_dbg(&chan->vc.chan.dev->device,792 "%s(): txd %p[%x]: submitted (hot linked)\n",793 __func__, vd, cookie);794 goto out;795 }796 797 /*798 * Fallback to placing the tx in the submitted queue799 */800 if (!list_empty(&vc->desc_submitted)) {801 vd_chained = list_entry(vc->desc_submitted.prev,802 struct virt_dma_desc, node);803 /*804 * Only chain the descriptors if no new misalignment is805 * introduced. If a new misalignment is chained, let the channel806 * stop, and be relaunched in misalign mode from the irq807 * handler.808 */809 if (chan->misaligned || !to_pxad_sw_desc(vd)->misaligned)810 pxad_desc_chain(vd_chained, vd);811 else812 vd_chained = NULL;813 }814 dev_dbg(&chan->vc.chan.dev->device,815 "%s(): txd %p[%x]: submitted (%s linked)\n",816 __func__, vd, cookie, vd_chained ? "cold" : "not");817 list_move_tail(&vd->node, &vc->desc_submitted);818 chan->misaligned |= to_pxad_sw_desc(vd)->misaligned;819 820out:821 spin_unlock_irqrestore(&vc->lock, flags);822 return cookie;823}824 825static void pxad_issue_pending(struct dma_chan *dchan)826{827 struct pxad_chan *chan = to_pxad_chan(dchan);828 struct virt_dma_desc *vd_first;829 unsigned long flags;830 831 spin_lock_irqsave(&chan->vc.lock, flags);832 if (list_empty(&chan->vc.desc_submitted))833 goto out;834 835 vd_first = list_first_entry(&chan->vc.desc_submitted,836 struct virt_dma_desc, node);837 dev_dbg(&chan->vc.chan.dev->device,838 "%s(): txd %p[%x]", __func__, vd_first, vd_first->tx.cookie);839 840 vchan_issue_pending(&chan->vc);841 if (!pxad_try_hotchain(&chan->vc, vd_first))842 pxad_launch_chan(chan, to_pxad_sw_desc(vd_first));843out:844 spin_unlock_irqrestore(&chan->vc.lock, flags);845}846 847static inline struct dma_async_tx_descriptor *848pxad_tx_prep(struct virt_dma_chan *vc, struct virt_dma_desc *vd,849 unsigned long tx_flags)850{851 struct dma_async_tx_descriptor *tx;852 struct pxad_chan *chan = container_of(vc, struct pxad_chan, vc);853 854 INIT_LIST_HEAD(&vd->node);855 tx = vchan_tx_prep(vc, vd, tx_flags);856 tx->tx_submit = pxad_tx_submit;857 dev_dbg(&chan->vc.chan.dev->device,858 "%s(): vc=%p txd=%p[%x] flags=0x%lx\n", __func__,859 vc, vd, vd->tx.cookie,860 tx_flags);861 862 return tx;863}864 865static void pxad_get_config(struct pxad_chan *chan,866 enum dma_transfer_direction dir,867 u32 *dcmd, u32 *dev_src, u32 *dev_dst)868{869 u32 maxburst = 0, dev_addr = 0;870 enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED;871 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device);872 873 *dcmd = 0;874 if (dir == DMA_DEV_TO_MEM) {875 maxburst = chan->cfg.src_maxburst;876 width = chan->cfg.src_addr_width;877 dev_addr = chan->cfg.src_addr;878 *dev_src = dev_addr;879 *dcmd |= PXA_DCMD_INCTRGADDR;880 if (chan->drcmr <= pdev->nr_requestors)881 *dcmd |= PXA_DCMD_FLOWSRC;882 }883 if (dir == DMA_MEM_TO_DEV) {884 maxburst = chan->cfg.dst_maxburst;885 width = chan->cfg.dst_addr_width;886 dev_addr = chan->cfg.dst_addr;887 *dev_dst = dev_addr;888 *dcmd |= PXA_DCMD_INCSRCADDR;889 if (chan->drcmr <= pdev->nr_requestors)890 *dcmd |= PXA_DCMD_FLOWTRG;891 }892 if (dir == DMA_MEM_TO_MEM)893 *dcmd |= PXA_DCMD_BURST32 | PXA_DCMD_INCTRGADDR |894 PXA_DCMD_INCSRCADDR;895 896 dev_dbg(&chan->vc.chan.dev->device,897 "%s(): dev_addr=0x%x maxburst=%d width=%d dir=%d\n",898 __func__, dev_addr, maxburst, width, dir);899 900 if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)901 *dcmd |= PXA_DCMD_WIDTH1;902 else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)903 *dcmd |= PXA_DCMD_WIDTH2;904 else if (width == DMA_SLAVE_BUSWIDTH_4_BYTES)905 *dcmd |= PXA_DCMD_WIDTH4;906 907 if (maxburst == 8)908 *dcmd |= PXA_DCMD_BURST8;909 else if (maxburst == 16)910 *dcmd |= PXA_DCMD_BURST16;911 else if (maxburst == 32)912 *dcmd |= PXA_DCMD_BURST32;913}914 915static struct dma_async_tx_descriptor *916pxad_prep_memcpy(struct dma_chan *dchan,917 dma_addr_t dma_dst, dma_addr_t dma_src,918 size_t len, unsigned long flags)919{920 struct pxad_chan *chan = to_pxad_chan(dchan);921 struct pxad_desc_sw *sw_desc;922 struct pxad_desc_hw *hw_desc;923 u32 dcmd;924 unsigned int i, nb_desc = 0;925 size_t copy;926 927 if (!dchan || !len)928 return NULL;929 930 dev_dbg(&chan->vc.chan.dev->device,931 "%s(): dma_dst=0x%lx dma_src=0x%lx len=%zu flags=%lx\n",932 __func__, (unsigned long)dma_dst, (unsigned long)dma_src,933 len, flags);934 pxad_get_config(chan, DMA_MEM_TO_MEM, &dcmd, NULL, NULL);935 936 nb_desc = DIV_ROUND_UP(len, PDMA_MAX_DESC_BYTES);937 sw_desc = pxad_alloc_desc(chan, nb_desc + 1);938 if (!sw_desc)939 return NULL;940 sw_desc->len = len;941 942 if (!IS_ALIGNED(dma_src, 1 << PDMA_ALIGNMENT) ||943 !IS_ALIGNED(dma_dst, 1 << PDMA_ALIGNMENT))944 sw_desc->misaligned = true;945 946 i = 0;947 do {948 hw_desc = sw_desc->hw_desc[i++];949 copy = min_t(size_t, len, PDMA_MAX_DESC_BYTES);950 hw_desc->dcmd = dcmd | (PXA_DCMD_LENGTH & copy);951 hw_desc->dsadr = dma_src;952 hw_desc->dtadr = dma_dst;953 len -= copy;954 dma_src += copy;955 dma_dst += copy;956 } while (len);957 set_updater_desc(sw_desc, flags);958 959 return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags);960}961 962static struct dma_async_tx_descriptor *963pxad_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,964 unsigned int sg_len, enum dma_transfer_direction dir,965 unsigned long flags, void *context)966{967 struct pxad_chan *chan = to_pxad_chan(dchan);968 struct pxad_desc_sw *sw_desc;969 size_t len, avail;970 struct scatterlist *sg;971 dma_addr_t dma;972 u32 dcmd, dsadr = 0, dtadr = 0;973 unsigned int nb_desc = 0, i, j = 0;974 975 if ((sgl == NULL) || (sg_len == 0))976 return NULL;977 978 pxad_get_config(chan, dir, &dcmd, &dsadr, &dtadr);979 dev_dbg(&chan->vc.chan.dev->device,980 "%s(): dir=%d flags=%lx\n", __func__, dir, flags);981 982 for_each_sg(sgl, sg, sg_len, i)983 nb_desc += DIV_ROUND_UP(sg_dma_len(sg), PDMA_MAX_DESC_BYTES);984 sw_desc = pxad_alloc_desc(chan, nb_desc + 1);985 if (!sw_desc)986 return NULL;987 988 for_each_sg(sgl, sg, sg_len, i) {989 dma = sg_dma_address(sg);990 avail = sg_dma_len(sg);991 sw_desc->len += avail;992 993 do {994 len = min_t(size_t, avail, PDMA_MAX_DESC_BYTES);995 if (dma & 0x7)996 sw_desc->misaligned = true;997 998 sw_desc->hw_desc[j]->dcmd =999 dcmd | (PXA_DCMD_LENGTH & len);1000 sw_desc->hw_desc[j]->dsadr = dsadr ? dsadr : dma;1001 sw_desc->hw_desc[j++]->dtadr = dtadr ? dtadr : dma;1002 1003 dma += len;1004 avail -= len;1005 } while (avail);1006 }1007 set_updater_desc(sw_desc, flags);1008 1009 return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags);1010}1011 1012static struct dma_async_tx_descriptor *1013pxad_prep_dma_cyclic(struct dma_chan *dchan,1014 dma_addr_t buf_addr, size_t len, size_t period_len,1015 enum dma_transfer_direction dir, unsigned long flags)1016{1017 struct pxad_chan *chan = to_pxad_chan(dchan);1018 struct pxad_desc_sw *sw_desc;1019 struct pxad_desc_hw **phw_desc;1020 dma_addr_t dma;1021 u32 dcmd, dsadr = 0, dtadr = 0;1022 unsigned int nb_desc = 0;1023 1024 if (!dchan || !len || !period_len)1025 return NULL;1026 if ((dir != DMA_DEV_TO_MEM) && (dir != DMA_MEM_TO_DEV)) {1027 dev_err(&chan->vc.chan.dev->device,1028 "Unsupported direction for cyclic DMA\n");1029 return NULL;1030 }1031 /* the buffer length must be a multiple of period_len */1032 if (len % period_len != 0 || period_len > PDMA_MAX_DESC_BYTES ||1033 !IS_ALIGNED(period_len, 1 << PDMA_ALIGNMENT))1034 return NULL;1035 1036 pxad_get_config(chan, dir, &dcmd, &dsadr, &dtadr);1037 dcmd |= PXA_DCMD_ENDIRQEN | (PXA_DCMD_LENGTH & period_len);1038 dev_dbg(&chan->vc.chan.dev->device,1039 "%s(): buf_addr=0x%lx len=%zu period=%zu dir=%d flags=%lx\n",1040 __func__, (unsigned long)buf_addr, len, period_len, dir, flags);1041 1042 nb_desc = DIV_ROUND_UP(period_len, PDMA_MAX_DESC_BYTES);1043 nb_desc *= DIV_ROUND_UP(len, period_len);1044 sw_desc = pxad_alloc_desc(chan, nb_desc + 1);1045 if (!sw_desc)1046 return NULL;1047 sw_desc->cyclic = true;1048 sw_desc->len = len;1049 1050 phw_desc = sw_desc->hw_desc;1051 dma = buf_addr;1052 do {1053 phw_desc[0]->dsadr = dsadr ? dsadr : dma;1054 phw_desc[0]->dtadr = dtadr ? dtadr : dma;1055 phw_desc[0]->dcmd = dcmd;1056 phw_desc++;1057 dma += period_len;1058 len -= period_len;1059 } while (len);1060 set_updater_desc(sw_desc, flags);1061 1062 return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags);1063}1064 1065static int pxad_config(struct dma_chan *dchan,1066 struct dma_slave_config *cfg)1067{1068 struct pxad_chan *chan = to_pxad_chan(dchan);1069 1070 if (!dchan)1071 return -EINVAL;1072 1073 chan->cfg = *cfg;1074 return 0;1075}1076 1077static int pxad_terminate_all(struct dma_chan *dchan)1078{1079 struct pxad_chan *chan = to_pxad_chan(dchan);1080 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device);1081 struct virt_dma_desc *vd = NULL;1082 unsigned long flags;1083 struct pxad_phy *phy;1084 LIST_HEAD(head);1085 1086 dev_dbg(&chan->vc.chan.dev->device,1087 "%s(): vchan %p: terminate all\n", __func__, &chan->vc);1088 1089 spin_lock_irqsave(&chan->vc.lock, flags);1090 vchan_get_all_descriptors(&chan->vc, &head);1091 1092 list_for_each_entry(vd, &head, node) {1093 dev_dbg(&chan->vc.chan.dev->device,1094 "%s(): cancelling txd %p[%x] (completed=%d)", __func__,1095 vd, vd->tx.cookie, is_desc_completed(vd));1096 }1097 1098 phy = chan->phy;1099 if (phy) {1100 phy_disable(chan->phy);1101 pxad_free_phy(chan);1102 chan->phy = NULL;1103 spin_lock(&pdev->phy_lock);1104 phy->vchan = NULL;1105 spin_unlock(&pdev->phy_lock);1106 }1107 spin_unlock_irqrestore(&chan->vc.lock, flags);1108 vchan_dma_desc_free_list(&chan->vc, &head);1109 1110 return 0;1111}1112 1113static unsigned int pxad_residue(struct pxad_chan *chan,1114 dma_cookie_t cookie)1115{1116 struct virt_dma_desc *vd = NULL;1117 struct pxad_desc_sw *sw_desc = NULL;1118 struct pxad_desc_hw *hw_desc = NULL;1119 u32 curr, start, len, end, residue = 0;1120 unsigned long flags;1121 bool passed = false;1122 int i;1123 1124 /*1125 * If the channel does not have a phy pointer anymore, it has already1126 * been completed. Therefore, its residue is 0.1127 */1128 if (!chan->phy)1129 return 0;1130 1131 spin_lock_irqsave(&chan->vc.lock, flags);1132 1133 vd = vchan_find_desc(&chan->vc, cookie);1134 if (!vd)1135 goto out;1136 1137 sw_desc = to_pxad_sw_desc(vd);1138 if (sw_desc->hw_desc[0]->dcmd & PXA_DCMD_INCSRCADDR)1139 curr = phy_readl_relaxed(chan->phy, DSADR);1140 else1141 curr = phy_readl_relaxed(chan->phy, DTADR);1142 1143 /*1144 * curr has to be actually read before checking descriptor1145 * completion, so that a curr inside a status updater1146 * descriptor implies the following test returns true, and1147 * preventing reordering of curr load and the test.1148 */1149 rmb();1150 if (is_desc_completed(vd))1151 goto out;1152 1153 for (i = 0; i < sw_desc->nb_desc - 1; i++) {1154 hw_desc = sw_desc->hw_desc[i];1155 if (sw_desc->hw_desc[0]->dcmd & PXA_DCMD_INCSRCADDR)1156 start = hw_desc->dsadr;1157 else1158 start = hw_desc->dtadr;1159 len = hw_desc->dcmd & PXA_DCMD_LENGTH;1160 end = start + len;1161 1162 /*1163 * 'passed' will be latched once we found the descriptor1164 * which lies inside the boundaries of the curr1165 * pointer. All descriptors that occur in the list1166 * _after_ we found that partially handled descriptor1167 * are still to be processed and are hence added to the1168 * residual bytes counter.1169 */1170 1171 if (passed) {1172 residue += len;1173 } else if (curr >= start && curr <= end) {1174 residue += end - curr;1175 passed = true;1176 }1177 }1178 if (!passed)1179 residue = sw_desc->len;1180 1181out:1182 spin_unlock_irqrestore(&chan->vc.lock, flags);1183 dev_dbg(&chan->vc.chan.dev->device,1184 "%s(): txd %p[%x] sw_desc=%p: %d\n",1185 __func__, vd, cookie, sw_desc, residue);1186 return residue;1187}1188 1189static enum dma_status pxad_tx_status(struct dma_chan *dchan,1190 dma_cookie_t cookie,1191 struct dma_tx_state *txstate)1192{1193 struct pxad_chan *chan = to_pxad_chan(dchan);1194 enum dma_status ret;1195 1196 if (cookie == chan->bus_error)1197 return DMA_ERROR;1198 1199 ret = dma_cookie_status(dchan, cookie, txstate);1200 if (likely(txstate && (ret != DMA_ERROR)))1201 dma_set_residue(txstate, pxad_residue(chan, cookie));1202 1203 return ret;1204}1205 1206static void pxad_synchronize(struct dma_chan *dchan)1207{1208 struct pxad_chan *chan = to_pxad_chan(dchan);1209 1210 wait_event(chan->wq_state, !is_chan_running(chan));1211 vchan_synchronize(&chan->vc);1212}1213 1214static void pxad_free_channels(struct dma_device *dmadev)1215{1216 struct pxad_chan *c, *cn;1217 1218 list_for_each_entry_safe(c, cn, &dmadev->channels,1219 vc.chan.device_node) {1220 list_del(&c->vc.chan.device_node);1221 tasklet_kill(&c->vc.task);1222 }1223}1224 1225static void pxad_remove(struct platform_device *op)1226{1227 struct pxad_device *pdev = platform_get_drvdata(op);1228 1229 pxad_cleanup_debugfs(pdev);1230 pxad_free_channels(&pdev->slave);1231}1232 1233static int pxad_init_phys(struct platform_device *op,1234 struct pxad_device *pdev,1235 unsigned int nb_phy_chans)1236{1237 int irq0, irq, nr_irq = 0, i, ret;1238 struct pxad_phy *phy;1239 1240 irq0 = platform_get_irq(op, 0);1241 if (irq0 < 0)1242 return irq0;1243 1244 pdev->phys = devm_kcalloc(&op->dev, nb_phy_chans,1245 sizeof(pdev->phys[0]), GFP_KERNEL);1246 if (!pdev->phys)1247 return -ENOMEM;1248 1249 for (i = 0; i < nb_phy_chans; i++)1250 if (platform_get_irq_optional(op, i) > 0)1251 nr_irq++;1252 1253 for (i = 0; i < nb_phy_chans; i++) {1254 phy = &pdev->phys[i];1255 phy->base = pdev->base;1256 phy->idx = i;1257 irq = platform_get_irq_optional(op, i);1258 if ((nr_irq > 1) && (irq > 0))1259 ret = devm_request_irq(&op->dev, irq,1260 pxad_chan_handler,1261 IRQF_SHARED, "pxa-dma", phy);1262 if ((nr_irq == 1) && (i == 0))1263 ret = devm_request_irq(&op->dev, irq0,1264 pxad_int_handler,1265 IRQF_SHARED, "pxa-dma", pdev);1266 if (ret) {1267 dev_err(pdev->slave.dev,1268 "%s(): can't request irq %d:%d\n", __func__,1269 irq, ret);1270 return ret;1271 }1272 }1273 1274 return 0;1275}1276 1277static const struct of_device_id pxad_dt_ids[] = {1278 { .compatible = "marvell,pdma-1.0", },1279 {}1280};1281MODULE_DEVICE_TABLE(of, pxad_dt_ids);1282 1283static struct dma_chan *pxad_dma_xlate(struct of_phandle_args *dma_spec,1284 struct of_dma *ofdma)1285{1286 struct pxad_device *d = ofdma->of_dma_data;1287 struct dma_chan *chan;1288 1289 chan = dma_get_any_slave_channel(&d->slave);1290 if (!chan)1291 return NULL;1292 1293 to_pxad_chan(chan)->drcmr = dma_spec->args[0];1294 to_pxad_chan(chan)->prio = dma_spec->args[1];1295 1296 return chan;1297}1298 1299static int pxad_init_dmadev(struct platform_device *op,1300 struct pxad_device *pdev,1301 unsigned int nr_phy_chans,1302 unsigned int nr_requestors)1303{1304 int ret;1305 unsigned int i;1306 struct pxad_chan *c;1307 1308 pdev->nr_chans = nr_phy_chans;1309 pdev->nr_requestors = nr_requestors;1310 INIT_LIST_HEAD(&pdev->slave.channels);1311 pdev->slave.device_alloc_chan_resources = pxad_alloc_chan_resources;1312 pdev->slave.device_free_chan_resources = pxad_free_chan_resources;1313 pdev->slave.device_tx_status = pxad_tx_status;1314 pdev->slave.device_issue_pending = pxad_issue_pending;1315 pdev->slave.device_config = pxad_config;1316 pdev->slave.device_synchronize = pxad_synchronize;1317 pdev->slave.device_terminate_all = pxad_terminate_all;1318 1319 if (op->dev.coherent_dma_mask)1320 dma_set_mask(&op->dev, op->dev.coherent_dma_mask);1321 else1322 dma_set_mask(&op->dev, DMA_BIT_MASK(32));1323 1324 ret = pxad_init_phys(op, pdev, nr_phy_chans);1325 if (ret)1326 return ret;1327 1328 for (i = 0; i < nr_phy_chans; i++) {1329 c = devm_kzalloc(&op->dev, sizeof(*c), GFP_KERNEL);1330 if (!c)1331 return -ENOMEM;1332 1333 c->drcmr = U32_MAX;1334 c->prio = PXAD_PRIO_LOWEST;1335 c->vc.desc_free = pxad_free_desc;1336 vchan_init(&c->vc, &pdev->slave);1337 init_waitqueue_head(&c->wq_state);1338 }1339 1340 return dmaenginem_async_device_register(&pdev->slave);1341}1342 1343static int pxad_probe(struct platform_device *op)1344{1345 struct pxad_device *pdev;1346 const struct dma_slave_map *slave_map = NULL;1347 struct mmp_dma_platdata *pdata = dev_get_platdata(&op->dev);1348 int ret, dma_channels = 0, nb_requestors = 0, slave_map_cnt = 0;1349 const enum dma_slave_buswidth widths =1350 DMA_SLAVE_BUSWIDTH_1_BYTE | DMA_SLAVE_BUSWIDTH_2_BYTES |1351 DMA_SLAVE_BUSWIDTH_4_BYTES;1352 1353 pdev = devm_kzalloc(&op->dev, sizeof(*pdev), GFP_KERNEL);1354 if (!pdev)1355 return -ENOMEM;1356 1357 spin_lock_init(&pdev->phy_lock);1358 1359 pdev->base = devm_platform_ioremap_resource(op, 0);1360 if (IS_ERR(pdev->base))1361 return PTR_ERR(pdev->base);1362 1363 if (op->dev.of_node) {1364 /* Parse new and deprecated dma-channels properties */1365 if (of_property_read_u32(op->dev.of_node, "dma-channels",1366 &dma_channels))1367 of_property_read_u32(op->dev.of_node, "#dma-channels",1368 &dma_channels);1369 /* Parse new and deprecated dma-requests properties */1370 ret = of_property_read_u32(op->dev.of_node, "dma-requests",1371 &nb_requestors);1372 if (ret)1373 ret = of_property_read_u32(op->dev.of_node, "#dma-requests",1374 &nb_requestors);1375 if (ret) {1376 dev_warn(pdev->slave.dev,1377 "#dma-requests set to default 32 as missing in OF: %d",1378 ret);1379 nb_requestors = 32;1380 }1381 } else if (pdata && pdata->dma_channels) {1382 dma_channels = pdata->dma_channels;1383 nb_requestors = pdata->nb_requestors;1384 slave_map = pdata->slave_map;1385 slave_map_cnt = pdata->slave_map_cnt;1386 } else {1387 dma_channels = 32; /* default 32 channel */1388 }1389 1390 dma_cap_set(DMA_SLAVE, pdev->slave.cap_mask);1391 dma_cap_set(DMA_MEMCPY, pdev->slave.cap_mask);1392 dma_cap_set(DMA_CYCLIC, pdev->slave.cap_mask);1393 dma_cap_set(DMA_PRIVATE, pdev->slave.cap_mask);1394 pdev->slave.device_prep_dma_memcpy = pxad_prep_memcpy;1395 pdev->slave.device_prep_slave_sg = pxad_prep_slave_sg;1396 pdev->slave.device_prep_dma_cyclic = pxad_prep_dma_cyclic;1397 pdev->slave.filter.map = slave_map;1398 pdev->slave.filter.mapcnt = slave_map_cnt;1399 pdev->slave.filter.fn = pxad_filter_fn;1400 1401 pdev->slave.copy_align = PDMA_ALIGNMENT;1402 pdev->slave.src_addr_widths = widths;1403 pdev->slave.dst_addr_widths = widths;1404 pdev->slave.directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);1405 pdev->slave.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;1406 pdev->slave.descriptor_reuse = true;1407 1408 pdev->slave.dev = &op->dev;1409 ret = pxad_init_dmadev(op, pdev, dma_channels, nb_requestors);1410 if (ret) {1411 dev_err(pdev->slave.dev, "unable to register\n");1412 return ret;1413 }1414 1415 if (op->dev.of_node) {1416 /* Device-tree DMA controller registration */1417 ret = of_dma_controller_register(op->dev.of_node,1418 pxad_dma_xlate, pdev);1419 if (ret < 0) {1420 dev_err(pdev->slave.dev,1421 "of_dma_controller_register failed\n");1422 return ret;1423 }1424 }1425 1426 platform_set_drvdata(op, pdev);1427 pxad_init_debugfs(pdev);1428 dev_info(pdev->slave.dev, "initialized %d channels on %d requestors\n",1429 dma_channels, nb_requestors);1430 return 0;1431}1432 1433static const struct platform_device_id pxad_id_table[] = {1434 { "pxa-dma", },1435 { },1436};1437 1438static struct platform_driver pxad_driver = {1439 .driver = {1440 .name = "pxa-dma",1441 .of_match_table = pxad_dt_ids,1442 },1443 .id_table = pxad_id_table,1444 .probe = pxad_probe,1445 .remove_new = pxad_remove,1446};1447 1448static bool pxad_filter_fn(struct dma_chan *chan, void *param)1449{1450 struct pxad_chan *c = to_pxad_chan(chan);1451 struct pxad_param *p = param;1452 1453 if (chan->device->dev->driver != &pxad_driver.driver)1454 return false;1455 1456 c->drcmr = p->drcmr;1457 c->prio = p->prio;1458 1459 return true;1460}1461 1462module_platform_driver(pxad_driver);1463 1464MODULE_DESCRIPTION("Marvell PXA Peripheral DMA Driver");1465MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");1466MODULE_LICENSE("GPL v2");1467