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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (C) ST-Ericsson SA 2007-20104 * Author: Per Friden <per.friden@stericsson.com> for ST-Ericsson SA5 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson SA6 */7#ifndef STE_DMA40_LL_H8#define STE_DMA40_LL_H9 10#define D40_DREG_PCBASE 0x40011#define D40_DREG_PCDELTA (8 * 4)12#define D40_LLI_ALIGN 16 /* LLI alignment must be 16 bytes. */13 14#define D40_LCPA_CHAN_SIZE 3215#define D40_LCPA_CHAN_DST_DELTA 1616 17#define D40_TYPE_TO_GROUP(type) (type / 16)18#define D40_TYPE_TO_EVENT(type) (type % 16)19#define D40_GROUP_SIZE 820#define D40_PHYS_TO_GROUP(phys) ((phys & (D40_GROUP_SIZE - 1)) / 2)21 22/* Most bits of the CFG register are the same in log as in phy mode */23#define D40_SREG_CFG_MST_POS 1524#define D40_SREG_CFG_TIM_POS 1425#define D40_SREG_CFG_EIM_POS 1326#define D40_SREG_CFG_LOG_INCR_POS 1227#define D40_SREG_CFG_PHY_PEN_POS 1228#define D40_SREG_CFG_PSIZE_POS 1029#define D40_SREG_CFG_ESIZE_POS 830#define D40_SREG_CFG_PRI_POS 731#define D40_SREG_CFG_LBE_POS 632#define D40_SREG_CFG_LOG_GIM_POS 533#define D40_SREG_CFG_LOG_MFU_POS 434#define D40_SREG_CFG_PHY_TM_POS 435#define D40_SREG_CFG_PHY_EVTL_POS 036 37 38/* Standard channel parameters - basic mode (element register) */39#define D40_SREG_ELEM_PHY_ECNT_POS 1640#define D40_SREG_ELEM_PHY_EIDX_POS 041 42#define D40_SREG_ELEM_PHY_ECNT_MASK (0xFFFF << D40_SREG_ELEM_PHY_ECNT_POS)43 44/* Standard channel parameters - basic mode (Link register) */45#define D40_SREG_LNK_PHY_TCP_POS 046#define D40_SREG_LNK_PHY_LMP_POS 147#define D40_SREG_LNK_PHY_PRE_POS 248/*49 * Source destination link address. Contains the50 * 29-bit byte word aligned address of the reload area.51 */52#define D40_SREG_LNK_PHYS_LNK_MASK 0xFFFFFFF8UL53 54/* Standard basic channel logical mode */55 56/* Element register */57#define D40_SREG_ELEM_LOG_ECNT_POS 1658#define D40_SREG_ELEM_LOG_LIDX_POS 859#define D40_SREG_ELEM_LOG_LOS_POS 160#define D40_SREG_ELEM_LOG_TCP_POS 061 62#define D40_SREG_ELEM_LOG_LIDX_MASK (0xFF << D40_SREG_ELEM_LOG_LIDX_POS)63 64/* Link register */65#define D40_EVENTLINE_POS(i) (2 * i)66#define D40_EVENTLINE_MASK(i) (0x3 << D40_EVENTLINE_POS(i))67 68/* Standard basic channel logical params in memory */69 70/* LCSP0 */71#define D40_MEM_LCSP0_ECNT_POS 1672#define D40_MEM_LCSP0_SPTR_POS 073 74#define D40_MEM_LCSP0_ECNT_MASK (0xFFFF << D40_MEM_LCSP0_ECNT_POS)75#define D40_MEM_LCSP0_SPTR_MASK (0xFFFF << D40_MEM_LCSP0_SPTR_POS)76 77/* LCSP1 */78#define D40_MEM_LCSP1_SPTR_POS 1679#define D40_MEM_LCSP1_SCFG_MST_POS 1580#define D40_MEM_LCSP1_SCFG_TIM_POS 1481#define D40_MEM_LCSP1_SCFG_EIM_POS 1382#define D40_MEM_LCSP1_SCFG_INCR_POS 1283#define D40_MEM_LCSP1_SCFG_PSIZE_POS 1084#define D40_MEM_LCSP1_SCFG_ESIZE_POS 885#define D40_MEM_LCSP1_SLOS_POS 186#define D40_MEM_LCSP1_STCP_POS 087 88#define D40_MEM_LCSP1_SPTR_MASK (0xFFFF << D40_MEM_LCSP1_SPTR_POS)89#define D40_MEM_LCSP1_SCFG_TIM_MASK (0x1 << D40_MEM_LCSP1_SCFG_TIM_POS)90#define D40_MEM_LCSP1_SCFG_INCR_MASK (0x1 << D40_MEM_LCSP1_SCFG_INCR_POS)91#define D40_MEM_LCSP1_SCFG_PSIZE_MASK (0x3 << D40_MEM_LCSP1_SCFG_PSIZE_POS)92#define D40_MEM_LCSP1_SLOS_MASK (0x7F << D40_MEM_LCSP1_SLOS_POS)93#define D40_MEM_LCSP1_STCP_MASK (0x1 << D40_MEM_LCSP1_STCP_POS)94 95/* LCSP2 */96#define D40_MEM_LCSP2_ECNT_POS 1697 98#define D40_MEM_LCSP2_ECNT_MASK (0xFFFF << D40_MEM_LCSP2_ECNT_POS)99 100/* LCSP3 */101#define D40_MEM_LCSP3_DCFG_MST_POS 15102#define D40_MEM_LCSP3_DCFG_TIM_POS 14103#define D40_MEM_LCSP3_DCFG_EIM_POS 13104#define D40_MEM_LCSP3_DCFG_INCR_POS 12105#define D40_MEM_LCSP3_DCFG_PSIZE_POS 10106#define D40_MEM_LCSP3_DCFG_ESIZE_POS 8107#define D40_MEM_LCSP3_DLOS_POS 1108#define D40_MEM_LCSP3_DTCP_POS 0109 110#define D40_MEM_LCSP3_DLOS_MASK (0x7F << D40_MEM_LCSP3_DLOS_POS)111#define D40_MEM_LCSP3_DTCP_MASK (0x1 << D40_MEM_LCSP3_DTCP_POS)112 113 114/* Standard channel parameter register offsets */115#define D40_CHAN_REG_SSCFG 0x00116#define D40_CHAN_REG_SSELT 0x04117#define D40_CHAN_REG_SSPTR 0x08118#define D40_CHAN_REG_SSLNK 0x0C119#define D40_CHAN_REG_SDCFG 0x10120#define D40_CHAN_REG_SDELT 0x14121#define D40_CHAN_REG_SDPTR 0x18122#define D40_CHAN_REG_SDLNK 0x1C123 124/* DMA Register Offsets */125#define D40_DREG_GCC 0x000126#define D40_DREG_GCC_ENA 0x1127/* This assumes that there are only 4 event groups */128#define D40_DREG_GCC_ENABLE_ALL 0x3ff01129#define D40_DREG_GCC_EVTGRP_POS 8130#define D40_DREG_GCC_SRC 0131#define D40_DREG_GCC_DST 1132#define D40_DREG_GCC_EVTGRP_ENA(x, y) \133 (1 << (D40_DREG_GCC_EVTGRP_POS + 2 * x + y))134 135#define D40_DREG_PRTYP 0x004136#define D40_DREG_PRSME 0x008137#define D40_DREG_PRSMO 0x00C138#define D40_DREG_PRMSE 0x010139#define D40_DREG_PRMSO 0x014140#define D40_DREG_PRMOE 0x018141#define D40_DREG_PRMOO 0x01C142#define D40_DREG_PRMO_PCHAN_BASIC 0x1143#define D40_DREG_PRMO_PCHAN_MODULO 0x2144#define D40_DREG_PRMO_PCHAN_DOUBLE_DST 0x3145#define D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG 0x1146#define D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY 0x2147#define D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG 0x3148 149#define D40_DREG_LCPA 0x020150#define D40_DREG_LCLA 0x024151 152#define D40_DREG_SSEG1 0x030153#define D40_DREG_SSEG2 0x034154#define D40_DREG_SSEG3 0x038155#define D40_DREG_SSEG4 0x03C156 157#define D40_DREG_SCEG1 0x040158#define D40_DREG_SCEG2 0x044159#define D40_DREG_SCEG3 0x048160#define D40_DREG_SCEG4 0x04C161 162#define D40_DREG_ACTIVE 0x050163#define D40_DREG_ACTIVO 0x054164#define D40_DREG_CIDMOD 0x058165#define D40_DREG_TCIDV 0x05C166#define D40_DREG_PCMIS 0x060167#define D40_DREG_PCICR 0x064168#define D40_DREG_PCTIS 0x068169#define D40_DREG_PCEIS 0x06C170 171#define D40_DREG_SPCMIS 0x070172#define D40_DREG_SPCICR 0x074173#define D40_DREG_SPCTIS 0x078174#define D40_DREG_SPCEIS 0x07C175 176#define D40_DREG_LCMIS0 0x080177#define D40_DREG_LCMIS1 0x084178#define D40_DREG_LCMIS2 0x088179#define D40_DREG_LCMIS3 0x08C180#define D40_DREG_LCICR0 0x090181#define D40_DREG_LCICR1 0x094182#define D40_DREG_LCICR2 0x098183#define D40_DREG_LCICR3 0x09C184#define D40_DREG_LCTIS0 0x0A0185#define D40_DREG_LCTIS1 0x0A4186#define D40_DREG_LCTIS2 0x0A8187#define D40_DREG_LCTIS3 0x0AC188#define D40_DREG_LCEIS0 0x0B0189#define D40_DREG_LCEIS1 0x0B4190#define D40_DREG_LCEIS2 0x0B8191#define D40_DREG_LCEIS3 0x0BC192 193#define D40_DREG_SLCMIS1 0x0C0194#define D40_DREG_SLCMIS2 0x0C4195#define D40_DREG_SLCMIS3 0x0C8196#define D40_DREG_SLCMIS4 0x0CC197 198#define D40_DREG_SLCICR1 0x0D0199#define D40_DREG_SLCICR2 0x0D4200#define D40_DREG_SLCICR3 0x0D8201#define D40_DREG_SLCICR4 0x0DC202 203#define D40_DREG_SLCTIS1 0x0E0204#define D40_DREG_SLCTIS2 0x0E4205#define D40_DREG_SLCTIS3 0x0E8206#define D40_DREG_SLCTIS4 0x0EC207 208#define D40_DREG_SLCEIS1 0x0F0209#define D40_DREG_SLCEIS2 0x0F4210#define D40_DREG_SLCEIS3 0x0F8211#define D40_DREG_SLCEIS4 0x0FC212 213#define D40_DREG_FSESS1 0x100214#define D40_DREG_FSESS2 0x104215 216#define D40_DREG_FSEBS1 0x108217#define D40_DREG_FSEBS2 0x10C218 219#define D40_DREG_PSEG1 0x110220#define D40_DREG_PSEG2 0x114221#define D40_DREG_PSEG3 0x118222#define D40_DREG_PSEG4 0x11C223#define D40_DREG_PCEG1 0x120224#define D40_DREG_PCEG2 0x124225#define D40_DREG_PCEG3 0x128226#define D40_DREG_PCEG4 0x12C227#define D40_DREG_RSEG1 0x130228#define D40_DREG_RSEG2 0x134229#define D40_DREG_RSEG3 0x138230#define D40_DREG_RSEG4 0x13C231#define D40_DREG_RCEG1 0x140232#define D40_DREG_RCEG2 0x144233#define D40_DREG_RCEG3 0x148234#define D40_DREG_RCEG4 0x14C235 236#define D40_DREG_PREFOT 0x15C237#define D40_DREG_EXTCFG 0x160238 239#define D40_DREG_CPSEG1 0x200240#define D40_DREG_CPSEG2 0x204241#define D40_DREG_CPSEG3 0x208242#define D40_DREG_CPSEG4 0x20C243#define D40_DREG_CPSEG5 0x210244 245#define D40_DREG_CPCEG1 0x220246#define D40_DREG_CPCEG2 0x224247#define D40_DREG_CPCEG3 0x228248#define D40_DREG_CPCEG4 0x22C249#define D40_DREG_CPCEG5 0x230250 251#define D40_DREG_CRSEG1 0x240252#define D40_DREG_CRSEG2 0x244253#define D40_DREG_CRSEG3 0x248254#define D40_DREG_CRSEG4 0x24C255#define D40_DREG_CRSEG5 0x250256 257#define D40_DREG_CRCEG1 0x260258#define D40_DREG_CRCEG2 0x264259#define D40_DREG_CRCEG3 0x268260#define D40_DREG_CRCEG4 0x26C261#define D40_DREG_CRCEG5 0x270262 263#define D40_DREG_CFSESS1 0x280264#define D40_DREG_CFSESS2 0x284265#define D40_DREG_CFSESS3 0x288266 267#define D40_DREG_CFSEBS1 0x290268#define D40_DREG_CFSEBS2 0x294269#define D40_DREG_CFSEBS3 0x298270 271#define D40_DREG_CLCMIS1 0x300272#define D40_DREG_CLCMIS2 0x304273#define D40_DREG_CLCMIS3 0x308274#define D40_DREG_CLCMIS4 0x30C275#define D40_DREG_CLCMIS5 0x310276 277#define D40_DREG_CLCICR1 0x320278#define D40_DREG_CLCICR2 0x324279#define D40_DREG_CLCICR3 0x328280#define D40_DREG_CLCICR4 0x32C281#define D40_DREG_CLCICR5 0x330282 283#define D40_DREG_CLCTIS1 0x340284#define D40_DREG_CLCTIS2 0x344285#define D40_DREG_CLCTIS3 0x348286#define D40_DREG_CLCTIS4 0x34C287#define D40_DREG_CLCTIS5 0x350288 289#define D40_DREG_CLCEIS1 0x360290#define D40_DREG_CLCEIS2 0x364291#define D40_DREG_CLCEIS3 0x368292#define D40_DREG_CLCEIS4 0x36C293#define D40_DREG_CLCEIS5 0x370294 295#define D40_DREG_CPCMIS 0x380296#define D40_DREG_CPCICR 0x384297#define D40_DREG_CPCTIS 0x388298#define D40_DREG_CPCEIS 0x38C299 300#define D40_DREG_SCCIDA1 0xE80301#define D40_DREG_SCCIDA2 0xE90302#define D40_DREG_SCCIDA3 0xEA0303#define D40_DREG_SCCIDA4 0xEB0304#define D40_DREG_SCCIDA5 0xEC0305 306#define D40_DREG_SCCIDB1 0xE84307#define D40_DREG_SCCIDB2 0xE94308#define D40_DREG_SCCIDB3 0xEA4309#define D40_DREG_SCCIDB4 0xEB4310#define D40_DREG_SCCIDB5 0xEC4311 312#define D40_DREG_PRSCCIDA 0xF80313#define D40_DREG_PRSCCIDB 0xF84314 315#define D40_DREG_STFU 0xFC8316#define D40_DREG_ICFG 0xFCC317#define D40_DREG_PERIPHID0 0xFE0318#define D40_DREG_PERIPHID1 0xFE4319#define D40_DREG_PERIPHID2 0xFE8320#define D40_DREG_PERIPHID3 0xFEC321#define D40_DREG_CELLID0 0xFF0322#define D40_DREG_CELLID1 0xFF4323#define D40_DREG_CELLID2 0xFF8324#define D40_DREG_CELLID3 0xFFC325 326/* LLI related structures */327 328/**329 * struct d40_phy_lli - The basic configuration register for each physical330 * channel.331 *332 * @reg_cfg: The configuration register.333 * @reg_elt: The element register.334 * @reg_ptr: The pointer register.335 * @reg_lnk: The link register.336 *337 * These registers are set up for both physical and logical transfers338 * Note that the bit in each register means differently in logical and339 * physical(standard) mode.340 *341 * This struct must be 16 bytes aligned, and only contain physical registers342 * since it will be directly accessed by the DMA.343 */344struct d40_phy_lli {345 u32 reg_cfg;346 u32 reg_elt;347 u32 reg_ptr;348 u32 reg_lnk;349};350 351/**352 * struct d40_phy_lli_bidir - struct for a transfer.353 *354 * @src: Register settings for src channel.355 * @dst: Register settings for dst channel.356 *357 * All DMA transfers have a source and a destination.358 */359 360struct d40_phy_lli_bidir {361 struct d40_phy_lli *src;362 struct d40_phy_lli *dst;363};364 365 366/**367 * struct d40_log_lli - logical lli configuration368 *369 * @lcsp02: Either maps to register lcsp0 if src or lcsp2 if dst.370 * @lcsp13: Either maps to register lcsp1 if src or lcsp3 if dst.371 *372 * This struct must be 8 bytes aligned since it will be accessed directly by373 * the DMA. Never add any none hw mapped registers to this struct.374 */375 376struct d40_log_lli {377 u32 lcsp02;378 u32 lcsp13;379};380 381/**382 * struct d40_log_lli_bidir - For both src and dst383 *384 * @src: pointer to src lli configuration.385 * @dst: pointer to dst lli configuration.386 *387 * You always have a src and a dst when doing DMA transfers.388 */389 390struct d40_log_lli_bidir {391 struct d40_log_lli *src;392 struct d40_log_lli *dst;393};394 395/**396 * struct d40_log_lli_full - LCPA layout397 *398 * @lcsp0: Logical Channel Standard Param 0 - Src.399 * @lcsp1: Logical Channel Standard Param 1 - Src.400 * @lcsp2: Logical Channel Standard Param 2 - Dst.401 * @lcsp3: Logical Channel Standard Param 3 - Dst.402 *403 * This struct maps to LCPA physical memory layout. Must map to404 * the hw.405 */406struct d40_log_lli_full {407 u32 lcsp0;408 u32 lcsp1;409 u32 lcsp2;410 u32 lcsp3;411};412 413/**414 * struct d40_def_lcsp - Default LCSP1 and LCSP3 settings415 *416 * @lcsp3: The default configuration for dst.417 * @lcsp1: The default configuration for src.418 */419struct d40_def_lcsp {420 u32 lcsp3;421 u32 lcsp1;422};423 424/* Physical channels */425 426enum d40_lli_flags {427 LLI_ADDR_INC = 1 << 0,428 LLI_TERM_INT = 1 << 1,429 LLI_CYCLIC = 1 << 2,430 LLI_LAST_LINK = 1 << 3,431};432 433void d40_phy_cfg(struct stedma40_chan_cfg *cfg,434 u32 *src_cfg,435 u32 *dst_cfg);436 437void d40_log_cfg(struct stedma40_chan_cfg *cfg,438 u32 *lcsp1,439 u32 *lcsp2);440 441int d40_phy_sg_to_lli(struct scatterlist *sg,442 int sg_len,443 dma_addr_t target,444 struct d40_phy_lli *lli,445 dma_addr_t lli_phys,446 u32 reg_cfg,447 struct stedma40_half_channel_info *info,448 struct stedma40_half_channel_info *otherinfo,449 unsigned long flags);450 451/* Logical channels */452 453int d40_log_sg_to_lli(struct scatterlist *sg,454 int sg_len,455 dma_addr_t dev_addr,456 struct d40_log_lli *lli_sg,457 u32 lcsp13, /* src or dst*/458 u32 data_width1, u32 data_width2);459 460void d40_log_lli_lcpa_write(struct d40_log_lli_full *lcpa,461 struct d40_log_lli *lli_dst,462 struct d40_log_lli *lli_src,463 int next, unsigned int flags);464 465void d40_log_lli_lcla_write(struct d40_log_lli *lcla,466 struct d40_log_lli *lli_dst,467 struct d40_log_lli *lli_src,468 int next, unsigned int flags);469 470#endif /* STE_DMA40_LLI_H */471