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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright (C) 2017-2020 Xilinx, Inc. All rights reserved.4 * Copyright (C) 2022, Advanced Micro Devices, Inc.5 */6 7#ifndef __DMA_XDMA_REGS_H8#define __DMA_XDMA_REGS_H9 10/* The length of register space exposed to host */11#define XDMA_REG_SPACE_LEN 6553612 13/*14 * maximum number of DMA channels for each direction:15 * Host to Card (H2C) or Card to Host (C2H)16 */17#define XDMA_MAX_CHANNELS 418 19/*20 * macros to define the number of descriptor blocks can be used in one21 * DMA transfer request.22 * the DMA engine uses a linked list of descriptor blocks that specify the23 * source, destination, and length of the DMA transfers.24 */25#define XDMA_DESC_BLOCK_NUM BIT(7)26#define XDMA_DESC_BLOCK_MASK (XDMA_DESC_BLOCK_NUM - 1)27 28/* descriptor definitions */29#define XDMA_DESC_ADJACENT 3230#define XDMA_DESC_ADJACENT_MASK (XDMA_DESC_ADJACENT - 1)31#define XDMA_DESC_ADJACENT_BITS GENMASK(13, 8)32#define XDMA_DESC_MAGIC 0xad4bUL33#define XDMA_DESC_MAGIC_BITS GENMASK(31, 16)34#define XDMA_DESC_FLAGS_BITS GENMASK(7, 0)35#define XDMA_DESC_STOPPED BIT(0)36#define XDMA_DESC_COMPLETED BIT(1)37#define XDMA_DESC_BLEN_BITS 2838#define XDMA_DESC_BLEN_MAX (BIT(XDMA_DESC_BLEN_BITS) - PAGE_SIZE)39 40/* macros to construct the descriptor control word */41#define XDMA_DESC_CONTROL(adjacent, flag) \42 (FIELD_PREP(XDMA_DESC_MAGIC_BITS, XDMA_DESC_MAGIC) | \43 FIELD_PREP(XDMA_DESC_ADJACENT_BITS, (adjacent) - 1) | \44 FIELD_PREP(XDMA_DESC_FLAGS_BITS, (flag)))45#define XDMA_DESC_CONTROL_LAST \46 XDMA_DESC_CONTROL(1, XDMA_DESC_STOPPED | XDMA_DESC_COMPLETED)47#define XDMA_DESC_CONTROL_CYCLIC \48 XDMA_DESC_CONTROL(1, XDMA_DESC_COMPLETED)49 50/*51 * Descriptor for a single contiguous memory block transfer.52 *53 * Multiple descriptors are linked by means of the next pointer. An additional54 * extra adjacent number gives the amount of extra contiguous descriptors.55 *56 * The descriptors are in root complex memory, and the bytes in the 32-bit57 * words must be in little-endian byte ordering.58 */59struct xdma_hw_desc {60 __le32 control;61 __le32 bytes;62 __le64 src_addr;63 __le64 dst_addr;64 __le64 next_desc;65};66 67#define XDMA_DESC_SIZE sizeof(struct xdma_hw_desc)68#define XDMA_DESC_BLOCK_SIZE (XDMA_DESC_SIZE * XDMA_DESC_ADJACENT)69#define XDMA_DESC_BLOCK_ALIGN 3270#define XDMA_DESC_BLOCK_BOUNDARY 409671 72/*73 * Channel registers74 */75#define XDMA_CHAN_IDENTIFIER 0x076#define XDMA_CHAN_CONTROL 0x477#define XDMA_CHAN_CONTROL_W1S 0x878#define XDMA_CHAN_CONTROL_W1C 0xc79#define XDMA_CHAN_STATUS 0x4080#define XDMA_CHAN_STATUS_RC 0x4481#define XDMA_CHAN_COMPLETED_DESC 0x4882#define XDMA_CHAN_ALIGNMENTS 0x4c83#define XDMA_CHAN_INTR_ENABLE 0x9084#define XDMA_CHAN_INTR_ENABLE_W1S 0x9485#define XDMA_CHAN_INTR_ENABLE_W1C 0x9c86 87#define XDMA_CHAN_STRIDE 0x10088#define XDMA_CHAN_H2C_OFFSET 0x089#define XDMA_CHAN_C2H_OFFSET 0x100090#define XDMA_CHAN_H2C_TARGET 0x091#define XDMA_CHAN_C2H_TARGET 0x192 93/* macro to check if channel is available */94#define XDMA_CHAN_MAGIC 0x1fc095#define XDMA_CHAN_CHECK_TARGET(id, target) \96 (((u32)(id) >> 16) == XDMA_CHAN_MAGIC + (target))97 98/* bits of the channel control register */99#define CHAN_CTRL_RUN_STOP BIT(0)100#define CHAN_CTRL_IE_DESC_STOPPED BIT(1)101#define CHAN_CTRL_IE_DESC_COMPLETED BIT(2)102#define CHAN_CTRL_IE_DESC_ALIGN_MISMATCH BIT(3)103#define CHAN_CTRL_IE_MAGIC_STOPPED BIT(4)104#define CHAN_CTRL_IE_IDLE_STOPPED BIT(6)105#define CHAN_CTRL_IE_READ_ERROR GENMASK(13, 9)106#define CHAN_CTRL_IE_WRITE_ERROR GENMASK(18, 14)107#define CHAN_CTRL_IE_DESC_ERROR GENMASK(23, 19)108#define CHAN_CTRL_NON_INCR_ADDR BIT(25)109#define CHAN_CTRL_POLL_MODE_WB BIT(26)110 111#define CHAN_CTRL_START (CHAN_CTRL_RUN_STOP | \112 CHAN_CTRL_IE_DESC_STOPPED | \113 CHAN_CTRL_IE_DESC_COMPLETED | \114 CHAN_CTRL_IE_DESC_ALIGN_MISMATCH | \115 CHAN_CTRL_IE_MAGIC_STOPPED | \116 CHAN_CTRL_IE_READ_ERROR | \117 CHAN_CTRL_IE_WRITE_ERROR | \118 CHAN_CTRL_IE_DESC_ERROR)119 120/* bits of the channel status register */121#define XDMA_CHAN_STATUS_BUSY BIT(0)122 123#define XDMA_CHAN_STATUS_MASK CHAN_CTRL_START124 125#define XDMA_CHAN_ERROR_MASK (CHAN_CTRL_IE_DESC_ALIGN_MISMATCH | \126 CHAN_CTRL_IE_MAGIC_STOPPED | \127 CHAN_CTRL_IE_READ_ERROR | \128 CHAN_CTRL_IE_WRITE_ERROR | \129 CHAN_CTRL_IE_DESC_ERROR)130 131/* bits of the channel interrupt enable mask */132#define CHAN_IM_DESC_ERROR BIT(19)133#define CHAN_IM_READ_ERROR BIT(9)134#define CHAN_IM_IDLE_STOPPED BIT(6)135#define CHAN_IM_MAGIC_STOPPED BIT(4)136#define CHAN_IM_DESC_COMPLETED BIT(2)137#define CHAN_IM_DESC_STOPPED BIT(1)138 139#define CHAN_IM_ALL (CHAN_IM_DESC_ERROR | CHAN_IM_READ_ERROR | \140 CHAN_IM_IDLE_STOPPED | CHAN_IM_MAGIC_STOPPED | \141 CHAN_IM_DESC_COMPLETED | CHAN_IM_DESC_STOPPED)142 143/*144 * Channel SGDMA registers145 */146#define XDMA_SGDMA_IDENTIFIER 0x4000147#define XDMA_SGDMA_DESC_LO 0x4080148#define XDMA_SGDMA_DESC_HI 0x4084149#define XDMA_SGDMA_DESC_ADJ 0x4088150#define XDMA_SGDMA_DESC_CREDIT 0x408c151 152/*153 * interrupt registers154 */155#define XDMA_IRQ_IDENTIFIER 0x2000156#define XDMA_IRQ_USER_INT_EN 0x2004157#define XDMA_IRQ_USER_INT_EN_W1S 0x2008158#define XDMA_IRQ_USER_INT_EN_W1C 0x200c159#define XDMA_IRQ_CHAN_INT_EN 0x2010160#define XDMA_IRQ_CHAN_INT_EN_W1S 0x2014161#define XDMA_IRQ_CHAN_INT_EN_W1C 0x2018162#define XDMA_IRQ_USER_INT_REQ 0x2040163#define XDMA_IRQ_CHAN_INT_REQ 0x2044164#define XDMA_IRQ_USER_INT_PEND 0x2048165#define XDMA_IRQ_CHAN_INT_PEND 0x204c166#define XDMA_IRQ_USER_VEC_NUM 0x2080167#define XDMA_IRQ_CHAN_VEC_NUM 0x20a0168 169#define XDMA_IRQ_VEC_SHIFT 8170 171#endif /* __DMA_XDMA_REGS_H */172