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1#2# EDAC Kconfig3# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com4# Licensed and distributed under the GPL5 6config EDAC_ATOMIC_SCRUB7 bool8 9config EDAC_SUPPORT10 bool11 12menuconfig EDAC13 tristate "EDAC (Error Detection And Correction) reporting"14 depends on HAS_IOMEM && EDAC_SUPPORT && RAS15 help16 EDAC is a subsystem along with hardware-specific drivers designed to17 report hardware errors. These are low-level errors that are reported18 in the CPU or supporting chipset or other subsystems:19 memory errors, cache errors, PCI errors, thermal throttling, etc..20 If unsure, select 'Y'.21 22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.23 24if EDAC25 26config EDAC_LEGACY_SYSFS27 bool "EDAC legacy sysfs"28 default y29 help30 Enable the compatibility sysfs nodes.31 Use 'Y' if your edac utilities aren't ported to work with the newer32 structures.33 34config EDAC_DEBUG35 bool "Debugging"36 select DEBUG_FS37 help38 This turns on debugging information for the entire EDAC subsystem.39 You do so by inserting edac_module with "edac_debug_level=x." Valid40 levels are 0-4 (from low to high) and by default it is set to 2.41 Usually you should select 'N' here.42 43config EDAC_DECODE_MCE44 tristate "Decode MCEs in human-readable form (only on AMD for now)"45 depends on CPU_SUP_AMD && X86_MCE_AMD46 default y47 help48 Enable this option if you want to decode Machine Check Exceptions49 occurring on your machine in human-readable form.50 51 You should definitely say Y here in case you want to decode MCEs52 which occur really early upon boot, before the module infrastructure53 has been initialized.54 55config EDAC_GHES56 tristate "Output ACPI APEI/GHES BIOS detected errors via EDAC"57 depends on ACPI_APEI_GHES58 select UEFI_CPER59 help60 Not all machines support hardware-driven error report. Some of those61 provide a BIOS-driven error report mechanism via ACPI, using the62 APEI/GHES driver. By enabling this option, the error reports provided63 by GHES are sent to userspace via the EDAC API.64 65 When this option is enabled, it will disable the hardware-driven66 mechanisms, if a GHES BIOS is detected, entering into the67 "Firmware First" mode.68 69 It should be noticed that keeping both GHES and a hardware-driven70 error mechanism won't work well, as BIOS will race with OS, while71 reading the error registers. So, if you want to not use "Firmware72 first" GHES error mechanism, you should disable GHES either at73 compilation time or by passing "ghes.disable=1" Kernel parameter74 at boot time.75 76 In doubt, say 'Y'.77 78config EDAC_AMD6479 tristate "AMD64 (Opteron, Athlon64)"80 depends on AMD_NB && EDAC_DECODE_MCE81 imply AMD_ATL82 help83 Support for error detection and correction of DRAM ECC errors on84 the AMD64 families (>= K8) of memory controllers.85 86 When EDAC_DEBUG is enabled, hardware error injection facilities87 through sysfs are available:88 89 AMD CPUs up to and excluding family 0x17 provide for Memory90 Error Injection into the ECC detection circuits. The amd64_edac91 module allows the operator/user to inject Uncorrectable and92 Correctable errors into DRAM.93 94 When enabled, in each of the respective memory controller directories95 (/sys/devices/system/edac/mc/mcX), there are 3 input files:96 97 - inject_section (0..3, 16-byte section of 64-byte cacheline),98 - inject_word (0..8, 16-bit word of 16-byte section),99 - inject_ecc_vector (hex ecc vector: select bits of inject word)100 101 In addition, there are two control files, inject_read and inject_write,102 which trigger the DRAM ECC Read and Write respectively.103 104config EDAC_AL_MC105 tristate "Amazon's Annapurna Lab Memory Controller"106 depends on (ARCH_ALPINE || COMPILE_TEST)107 help108 Support for error detection and correction for Amazon's Annapurna109 Labs Alpine chips which allow 1 bit correction and 2 bits detection.110 111config EDAC_AMD76X112 tristate "AMD 76x (760, 762, 768)"113 depends on PCI && X86_32114 help115 Support for error detection and correction on the AMD 76x116 series of chipsets used with the Athlon processor.117 118config EDAC_E7XXX119 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"120 depends on PCI && X86_32121 help122 Support for error detection and correction on the Intel123 E7205, E7500, E7501 and E7505 server chipsets.124 125config EDAC_E752X126 tristate "Intel e752x (e7520, e7525, e7320) and 3100"127 depends on PCI && X86128 help129 Support for error detection and correction on the Intel130 E7520, E7525, E7320 server chipsets.131 132config EDAC_I82443BXGX133 tristate "Intel 82443BX/GX (440BX/GX)"134 depends on PCI && X86_32135 depends on BROKEN136 help137 Support for error detection and correction on the Intel138 82443BX/GX memory controllers (440BX/GX chipsets).139 140config EDAC_I82875P141 tristate "Intel 82875p (D82875P, E7210)"142 depends on PCI && X86_32143 help144 Support for error detection and correction on the Intel145 DP82785P and E7210 server chipsets.146 147config EDAC_I82975X148 tristate "Intel 82975x (D82975x)"149 depends on PCI && X86150 help151 Support for error detection and correction on the Intel152 DP82975x server chipsets.153 154config EDAC_I3000155 tristate "Intel 3000/3010"156 depends on PCI && X86157 help158 Support for error detection and correction on the Intel159 3000 and 3010 server chipsets.160 161config EDAC_I3200162 tristate "Intel 3200"163 depends on PCI && X86164 help165 Support for error detection and correction on the Intel166 3200 and 3210 server chipsets.167 168config EDAC_IE31200169 tristate "Intel e312xx"170 depends on PCI && X86171 help172 Support for error detection and correction on the Intel173 E3-1200 based DRAM controllers.174 175config EDAC_X38176 tristate "Intel X38"177 depends on PCI && X86178 help179 Support for error detection and correction on the Intel180 X38 server chipsets.181 182config EDAC_I5400183 tristate "Intel 5400 (Seaburg) chipsets"184 depends on PCI && X86185 help186 Support for error detection and correction the Intel187 i5400 MCH chipset (Seaburg).188 189config EDAC_I7CORE190 tristate "Intel i7 Core (Nehalem) processors"191 depends on PCI && X86 && X86_MCE_INTEL192 help193 Support for error detection and correction the Intel194 i7 Core (Nehalem) Integrated Memory Controller that exists on195 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx196 and Xeon 55xx processors.197 198config EDAC_I82860199 tristate "Intel 82860"200 depends on PCI && X86_32201 help202 Support for error detection and correction on the Intel203 82860 chipset.204 205config EDAC_R82600206 tristate "Radisys 82600 embedded chipset"207 depends on PCI && X86_32208 help209 Support for error detection and correction on the Radisys210 82600 embedded chipset.211 212config EDAC_I5000213 tristate "Intel Greencreek/Blackford chipset"214 depends on X86 && PCI215 depends on BROKEN216 help217 Support for error detection and correction the Intel218 Greekcreek/Blackford chipsets.219 220config EDAC_I5100221 tristate "Intel San Clemente MCH"222 depends on X86 && PCI223 help224 Support for error detection and correction the Intel225 San Clemente MCH.226 227config EDAC_I7300228 tristate "Intel Clarksboro MCH"229 depends on X86 && PCI230 help231 Support for error detection and correction the Intel232 Clarksboro MCH (Intel 7300 chipset).233 234config EDAC_SBRIDGE235 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"236 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG237 help238 Support for error detection and correction the Intel239 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.240 241config EDAC_SKX242 tristate "Intel Skylake server Integrated MC"243 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI244 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y245 select DMI246 select ACPI_ADXL247 help248 Support for error detection and correction the Intel249 Skylake server Integrated Memory Controllers. If your250 system has non-volatile DIMMs you should also manually251 select CONFIG_ACPI_NFIT.252 253config EDAC_I10NM254 tristate "Intel 10nm server Integrated MC"255 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI256 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y257 select DMI258 select ACPI_ADXL259 help260 Support for error detection and correction the Intel261 10nm server Integrated Memory Controllers. If your262 system has non-volatile DIMMs you should also manually263 select CONFIG_ACPI_NFIT.264 265config EDAC_PND2266 tristate "Intel Pondicherry2"267 depends on PCI && X86_64 && X86_MCE_INTEL268 select P2SB if X86269 help270 Support for error detection and correction on the Intel271 Pondicherry2 Integrated Memory Controller. This SoC IP is272 first used on the Apollo Lake platform and Denverton273 micro-server but may appear on others in the future.274 275config EDAC_IGEN6276 tristate "Intel client SoC Integrated MC"277 depends on PCI && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG278 depends on X86_64 && X86_MCE_INTEL279 help280 Support for error detection and correction on the Intel281 client SoC Integrated Memory Controller using In-Band ECC IP.282 This In-Band ECC is first used on the Elkhart Lake SoC but283 may appear on others in the future.284 285config EDAC_MPC85XX286 bool "Freescale MPC83xx / MPC85xx"287 depends on FSL_SOC && EDAC=y288 help289 Support for error detection and correction on the Freescale290 MPC8349, MPC8560, MPC8540, MPC8548, T4240291 292config EDAC_LAYERSCAPE293 tristate "Freescale Layerscape DDR"294 depends on ARCH_LAYERSCAPE || SOC_LS1021A295 help296 Support for error detection and correction on Freescale memory297 controllers on Layerscape SoCs.298 299config EDAC_PASEMI300 tristate "PA Semi PWRficient"301 depends on PPC_PASEMI && PCI302 help303 Support for error detection and correction on PA Semi304 PWRficient.305 306config EDAC_CELL307 tristate "Cell Broadband Engine memory controller"308 depends on PPC_CELL_COMMON309 help310 Support for error detection and correction on the311 Cell Broadband Engine internal memory controller312 on platform without a hypervisor313 314config EDAC_AMD8131315 tristate "AMD8131 HyperTransport PCI-X Tunnel"316 depends on PCI && PPC_MAPLE317 help318 Support for error detection and correction on the319 AMD8131 HyperTransport PCI-X Tunnel chip.320 Note, add more Kconfig dependency if it's adopted321 on some machine other than Maple.322 323config EDAC_AMD8111324 tristate "AMD8111 HyperTransport I/O Hub"325 depends on PCI && PPC_MAPLE326 help327 Support for error detection and correction on the328 AMD8111 HyperTransport I/O Hub chip.329 Note, add more Kconfig dependency if it's adopted330 on some machine other than Maple.331 332config EDAC_CPC925333 tristate "IBM CPC925 Memory Controller (PPC970FX)"334 depends on PPC64335 help336 Support for error detection and correction on the337 IBM CPC925 Bridge and Memory Controller, which is338 a companion chip to the PowerPC 970 family of339 processors.340 341config EDAC_HIGHBANK_MC342 tristate "Highbank Memory Controller"343 depends on ARCH_HIGHBANK344 help345 Support for error detection and correction on the346 Calxeda Highbank memory controller.347 348config EDAC_HIGHBANK_L2349 tristate "Highbank L2 Cache"350 depends on ARCH_HIGHBANK351 help352 Support for error detection and correction on the353 Calxeda Highbank memory controller.354 355config EDAC_OCTEON_PC356 tristate "Cavium Octeon Primary Caches"357 depends on CPU_CAVIUM_OCTEON358 help359 Support for error detection and correction on the primary caches of360 the cnMIPS cores of Cavium Octeon family SOCs.361 362config EDAC_OCTEON_L2C363 tristate "Cavium Octeon Secondary Caches (L2C)"364 depends on CAVIUM_OCTEON_SOC365 help366 Support for error detection and correction on the367 Cavium Octeon family of SOCs.368 369config EDAC_OCTEON_LMC370 tristate "Cavium Octeon DRAM Memory Controller (LMC)"371 depends on CAVIUM_OCTEON_SOC372 help373 Support for error detection and correction on the374 Cavium Octeon family of SOCs.375 376config EDAC_OCTEON_PCI377 tristate "Cavium Octeon PCI Controller"378 depends on PCI && CAVIUM_OCTEON_SOC379 help380 Support for error detection and correction on the381 Cavium Octeon family of SOCs.382 383config EDAC_THUNDERX384 tristate "Cavium ThunderX EDAC"385 depends on ARM64386 depends on PCI387 help388 Support for error detection and correction on the389 Cavium ThunderX memory controllers (LMC), Cache390 Coherent Processor Interconnect (CCPI) and L2 cache391 blocks (TAD, CBC, MCI).392 393config EDAC_ALTERA394 bool "Altera SOCFPGA ECC"395 depends on EDAC=y && ARCH_INTEL_SOCFPGA396 help397 Support for error detection and correction on the398 Altera SOCs. This is the global enable for the399 various Altera peripherals.400 401config EDAC_ALTERA_SDRAM402 bool "Altera SDRAM ECC"403 depends on EDAC_ALTERA=y404 help405 Support for error detection and correction on the406 Altera SDRAM Memory for Altera SoCs. Note that the407 preloader must initialize the SDRAM before loading408 the kernel.409 410config EDAC_ALTERA_L2C411 bool "Altera L2 Cache ECC"412 depends on EDAC_ALTERA=y && CACHE_L2X0413 help414 Support for error detection and correction on the415 Altera L2 cache Memory for Altera SoCs. This option416 requires L2 cache.417 418config EDAC_ALTERA_OCRAM419 bool "Altera On-Chip RAM ECC"420 depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR421 help422 Support for error detection and correction on the423 Altera On-Chip RAM Memory for Altera SoCs.424 425config EDAC_ALTERA_ETHERNET426 bool "Altera Ethernet FIFO ECC"427 depends on EDAC_ALTERA=y428 help429 Support for error detection and correction on the430 Altera Ethernet FIFO Memory for Altera SoCs.431 432config EDAC_ALTERA_NAND433 bool "Altera NAND FIFO ECC"434 depends on EDAC_ALTERA=y && MTD_NAND_DENALI435 help436 Support for error detection and correction on the437 Altera NAND FIFO Memory for Altera SoCs.438 439config EDAC_ALTERA_DMA440 bool "Altera DMA FIFO ECC"441 depends on EDAC_ALTERA=y && PL330_DMA=y442 help443 Support for error detection and correction on the444 Altera DMA FIFO Memory for Altera SoCs.445 446config EDAC_ALTERA_USB447 bool "Altera USB FIFO ECC"448 depends on EDAC_ALTERA=y && USB_DWC2449 help450 Support for error detection and correction on the451 Altera USB FIFO Memory for Altera SoCs.452 453config EDAC_ALTERA_QSPI454 bool "Altera QSPI FIFO ECC"455 depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI456 help457 Support for error detection and correction on the458 Altera QSPI FIFO Memory for Altera SoCs.459 460config EDAC_ALTERA_SDMMC461 bool "Altera SDMMC FIFO ECC"462 depends on EDAC_ALTERA=y && MMC_DW463 help464 Support for error detection and correction on the465 Altera SDMMC FIFO Memory for Altera SoCs.466 467config EDAC_SIFIVE468 bool "Sifive platform EDAC driver"469 depends on EDAC=y && SIFIVE_CCACHE470 help471 Support for error detection and correction on the SiFive SoCs.472 473config EDAC_ARMADA_XP474 bool "Marvell Armada XP DDR and L2 Cache ECC"475 depends on MACH_MVEBU_V7476 help477 Support for error correction and detection on the Marvell Aramada XP478 DDR RAM and L2 cache controllers.479 480config EDAC_SYNOPSYS481 tristate "Synopsys DDR Memory Controller"482 depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || ARCH_MXC483 help484 Support for error detection and correction on the Synopsys DDR485 memory controller.486 487config EDAC_XGENE488 tristate "APM X-Gene SoC"489 depends on (ARM64 || COMPILE_TEST)490 help491 Support for error detection and correction on the492 APM X-Gene family of SOCs.493 494config EDAC_TI495 tristate "Texas Instruments DDR3 ECC Controller"496 depends on ARCH_KEYSTONE || SOC_DRA7XX497 help498 Support for error detection and correction on the TI SoCs.499 500config EDAC_QCOM501 tristate "QCOM EDAC Controller"502 depends on ARCH_QCOM && QCOM_LLCC503 help504 Support for error detection and correction on the505 Qualcomm Technologies, Inc. SoCs.506 507 This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs).508 As of now, it supports error reporting for Last Level Cache Controller (LLCC)509 of Tag RAM and Data RAM.510 511 For debugging issues having to do with stability and overall system512 health, you should probably say 'Y' here.513 514config EDAC_ASPEED515 tristate "Aspeed AST BMC SoC"516 depends on ARCH_ASPEED517 help518 Support for error detection and correction on the Aspeed AST BMC SoC.519 520 First, ECC must be configured in the bootloader. Then, this driver521 will expose error counters via the EDAC kernel framework.522 523config EDAC_BLUEFIELD524 tristate "Mellanox BlueField Memory ECC"525 depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST)526 help527 Support for error detection and correction on the528 Mellanox BlueField SoCs.529 530config EDAC_DMC520531 tristate "ARM DMC-520 ECC"532 depends on ARM64533 help534 Support for error detection and correction on the535 SoCs with ARM DMC-520 DRAM controller.536 537config EDAC_ZYNQMP538 tristate "Xilinx ZynqMP OCM Controller"539 depends on ARCH_ZYNQMP || COMPILE_TEST540 help541 This driver supports error detection and correction for the542 Xilinx ZynqMP OCM (On Chip Memory) controller. It can also be543 built as a module. In that case it will be called zynqmp_edac.544 545config EDAC_NPCM546 tristate "Nuvoton NPCM DDR Memory Controller"547 depends on (ARCH_NPCM || COMPILE_TEST)548 help549 Support for error detection and correction on the Nuvoton NPCM DDR550 memory controller.551 552 The memory controller supports single bit error correction, double bit553 error detection (in-line ECC in which a section 1/8th of the memory554 device used to store data is used for ECC storage).555 556config EDAC_VERSAL557 tristate "Xilinx Versal DDR Memory Controller"558 depends on ARCH_ZYNQMP || COMPILE_TEST559 help560 Support for error detection and correction on the Xilinx Versal DDR561 memory controller.562 563 Report both single bit errors (CE) and double bit errors (UE).564 Support injecting both correctable and uncorrectable errors565 for debugging purposes.566 567 568endif # EDAC569