2217 lines · c
1// SPDX-License-Identifier: GPL-2.02/*3 * Copyright (C) 2017-2018, Intel Corporation. All rights reserved4 * Copyright Altera Corporation (C) 2014-2016. All rights reserved.5 * Copyright 2011-2012 Calxeda, Inc.6 */7 8#include <asm/cacheflush.h>9#include <linux/ctype.h>10#include <linux/delay.h>11#include <linux/edac.h>12#include <linux/firmware/intel/stratix10-smc.h>13#include <linux/genalloc.h>14#include <linux/interrupt.h>15#include <linux/irqchip/chained_irq.h>16#include <linux/kernel.h>17#include <linux/mfd/altera-sysmgr.h>18#include <linux/mfd/syscon.h>19#include <linux/notifier.h>20#include <linux/of_address.h>21#include <linux/of_irq.h>22#include <linux/of_platform.h>23#include <linux/panic_notifier.h>24#include <linux/platform_device.h>25#include <linux/property.h>26#include <linux/regmap.h>27#include <linux/types.h>28#include <linux/uaccess.h>29 30#include "altera_edac.h"31#include "edac_module.h"32 33#define EDAC_MOD_STR "altera_edac"34#define EDAC_DEVICE "Altera"35 36#ifdef CONFIG_EDAC_ALTERA_SDRAM37static const struct altr_sdram_prv_data c5_data = {38 .ecc_ctrl_offset = CV_CTLCFG_OFST,39 .ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN,40 .ecc_stat_offset = CV_DRAMSTS_OFST,41 .ecc_stat_ce_mask = CV_DRAMSTS_SBEERR,42 .ecc_stat_ue_mask = CV_DRAMSTS_DBEERR,43 .ecc_saddr_offset = CV_ERRADDR_OFST,44 .ecc_daddr_offset = CV_ERRADDR_OFST,45 .ecc_cecnt_offset = CV_SBECOUNT_OFST,46 .ecc_uecnt_offset = CV_DBECOUNT_OFST,47 .ecc_irq_en_offset = CV_DRAMINTR_OFST,48 .ecc_irq_en_mask = CV_DRAMINTR_INTREN,49 .ecc_irq_clr_offset = CV_DRAMINTR_OFST,50 .ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN),51 .ecc_cnt_rst_offset = CV_DRAMINTR_OFST,52 .ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR,53 .ce_ue_trgr_offset = CV_CTLCFG_OFST,54 .ce_set_mask = CV_CTLCFG_GEN_SB_ERR,55 .ue_set_mask = CV_CTLCFG_GEN_DB_ERR,56};57 58static const struct altr_sdram_prv_data a10_data = {59 .ecc_ctrl_offset = A10_ECCCTRL1_OFST,60 .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN,61 .ecc_stat_offset = A10_INTSTAT_OFST,62 .ecc_stat_ce_mask = A10_INTSTAT_SBEERR,63 .ecc_stat_ue_mask = A10_INTSTAT_DBEERR,64 .ecc_saddr_offset = A10_SERRADDR_OFST,65 .ecc_daddr_offset = A10_DERRADDR_OFST,66 .ecc_irq_en_offset = A10_ERRINTEN_OFST,67 .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK,68 .ecc_irq_clr_offset = A10_INTSTAT_OFST,69 .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),70 .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST,71 .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK,72 .ce_ue_trgr_offset = A10_DIAGINTTEST_OFST,73 .ce_set_mask = A10_DIAGINT_TSERRA_MASK,74 .ue_set_mask = A10_DIAGINT_TDERRA_MASK,75};76 77/*********************** EDAC Memory Controller Functions ****************/78 79/* The SDRAM controller uses the EDAC Memory Controller framework. */80 81static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)82{83 struct mem_ctl_info *mci = dev_id;84 struct altr_sdram_mc_data *drvdata = mci->pvt_info;85 const struct altr_sdram_prv_data *priv = drvdata->data;86 u32 status, err_count = 1, err_addr;87 88 regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status);89 90 if (status & priv->ecc_stat_ue_mask) {91 regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset,92 &err_addr);93 if (priv->ecc_uecnt_offset)94 regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset,95 &err_count);96 panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",97 err_count, err_addr);98 }99 if (status & priv->ecc_stat_ce_mask) {100 regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset,101 &err_addr);102 if (priv->ecc_uecnt_offset)103 regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset,104 &err_count);105 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,106 err_addr >> PAGE_SHIFT,107 err_addr & ~PAGE_MASK, 0,108 0, 0, -1, mci->ctl_name, "");109 /* Clear IRQ to resume */110 regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset,111 priv->ecc_irq_clr_mask);112 113 return IRQ_HANDLED;114 }115 return IRQ_NONE;116}117 118static ssize_t altr_sdr_mc_err_inject_write(struct file *file,119 const char __user *data,120 size_t count, loff_t *ppos)121{122 struct mem_ctl_info *mci = file->private_data;123 struct altr_sdram_mc_data *drvdata = mci->pvt_info;124 const struct altr_sdram_prv_data *priv = drvdata->data;125 u32 *ptemp;126 dma_addr_t dma_handle;127 u32 reg, read_reg;128 129 ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL);130 if (!ptemp) {131 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);132 edac_printk(KERN_ERR, EDAC_MC,133 "Inject: Buffer Allocation error\n");134 return -ENOMEM;135 }136 137 regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset,138 &read_reg);139 read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask);140 141 /* Error are injected by writing a word while the SBE or DBE142 * bit in the CTLCFG register is set. Reading the word will143 * trigger the SBE or DBE error and the corresponding IRQ.144 */145 if (count == 3) {146 edac_printk(KERN_ALERT, EDAC_MC,147 "Inject Double bit error\n");148 local_irq_disable();149 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,150 (read_reg | priv->ue_set_mask));151 local_irq_enable();152 } else {153 edac_printk(KERN_ALERT, EDAC_MC,154 "Inject Single bit error\n");155 local_irq_disable();156 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,157 (read_reg | priv->ce_set_mask));158 local_irq_enable();159 }160 161 ptemp[0] = 0x5A5A5A5A;162 ptemp[1] = 0xA5A5A5A5;163 164 /* Clear the error injection bits */165 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg);166 /* Ensure it has been written out */167 wmb();168 169 /*170 * To trigger the error, we need to read the data back171 * (the data was written with errors above).172 * The READ_ONCE macros and printk are used to prevent the173 * the compiler optimizing these reads out.174 */175 reg = READ_ONCE(ptemp[0]);176 read_reg = READ_ONCE(ptemp[1]);177 /* Force Read */178 rmb();179 180 edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n",181 reg, read_reg);182 183 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);184 185 return count;186}187 188static const struct file_operations altr_sdr_mc_debug_inject_fops = {189 .open = simple_open,190 .write = altr_sdr_mc_err_inject_write,191 .llseek = generic_file_llseek,192};193 194static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)195{196 if (!IS_ENABLED(CONFIG_EDAC_DEBUG))197 return;198 199 if (!mci->debugfs)200 return;201 202 edac_debugfs_create_file("altr_trigger", S_IWUSR, mci->debugfs, mci,203 &altr_sdr_mc_debug_inject_fops);204}205 206/* Get total memory size from Open Firmware DTB */207static unsigned long get_total_mem(void)208{209 struct device_node *np = NULL;210 struct resource res;211 int ret;212 unsigned long total_mem = 0;213 214 for_each_node_by_type(np, "memory") {215 ret = of_address_to_resource(np, 0, &res);216 if (ret)217 continue;218 219 total_mem += resource_size(&res);220 }221 edac_dbg(0, "total_mem 0x%lx\n", total_mem);222 return total_mem;223}224 225static const struct of_device_id altr_sdram_ctrl_of_match[] = {226 { .compatible = "altr,sdram-edac", .data = &c5_data},227 { .compatible = "altr,sdram-edac-a10", .data = &a10_data},228 {},229};230MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);231 232static int a10_init(struct regmap *mc_vbase)233{234 if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST,235 A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) {236 edac_printk(KERN_ERR, EDAC_MC,237 "Error setting SB IRQ mode\n");238 return -ENODEV;239 }240 241 if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) {242 edac_printk(KERN_ERR, EDAC_MC,243 "Error setting trigger count\n");244 return -ENODEV;245 }246 247 return 0;248}249 250static int a10_unmask_irq(struct platform_device *pdev, u32 mask)251{252 void __iomem *sm_base;253 int ret = 0;254 255 if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32),256 dev_name(&pdev->dev))) {257 edac_printk(KERN_ERR, EDAC_MC,258 "Unable to request mem region\n");259 return -EBUSY;260 }261 262 sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32));263 if (!sm_base) {264 edac_printk(KERN_ERR, EDAC_MC,265 "Unable to ioremap device\n");266 267 ret = -ENOMEM;268 goto release;269 }270 271 iowrite32(mask, sm_base);272 273 iounmap(sm_base);274 275release:276 release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32));277 278 return ret;279}280 281static int altr_sdram_probe(struct platform_device *pdev)282{283 struct edac_mc_layer layers[2];284 struct mem_ctl_info *mci;285 struct altr_sdram_mc_data *drvdata;286 const struct altr_sdram_prv_data *priv;287 struct regmap *mc_vbase;288 struct dimm_info *dimm;289 u32 read_reg;290 int irq, irq2, res = 0;291 unsigned long mem_size, irqflags = 0;292 293 /* Grab the register range from the sdr controller in device tree */294 mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,295 "altr,sdr-syscon");296 if (IS_ERR(mc_vbase)) {297 edac_printk(KERN_ERR, EDAC_MC,298 "regmap for altr,sdr-syscon lookup failed.\n");299 return -ENODEV;300 }301 302 /* Check specific dependencies for the module */303 priv = device_get_match_data(&pdev->dev);304 305 /* Validate the SDRAM controller has ECC enabled */306 if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) ||307 ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {308 edac_printk(KERN_ERR, EDAC_MC,309 "No ECC/ECC disabled [0x%08X]\n", read_reg);310 return -ENODEV;311 }312 313 /* Grab memory size from device tree. */314 mem_size = get_total_mem();315 if (!mem_size) {316 edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");317 return -ENODEV;318 }319 320 /* Ensure the SDRAM Interrupt is disabled */321 if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset,322 priv->ecc_irq_en_mask, 0)) {323 edac_printk(KERN_ERR, EDAC_MC,324 "Error disabling SDRAM ECC IRQ\n");325 return -ENODEV;326 }327 328 /* Toggle to clear the SDRAM Error count */329 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,330 priv->ecc_cnt_rst_mask,331 priv->ecc_cnt_rst_mask)) {332 edac_printk(KERN_ERR, EDAC_MC,333 "Error clearing SDRAM ECC count\n");334 return -ENODEV;335 }336 337 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,338 priv->ecc_cnt_rst_mask, 0)) {339 edac_printk(KERN_ERR, EDAC_MC,340 "Error clearing SDRAM ECC count\n");341 return -ENODEV;342 }343 344 irq = platform_get_irq(pdev, 0);345 if (irq < 0) {346 edac_printk(KERN_ERR, EDAC_MC,347 "No irq %d in DT\n", irq);348 return irq;349 }350 351 /* Arria10 has a 2nd IRQ */352 irq2 = platform_get_irq(pdev, 1);353 354 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;355 layers[0].size = 1;356 layers[0].is_virt_csrow = true;357 layers[1].type = EDAC_MC_LAYER_CHANNEL;358 layers[1].size = 1;359 layers[1].is_virt_csrow = false;360 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,361 sizeof(struct altr_sdram_mc_data));362 if (!mci)363 return -ENOMEM;364 365 mci->pdev = &pdev->dev;366 drvdata = mci->pvt_info;367 drvdata->mc_vbase = mc_vbase;368 drvdata->data = priv;369 platform_set_drvdata(pdev, mci);370 371 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {372 edac_printk(KERN_ERR, EDAC_MC,373 "Unable to get managed device resource\n");374 res = -ENOMEM;375 goto free;376 }377 378 mci->mtype_cap = MEM_FLAG_DDR3;379 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;380 mci->edac_cap = EDAC_FLAG_SECDED;381 mci->mod_name = EDAC_MOD_STR;382 mci->ctl_name = dev_name(&pdev->dev);383 mci->scrub_mode = SCRUB_SW_SRC;384 mci->dev_name = dev_name(&pdev->dev);385 386 dimm = *mci->dimms;387 dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;388 dimm->grain = 8;389 dimm->dtype = DEV_X8;390 dimm->mtype = MEM_DDR3;391 dimm->edac_mode = EDAC_SECDED;392 393 res = edac_mc_add_mc(mci);394 if (res < 0)395 goto err;396 397 /* Only the Arria10 has separate IRQs */398 if (of_machine_is_compatible("altr,socfpga-arria10")) {399 /* Arria10 specific initialization */400 res = a10_init(mc_vbase);401 if (res < 0)402 goto err2;403 404 res = devm_request_irq(&pdev->dev, irq2,405 altr_sdram_mc_err_handler,406 IRQF_SHARED, dev_name(&pdev->dev), mci);407 if (res < 0) {408 edac_mc_printk(mci, KERN_ERR,409 "Unable to request irq %d\n", irq2);410 res = -ENODEV;411 goto err2;412 }413 414 res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK);415 if (res < 0)416 goto err2;417 418 irqflags = IRQF_SHARED;419 }420 421 res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,422 irqflags, dev_name(&pdev->dev), mci);423 if (res < 0) {424 edac_mc_printk(mci, KERN_ERR,425 "Unable to request irq %d\n", irq);426 res = -ENODEV;427 goto err2;428 }429 430 /* Infrastructure ready - enable the IRQ */431 if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,432 priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {433 edac_mc_printk(mci, KERN_ERR,434 "Error enabling SDRAM ECC IRQ\n");435 res = -ENODEV;436 goto err2;437 }438 439 altr_sdr_mc_create_debugfs_nodes(mci);440 441 devres_close_group(&pdev->dev, NULL);442 443 return 0;444 445err2:446 edac_mc_del_mc(&pdev->dev);447err:448 devres_release_group(&pdev->dev, NULL);449free:450 edac_mc_free(mci);451 edac_printk(KERN_ERR, EDAC_MC,452 "EDAC Probe Failed; Error %d\n", res);453 454 return res;455}456 457static void altr_sdram_remove(struct platform_device *pdev)458{459 struct mem_ctl_info *mci = platform_get_drvdata(pdev);460 461 edac_mc_del_mc(&pdev->dev);462 edac_mc_free(mci);463 platform_set_drvdata(pdev, NULL);464}465 466/*467 * If you want to suspend, need to disable EDAC by removing it468 * from the device tree or defconfig.469 */470#ifdef CONFIG_PM471static int altr_sdram_prepare(struct device *dev)472{473 pr_err("Suspend not allowed when EDAC is enabled.\n");474 475 return -EPERM;476}477 478static const struct dev_pm_ops altr_sdram_pm_ops = {479 .prepare = altr_sdram_prepare,480};481#endif482 483static struct platform_driver altr_sdram_edac_driver = {484 .probe = altr_sdram_probe,485 .remove_new = altr_sdram_remove,486 .driver = {487 .name = "altr_sdram_edac",488#ifdef CONFIG_PM489 .pm = &altr_sdram_pm_ops,490#endif491 .of_match_table = altr_sdram_ctrl_of_match,492 },493};494 495module_platform_driver(altr_sdram_edac_driver);496 497#endif /* CONFIG_EDAC_ALTERA_SDRAM */498 499/************************* EDAC Parent Probe *************************/500 501static const struct of_device_id altr_edac_device_of_match[];502 503static const struct of_device_id altr_edac_of_match[] = {504 { .compatible = "altr,socfpga-ecc-manager" },505 {},506};507MODULE_DEVICE_TABLE(of, altr_edac_of_match);508 509static int altr_edac_probe(struct platform_device *pdev)510{511 of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match,512 NULL, &pdev->dev);513 return 0;514}515 516static struct platform_driver altr_edac_driver = {517 .probe = altr_edac_probe,518 .driver = {519 .name = "socfpga_ecc_manager",520 .of_match_table = altr_edac_of_match,521 },522};523module_platform_driver(altr_edac_driver);524 525/************************* EDAC Device Functions *************************/526 527/*528 * EDAC Device Functions (shared between various IPs).529 * The discrete memories use the EDAC Device framework. The probe530 * and error handling functions are very similar between memories531 * so they are shared. The memory allocation and freeing for EDAC532 * trigger testing are different for each memory.533 */534 535#ifdef CONFIG_EDAC_ALTERA_OCRAM536static const struct edac_device_prv_data ocramecc_data;537#endif538#ifdef CONFIG_EDAC_ALTERA_L2C539static const struct edac_device_prv_data l2ecc_data;540#endif541#ifdef CONFIG_EDAC_ALTERA_OCRAM542static const struct edac_device_prv_data a10_ocramecc_data;543#endif544#ifdef CONFIG_EDAC_ALTERA_L2C545static const struct edac_device_prv_data a10_l2ecc_data;546#endif547 548static irqreturn_t altr_edac_device_handler(int irq, void *dev_id)549{550 irqreturn_t ret_value = IRQ_NONE;551 struct edac_device_ctl_info *dci = dev_id;552 struct altr_edac_device_dev *drvdata = dci->pvt_info;553 const struct edac_device_prv_data *priv = drvdata->data;554 555 if (irq == drvdata->sb_irq) {556 if (priv->ce_clear_mask)557 writel(priv->ce_clear_mask, drvdata->base);558 edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name);559 ret_value = IRQ_HANDLED;560 } else if (irq == drvdata->db_irq) {561 if (priv->ue_clear_mask)562 writel(priv->ue_clear_mask, drvdata->base);563 edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name);564 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");565 ret_value = IRQ_HANDLED;566 } else {567 WARN_ON(1);568 }569 570 return ret_value;571}572 573static ssize_t __maybe_unused574altr_edac_device_trig(struct file *file, const char __user *user_buf,575 size_t count, loff_t *ppos)576 577{578 u32 *ptemp, i, error_mask;579 int result = 0;580 u8 trig_type;581 unsigned long flags;582 struct edac_device_ctl_info *edac_dci = file->private_data;583 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;584 const struct edac_device_prv_data *priv = drvdata->data;585 void *generic_ptr = edac_dci->dev;586 587 if (!user_buf || get_user(trig_type, user_buf))588 return -EFAULT;589 590 if (!priv->alloc_mem)591 return -ENOMEM;592 593 /*594 * Note that generic_ptr is initialized to the device * but in595 * some alloc_functions, this is overridden and returns data.596 */597 ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr);598 if (!ptemp) {599 edac_printk(KERN_ERR, EDAC_DEVICE,600 "Inject: Buffer Allocation error\n");601 return -ENOMEM;602 }603 604 if (trig_type == ALTR_UE_TRIGGER_CHAR)605 error_mask = priv->ue_set_mask;606 else607 error_mask = priv->ce_set_mask;608 609 edac_printk(KERN_ALERT, EDAC_DEVICE,610 "Trigger Error Mask (0x%X)\n", error_mask);611 612 local_irq_save(flags);613 /* write ECC corrupted data out. */614 for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) {615 /* Read data so we're in the correct state */616 rmb();617 if (READ_ONCE(ptemp[i]))618 result = -1;619 /* Toggle Error bit (it is latched), leave ECC enabled */620 writel(error_mask, (drvdata->base + priv->set_err_ofst));621 writel(priv->ecc_enable_mask, (drvdata->base +622 priv->set_err_ofst));623 ptemp[i] = i;624 }625 /* Ensure it has been written out */626 wmb();627 local_irq_restore(flags);628 629 if (result)630 edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n");631 632 /* Read out written data. ECC error caused here */633 for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++)634 if (READ_ONCE(ptemp[i]) != i)635 edac_printk(KERN_ERR, EDAC_DEVICE,636 "Read doesn't match written data\n");637 638 if (priv->free_mem)639 priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr);640 641 return count;642}643 644static const struct file_operations altr_edac_device_inject_fops __maybe_unused = {645 .open = simple_open,646 .write = altr_edac_device_trig,647 .llseek = generic_file_llseek,648};649 650static ssize_t __maybe_unused651altr_edac_a10_device_trig(struct file *file, const char __user *user_buf,652 size_t count, loff_t *ppos);653 654static const struct file_operations altr_edac_a10_device_inject_fops __maybe_unused = {655 .open = simple_open,656 .write = altr_edac_a10_device_trig,657 .llseek = generic_file_llseek,658};659 660static ssize_t __maybe_unused661altr_edac_a10_device_trig2(struct file *file, const char __user *user_buf,662 size_t count, loff_t *ppos);663 664static const struct file_operations altr_edac_a10_device_inject2_fops __maybe_unused = {665 .open = simple_open,666 .write = altr_edac_a10_device_trig2,667 .llseek = generic_file_llseek,668};669 670static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci,671 const struct edac_device_prv_data *priv)672{673 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;674 675 if (!IS_ENABLED(CONFIG_EDAC_DEBUG))676 return;677 678 drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name);679 if (!drvdata->debugfs_dir)680 return;681 682 if (!edac_debugfs_create_file("altr_trigger", S_IWUSR,683 drvdata->debugfs_dir, edac_dci,684 priv->inject_fops))685 debugfs_remove_recursive(drvdata->debugfs_dir);686}687 688static const struct of_device_id altr_edac_device_of_match[] = {689#ifdef CONFIG_EDAC_ALTERA_L2C690 { .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data },691#endif692#ifdef CONFIG_EDAC_ALTERA_OCRAM693 { .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data },694#endif695 {},696};697MODULE_DEVICE_TABLE(of, altr_edac_device_of_match);698 699/*700 * altr_edac_device_probe()701 * This is a generic EDAC device driver that will support702 * various Altera memory devices such as the L2 cache ECC and703 * OCRAM ECC as well as the memories for other peripherals.704 * Module specific initialization is done by passing the705 * function index in the device tree.706 */707static int altr_edac_device_probe(struct platform_device *pdev)708{709 struct edac_device_ctl_info *dci;710 struct altr_edac_device_dev *drvdata;711 struct resource *r;712 int res = 0;713 struct device_node *np = pdev->dev.of_node;714 char *ecc_name = (char *)np->name;715 static int dev_instance;716 717 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {718 edac_printk(KERN_ERR, EDAC_DEVICE,719 "Unable to open devm\n");720 return -ENOMEM;721 }722 723 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);724 if (!r) {725 edac_printk(KERN_ERR, EDAC_DEVICE,726 "Unable to get mem resource\n");727 res = -ENODEV;728 goto fail;729 }730 731 if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r),732 dev_name(&pdev->dev))) {733 edac_printk(KERN_ERR, EDAC_DEVICE,734 "%s:Error requesting mem region\n", ecc_name);735 res = -EBUSY;736 goto fail;737 }738 739 dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name,740 1, ecc_name, 1, 0, dev_instance++);741 742 if (!dci) {743 edac_printk(KERN_ERR, EDAC_DEVICE,744 "%s: Unable to allocate EDAC device\n", ecc_name);745 res = -ENOMEM;746 goto fail;747 }748 749 drvdata = dci->pvt_info;750 dci->dev = &pdev->dev;751 platform_set_drvdata(pdev, dci);752 drvdata->edac_dev_name = ecc_name;753 754 drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));755 if (!drvdata->base) {756 res = -ENOMEM;757 goto fail1;758 }759 760 /* Get driver specific data for this EDAC device */761 drvdata->data = of_match_node(altr_edac_device_of_match, np)->data;762 763 /* Check specific dependencies for the module */764 if (drvdata->data->setup) {765 res = drvdata->data->setup(drvdata);766 if (res)767 goto fail1;768 }769 770 drvdata->sb_irq = platform_get_irq(pdev, 0);771 res = devm_request_irq(&pdev->dev, drvdata->sb_irq,772 altr_edac_device_handler,773 0, dev_name(&pdev->dev), dci);774 if (res)775 goto fail1;776 777 drvdata->db_irq = platform_get_irq(pdev, 1);778 res = devm_request_irq(&pdev->dev, drvdata->db_irq,779 altr_edac_device_handler,780 0, dev_name(&pdev->dev), dci);781 if (res)782 goto fail1;783 784 dci->mod_name = "Altera ECC Manager";785 dci->dev_name = drvdata->edac_dev_name;786 787 res = edac_device_add_device(dci);788 if (res)789 goto fail1;790 791 altr_create_edacdev_dbgfs(dci, drvdata->data);792 793 devres_close_group(&pdev->dev, NULL);794 795 return 0;796 797fail1:798 edac_device_free_ctl_info(dci);799fail:800 devres_release_group(&pdev->dev, NULL);801 edac_printk(KERN_ERR, EDAC_DEVICE,802 "%s:Error setting up EDAC device: %d\n", ecc_name, res);803 804 return res;805}806 807static void altr_edac_device_remove(struct platform_device *pdev)808{809 struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);810 struct altr_edac_device_dev *drvdata = dci->pvt_info;811 812 debugfs_remove_recursive(drvdata->debugfs_dir);813 edac_device_del_device(&pdev->dev);814 edac_device_free_ctl_info(dci);815}816 817static struct platform_driver altr_edac_device_driver = {818 .probe = altr_edac_device_probe,819 .remove_new = altr_edac_device_remove,820 .driver = {821 .name = "altr_edac_device",822 .of_match_table = altr_edac_device_of_match,823 },824};825module_platform_driver(altr_edac_device_driver);826 827/******************* Arria10 Device ECC Shared Functions *****************/828 829/*830 * Test for memory's ECC dependencies upon entry because platform specific831 * startup should have initialized the memory and enabled the ECC.832 * Can't turn on ECC here because accessing un-initialized memory will833 * cause CE/UE errors possibly causing an ABORT.834 */835static int __maybe_unused836altr_check_ecc_deps(struct altr_edac_device_dev *device)837{838 void __iomem *base = device->base;839 const struct edac_device_prv_data *prv = device->data;840 841 if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask)842 return 0;843 844 edac_printk(KERN_ERR, EDAC_DEVICE,845 "%s: No ECC present or ECC disabled.\n",846 device->edac_dev_name);847 return -ENODEV;848}849 850static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id)851{852 struct altr_edac_device_dev *dci = dev_id;853 void __iomem *base = dci->base;854 855 if (irq == dci->sb_irq) {856 writel(ALTR_A10_ECC_SERRPENA,857 base + ALTR_A10_ECC_INTSTAT_OFST);858 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);859 860 return IRQ_HANDLED;861 } else if (irq == dci->db_irq) {862 writel(ALTR_A10_ECC_DERRPENA,863 base + ALTR_A10_ECC_INTSTAT_OFST);864 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);865 if (dci->data->panic)866 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");867 868 return IRQ_HANDLED;869 }870 871 WARN_ON(1);872 873 return IRQ_NONE;874}875 876/******************* Arria10 Memory Buffer Functions *********************/877 878static inline int a10_get_irq_mask(struct device_node *np)879{880 int irq;881 const u32 *handle = of_get_property(np, "interrupts", NULL);882 883 if (!handle)884 return -ENODEV;885 irq = be32_to_cpup(handle);886 return irq;887}888 889static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr)890{891 u32 value = readl(ioaddr);892 893 value |= bit_mask;894 writel(value, ioaddr);895}896 897static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr)898{899 u32 value = readl(ioaddr);900 901 value &= ~bit_mask;902 writel(value, ioaddr);903}904 905static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr)906{907 u32 value = readl(ioaddr);908 909 return (value & bit_mask) ? 1 : 0;910}911 912/*913 * This function uses the memory initialization block in the Arria10 ECC914 * controller to initialize/clear the entire memory data and ECC data.915 */916static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port)917{918 int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US;919 u32 init_mask, stat_mask, clear_mask;920 int ret = 0;921 922 if (port) {923 init_mask = ALTR_A10_ECC_INITB;924 stat_mask = ALTR_A10_ECC_INITCOMPLETEB;925 clear_mask = ALTR_A10_ECC_ERRPENB_MASK;926 } else {927 init_mask = ALTR_A10_ECC_INITA;928 stat_mask = ALTR_A10_ECC_INITCOMPLETEA;929 clear_mask = ALTR_A10_ECC_ERRPENA_MASK;930 }931 932 ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST));933 while (limit--) {934 if (ecc_test_bits(stat_mask,935 (ioaddr + ALTR_A10_ECC_INITSTAT_OFST)))936 break;937 udelay(1);938 }939 if (limit < 0)940 ret = -EBUSY;941 942 /* Clear any pending ECC interrupts */943 writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST));944 945 return ret;946}947 948static __init int __maybe_unused949altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask,950 u32 ecc_ctrl_en_mask, bool dual_port)951{952 int ret = 0;953 void __iomem *ecc_block_base;954 struct regmap *ecc_mgr_map;955 char *ecc_name;956 struct device_node *np_eccmgr;957 958 ecc_name = (char *)np->name;959 960 /* Get the ECC Manager - parent of the device EDACs */961 np_eccmgr = of_get_parent(np);962 963 ecc_mgr_map =964 altr_sysmgr_regmap_lookup_by_phandle(np_eccmgr,965 "altr,sysmgr-syscon");966 967 of_node_put(np_eccmgr);968 if (IS_ERR(ecc_mgr_map)) {969 edac_printk(KERN_ERR, EDAC_DEVICE,970 "Unable to get syscon altr,sysmgr-syscon\n");971 return -ENODEV;972 }973 974 /* Map the ECC Block */975 ecc_block_base = of_iomap(np, 0);976 if (!ecc_block_base) {977 edac_printk(KERN_ERR, EDAC_DEVICE,978 "Unable to map %s ECC block\n", ecc_name);979 return -ENODEV;980 }981 982 /* Disable ECC */983 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask);984 writel(ALTR_A10_ECC_SERRINTEN,985 (ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST));986 ecc_clear_bits(ecc_ctrl_en_mask,987 (ecc_block_base + ALTR_A10_ECC_CTRL_OFST));988 /* Ensure all writes complete */989 wmb();990 /* Use HW initialization block to initialize memory for ECC */991 ret = altr_init_memory_port(ecc_block_base, 0);992 if (ret) {993 edac_printk(KERN_ERR, EDAC_DEVICE,994 "ECC: cannot init %s PORTA memory\n", ecc_name);995 goto out;996 }997 998 if (dual_port) {999 ret = altr_init_memory_port(ecc_block_base, 1);1000 if (ret) {1001 edac_printk(KERN_ERR, EDAC_DEVICE,1002 "ECC: cannot init %s PORTB memory\n",1003 ecc_name);1004 goto out;1005 }1006 }1007 1008 /* Interrupt mode set to every SBERR */1009 regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST,1010 ALTR_A10_ECC_INTMODE);1011 /* Enable ECC */1012 ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base +1013 ALTR_A10_ECC_CTRL_OFST));1014 writel(ALTR_A10_ECC_SERRINTEN,1015 (ecc_block_base + ALTR_A10_ECC_ERRINTENS_OFST));1016 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, irq_mask);1017 /* Ensure all writes complete */1018 wmb();1019out:1020 iounmap(ecc_block_base);1021 return ret;1022}1023 1024static int validate_parent_available(struct device_node *np);1025static const struct of_device_id altr_edac_a10_device_of_match[];1026static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat)1027{1028 int irq;1029 struct device_node *child, *np;1030 1031 np = of_find_compatible_node(NULL, NULL,1032 "altr,socfpga-a10-ecc-manager");1033 if (!np) {1034 edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n");1035 return -ENODEV;1036 }1037 1038 for_each_child_of_node(np, child) {1039 const struct of_device_id *pdev_id;1040 const struct edac_device_prv_data *prv;1041 1042 if (!of_device_is_available(child))1043 continue;1044 if (!of_device_is_compatible(child, compat))1045 continue;1046 1047 if (validate_parent_available(child))1048 continue;1049 1050 irq = a10_get_irq_mask(child);1051 if (irq < 0)1052 continue;1053 1054 /* Get matching node and check for valid result */1055 pdev_id = of_match_node(altr_edac_a10_device_of_match, child);1056 if (IS_ERR_OR_NULL(pdev_id))1057 continue;1058 1059 /* Validate private data pointer before dereferencing */1060 prv = pdev_id->data;1061 if (!prv)1062 continue;1063 1064 altr_init_a10_ecc_block(child, BIT(irq),1065 prv->ecc_enable_mask, 0);1066 }1067 1068 of_node_put(np);1069 return 0;1070}1071 1072/*********************** SDRAM EDAC Device Functions *********************/1073 1074#ifdef CONFIG_EDAC_ALTERA_SDRAM1075 1076/*1077 * A legacy U-Boot bug only enabled memory mapped access to the ECC Enable1078 * register if ECC is enabled. Linux checks the ECC Enable register to1079 * determine ECC status.1080 * Use an SMC call (which always works) to determine ECC enablement.1081 */1082static int altr_s10_sdram_check_ecc_deps(struct altr_edac_device_dev *device)1083{1084 const struct edac_device_prv_data *prv = device->data;1085 unsigned long sdram_ecc_addr;1086 struct arm_smccc_res result;1087 struct device_node *np;1088 phys_addr_t sdram_addr;1089 u32 read_reg;1090 int ret;1091 1092 np = of_find_compatible_node(NULL, NULL, "altr,sdr-ctl");1093 if (!np)1094 goto sdram_err;1095 1096 sdram_addr = of_translate_address(np, of_get_address(np, 0,1097 NULL, NULL));1098 of_node_put(np);1099 sdram_ecc_addr = (unsigned long)sdram_addr + prv->ecc_en_ofst;1100 arm_smccc_smc(INTEL_SIP_SMC_REG_READ, sdram_ecc_addr,1101 0, 0, 0, 0, 0, 0, &result);1102 read_reg = (unsigned int)result.a1;1103 ret = (int)result.a0;1104 if (!ret && (read_reg & prv->ecc_enable_mask))1105 return 0;1106 1107sdram_err:1108 edac_printk(KERN_ERR, EDAC_DEVICE,1109 "%s: No ECC present or ECC disabled.\n",1110 device->edac_dev_name);1111 return -ENODEV;1112}1113 1114static const struct edac_device_prv_data s10_sdramecc_data = {1115 .setup = altr_s10_sdram_check_ecc_deps,1116 .ce_clear_mask = ALTR_S10_ECC_SERRPENA,1117 .ue_clear_mask = ALTR_S10_ECC_DERRPENA,1118 .ecc_enable_mask = ALTR_S10_ECC_EN,1119 .ecc_en_ofst = ALTR_S10_ECC_CTRL_SDRAM_OFST,1120 .ce_set_mask = ALTR_S10_ECC_TSERRA,1121 .ue_set_mask = ALTR_S10_ECC_TDERRA,1122 .set_err_ofst = ALTR_S10_ECC_INTTEST_OFST,1123 .ecc_irq_handler = altr_edac_a10_ecc_irq,1124 .inject_fops = &altr_edac_a10_device_inject_fops,1125};1126#endif /* CONFIG_EDAC_ALTERA_SDRAM */1127 1128/*********************** OCRAM EDAC Device Functions *********************/1129 1130#ifdef CONFIG_EDAC_ALTERA_OCRAM1131 1132static void *ocram_alloc_mem(size_t size, void **other)1133{1134 struct device_node *np;1135 struct gen_pool *gp;1136 void *sram_addr;1137 1138 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc");1139 if (!np)1140 return NULL;1141 1142 gp = of_gen_pool_get(np, "iram", 0);1143 of_node_put(np);1144 if (!gp)1145 return NULL;1146 1147 sram_addr = (void *)gen_pool_alloc(gp, size);1148 if (!sram_addr)1149 return NULL;1150 1151 memset(sram_addr, 0, size);1152 /* Ensure data is written out */1153 wmb();1154 1155 /* Remember this handle for freeing later */1156 *other = gp;1157 1158 return sram_addr;1159}1160 1161static void ocram_free_mem(void *p, size_t size, void *other)1162{1163 gen_pool_free((struct gen_pool *)other, (unsigned long)p, size);1164}1165 1166static const struct edac_device_prv_data ocramecc_data = {1167 .setup = altr_check_ecc_deps,1168 .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR),1169 .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR),1170 .alloc_mem = ocram_alloc_mem,1171 .free_mem = ocram_free_mem,1172 .ecc_enable_mask = ALTR_OCR_ECC_EN,1173 .ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET,1174 .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS),1175 .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD),1176 .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET,1177 .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE,1178 .inject_fops = &altr_edac_device_inject_fops,1179};1180 1181static int __maybe_unused1182altr_check_ocram_deps_init(struct altr_edac_device_dev *device)1183{1184 void __iomem *base = device->base;1185 int ret;1186 1187 ret = altr_check_ecc_deps(device);1188 if (ret)1189 return ret;1190 1191 /* Verify OCRAM has been initialized */1192 if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA,1193 (base + ALTR_A10_ECC_INITSTAT_OFST)))1194 return -ENODEV;1195 1196 /* Enable IRQ on Single Bit Error */1197 writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST));1198 /* Ensure all writes complete */1199 wmb();1200 1201 return 0;1202}1203 1204static const struct edac_device_prv_data a10_ocramecc_data = {1205 .setup = altr_check_ocram_deps_init,1206 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,1207 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,1208 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM,1209 .ecc_enable_mask = ALTR_A10_OCRAM_ECC_EN_CTL,1210 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,1211 .ce_set_mask = ALTR_A10_ECC_TSERRA,1212 .ue_set_mask = ALTR_A10_ECC_TDERRA,1213 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,1214 .ecc_irq_handler = altr_edac_a10_ecc_irq,1215 .inject_fops = &altr_edac_a10_device_inject2_fops,1216 /*1217 * OCRAM panic on uncorrectable error because sleep/resume1218 * functions and FPGA contents are stored in OCRAM. Prefer1219 * a kernel panic over executing/loading corrupted data.1220 */1221 .panic = true,1222};1223 1224#endif /* CONFIG_EDAC_ALTERA_OCRAM */1225 1226/********************* L2 Cache EDAC Device Functions ********************/1227 1228#ifdef CONFIG_EDAC_ALTERA_L2C1229 1230static void *l2_alloc_mem(size_t size, void **other)1231{1232 struct device *dev = *other;1233 void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL);1234 1235 if (!ptemp)1236 return NULL;1237 1238 /* Make sure everything is written out */1239 wmb();1240 1241 /*1242 * Clean all cache levels up to LoC (includes L2)1243 * This ensures the corrupted data is written into1244 * L2 cache for readback test (which causes ECC error).1245 */1246 flush_cache_all();1247 1248 return ptemp;1249}1250 1251static void l2_free_mem(void *p, size_t size, void *other)1252{1253 struct device *dev = other;1254 1255 if (dev && p)1256 devm_kfree(dev, p);1257}1258 1259/*1260 * altr_l2_check_deps()1261 * Test for L2 cache ECC dependencies upon entry because1262 * platform specific startup should have initialized the L21263 * memory and enabled the ECC.1264 * Bail if ECC is not enabled.1265 * Note that L2 Cache Enable is forced at build time.1266 */1267static int altr_l2_check_deps(struct altr_edac_device_dev *device)1268{1269 void __iomem *base = device->base;1270 const struct edac_device_prv_data *prv = device->data;1271 1272 if ((readl(base) & prv->ecc_enable_mask) ==1273 prv->ecc_enable_mask)1274 return 0;1275 1276 edac_printk(KERN_ERR, EDAC_DEVICE,1277 "L2: No ECC present, or ECC disabled\n");1278 return -ENODEV;1279}1280 1281static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id)1282{1283 struct altr_edac_device_dev *dci = dev_id;1284 1285 if (irq == dci->sb_irq) {1286 regmap_write(dci->edac->ecc_mgr_map,1287 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,1288 A10_SYSGMR_MPU_CLEAR_L2_ECC_SB);1289 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);1290 1291 return IRQ_HANDLED;1292 } else if (irq == dci->db_irq) {1293 regmap_write(dci->edac->ecc_mgr_map,1294 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,1295 A10_SYSGMR_MPU_CLEAR_L2_ECC_MB);1296 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);1297 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");1298 1299 return IRQ_HANDLED;1300 }1301 1302 WARN_ON(1);1303 1304 return IRQ_NONE;1305}1306 1307static const struct edac_device_prv_data l2ecc_data = {1308 .setup = altr_l2_check_deps,1309 .ce_clear_mask = 0,1310 .ue_clear_mask = 0,1311 .alloc_mem = l2_alloc_mem,1312 .free_mem = l2_free_mem,1313 .ecc_enable_mask = ALTR_L2_ECC_EN,1314 .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS),1315 .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD),1316 .set_err_ofst = ALTR_L2_ECC_REG_OFFSET,1317 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,1318 .inject_fops = &altr_edac_device_inject_fops,1319};1320 1321static const struct edac_device_prv_data a10_l2ecc_data = {1322 .setup = altr_l2_check_deps,1323 .ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR,1324 .ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR,1325 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2,1326 .alloc_mem = l2_alloc_mem,1327 .free_mem = l2_free_mem,1328 .ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL,1329 .ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK,1330 .ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK,1331 .set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST,1332 .ecc_irq_handler = altr_edac_a10_l2_irq,1333 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,1334 .inject_fops = &altr_edac_device_inject_fops,1335};1336 1337#endif /* CONFIG_EDAC_ALTERA_L2C */1338 1339/********************* Ethernet Device Functions ********************/1340 1341#ifdef CONFIG_EDAC_ALTERA_ETHERNET1342 1343static int __init socfpga_init_ethernet_ecc(struct altr_edac_device_dev *dev)1344{1345 int ret;1346 1347 ret = altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc");1348 if (ret)1349 return ret;1350 1351 return altr_check_ecc_deps(dev);1352}1353 1354static const struct edac_device_prv_data a10_enetecc_data = {1355 .setup = socfpga_init_ethernet_ecc,1356 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,1357 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,1358 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,1359 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,1360 .ce_set_mask = ALTR_A10_ECC_TSERRA,1361 .ue_set_mask = ALTR_A10_ECC_TDERRA,1362 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,1363 .ecc_irq_handler = altr_edac_a10_ecc_irq,1364 .inject_fops = &altr_edac_a10_device_inject2_fops,1365};1366 1367#endif /* CONFIG_EDAC_ALTERA_ETHERNET */1368 1369/********************** NAND Device Functions **********************/1370 1371#ifdef CONFIG_EDAC_ALTERA_NAND1372 1373static int __init socfpga_init_nand_ecc(struct altr_edac_device_dev *device)1374{1375 int ret;1376 1377 ret = altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc");1378 if (ret)1379 return ret;1380 1381 return altr_check_ecc_deps(device);1382}1383 1384static const struct edac_device_prv_data a10_nandecc_data = {1385 .setup = socfpga_init_nand_ecc,1386 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,1387 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,1388 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,1389 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,1390 .ce_set_mask = ALTR_A10_ECC_TSERRA,1391 .ue_set_mask = ALTR_A10_ECC_TDERRA,1392 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,1393 .ecc_irq_handler = altr_edac_a10_ecc_irq,1394 .inject_fops = &altr_edac_a10_device_inject_fops,1395};1396 1397#endif /* CONFIG_EDAC_ALTERA_NAND */1398 1399/********************** DMA Device Functions **********************/1400 1401#ifdef CONFIG_EDAC_ALTERA_DMA1402 1403static int __init socfpga_init_dma_ecc(struct altr_edac_device_dev *device)1404{1405 int ret;1406 1407 ret = altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc");1408 if (ret)1409 return ret;1410 1411 return altr_check_ecc_deps(device);1412}1413 1414static const struct edac_device_prv_data a10_dmaecc_data = {1415 .setup = socfpga_init_dma_ecc,1416 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,1417 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,1418 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,1419 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,1420 .ce_set_mask = ALTR_A10_ECC_TSERRA,1421 .ue_set_mask = ALTR_A10_ECC_TDERRA,1422 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,1423 .ecc_irq_handler = altr_edac_a10_ecc_irq,1424 .inject_fops = &altr_edac_a10_device_inject_fops,1425};1426 1427#endif /* CONFIG_EDAC_ALTERA_DMA */1428 1429/********************** USB Device Functions **********************/1430 1431#ifdef CONFIG_EDAC_ALTERA_USB1432 1433static int __init socfpga_init_usb_ecc(struct altr_edac_device_dev *device)1434{1435 int ret;1436 1437 ret = altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc");1438 if (ret)1439 return ret;1440 1441 return altr_check_ecc_deps(device);1442}1443 1444static const struct edac_device_prv_data a10_usbecc_data = {1445 .setup = socfpga_init_usb_ecc,1446 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,1447 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,1448 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,1449 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,1450 .ce_set_mask = ALTR_A10_ECC_TSERRA,1451 .ue_set_mask = ALTR_A10_ECC_TDERRA,1452 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,1453 .ecc_irq_handler = altr_edac_a10_ecc_irq,1454 .inject_fops = &altr_edac_a10_device_inject2_fops,1455};1456 1457#endif /* CONFIG_EDAC_ALTERA_USB */1458 1459/********************** QSPI Device Functions **********************/1460 1461#ifdef CONFIG_EDAC_ALTERA_QSPI1462 1463static int __init socfpga_init_qspi_ecc(struct altr_edac_device_dev *device)1464{1465 int ret;1466 1467 ret = altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc");1468 if (ret)1469 return ret;1470 1471 return altr_check_ecc_deps(device);1472}1473 1474static const struct edac_device_prv_data a10_qspiecc_data = {1475 .setup = socfpga_init_qspi_ecc,1476 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,1477 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,1478 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,1479 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,1480 .ce_set_mask = ALTR_A10_ECC_TSERRA,1481 .ue_set_mask = ALTR_A10_ECC_TDERRA,1482 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,1483 .ecc_irq_handler = altr_edac_a10_ecc_irq,1484 .inject_fops = &altr_edac_a10_device_inject_fops,1485};1486 1487#endif /* CONFIG_EDAC_ALTERA_QSPI */1488 1489/********************* SDMMC Device Functions **********************/1490 1491#ifdef CONFIG_EDAC_ALTERA_SDMMC1492 1493static const struct edac_device_prv_data a10_sdmmceccb_data;1494static int altr_portb_setup(struct altr_edac_device_dev *device)1495{1496 struct edac_device_ctl_info *dci;1497 struct altr_edac_device_dev *altdev;1498 char *ecc_name = "sdmmcb-ecc";1499 int edac_idx, rc;1500 struct device_node *np;1501 const struct edac_device_prv_data *prv = &a10_sdmmceccb_data;1502 1503 rc = altr_check_ecc_deps(device);1504 if (rc)1505 return rc;1506 1507 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");1508 if (!np) {1509 edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n");1510 return -ENODEV;1511 }1512 1513 /* Create the PortB EDAC device */1514 edac_idx = edac_device_alloc_index();1515 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1,1516 ecc_name, 1, 0, edac_idx);1517 if (!dci) {1518 edac_printk(KERN_ERR, EDAC_DEVICE,1519 "%s: Unable to allocate PortB EDAC device\n",1520 ecc_name);1521 return -ENOMEM;1522 }1523 1524 /* Initialize the PortB EDAC device structure from PortA structure */1525 altdev = dci->pvt_info;1526 *altdev = *device;1527 1528 if (!devres_open_group(&altdev->ddev, altr_portb_setup, GFP_KERNEL))1529 return -ENOMEM;1530 1531 /* Update PortB specific values */1532 altdev->edac_dev_name = ecc_name;1533 altdev->edac_idx = edac_idx;1534 altdev->edac_dev = dci;1535 altdev->data = prv;1536 dci->dev = &altdev->ddev;1537 dci->ctl_name = "Altera ECC Manager";1538 dci->mod_name = ecc_name;1539 dci->dev_name = ecc_name;1540 1541 /*1542 * Update the PortB IRQs - A10 has 4, S10 has 2, Index accordingly1543 *1544 * FIXME: Instead of ifdefs with different architectures the driver1545 * should properly use compatibles.1546 */1547#ifdef CONFIG_64BIT1548 altdev->sb_irq = irq_of_parse_and_map(np, 1);1549#else1550 altdev->sb_irq = irq_of_parse_and_map(np, 2);1551#endif1552 if (!altdev->sb_irq) {1553 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB SBIRQ alloc\n");1554 rc = -ENODEV;1555 goto err_release_group_1;1556 }1557 rc = devm_request_irq(&altdev->ddev, altdev->sb_irq,1558 prv->ecc_irq_handler,1559 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,1560 ecc_name, altdev);1561 if (rc) {1562 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB SBERR IRQ error\n");1563 goto err_release_group_1;1564 }1565 1566#ifdef CONFIG_64BIT1567 /* Use IRQ to determine SError origin instead of assigning IRQ */1568 rc = of_property_read_u32_index(np, "interrupts", 1, &altdev->db_irq);1569 if (rc) {1570 edac_printk(KERN_ERR, EDAC_DEVICE,1571 "Error PortB DBIRQ alloc\n");1572 goto err_release_group_1;1573 }1574#else1575 altdev->db_irq = irq_of_parse_and_map(np, 3);1576 if (!altdev->db_irq) {1577 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB DBIRQ alloc\n");1578 rc = -ENODEV;1579 goto err_release_group_1;1580 }1581 rc = devm_request_irq(&altdev->ddev, altdev->db_irq,1582 prv->ecc_irq_handler,1583 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,1584 ecc_name, altdev);1585 if (rc) {1586 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB DBERR IRQ error\n");1587 goto err_release_group_1;1588 }1589#endif1590 1591 rc = edac_device_add_device(dci);1592 if (rc) {1593 edac_printk(KERN_ERR, EDAC_DEVICE,1594 "edac_device_add_device portB failed\n");1595 rc = -ENOMEM;1596 goto err_release_group_1;1597 }1598 altr_create_edacdev_dbgfs(dci, prv);1599 1600 list_add(&altdev->next, &altdev->edac->a10_ecc_devices);1601 1602 devres_remove_group(&altdev->ddev, altr_portb_setup);1603 1604 return 0;1605 1606err_release_group_1:1607 edac_device_free_ctl_info(dci);1608 devres_release_group(&altdev->ddev, altr_portb_setup);1609 edac_printk(KERN_ERR, EDAC_DEVICE,1610 "%s:Error setting up EDAC device: %d\n", ecc_name, rc);1611 return rc;1612}1613 1614static int __init socfpga_init_sdmmc_ecc(struct altr_edac_device_dev *device)1615{1616 int rc = -ENODEV;1617 struct device_node *child;1618 1619 child = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");1620 if (!child)1621 return -ENODEV;1622 1623 if (!of_device_is_available(child))1624 goto exit;1625 1626 if (validate_parent_available(child))1627 goto exit;1628 1629 /* Init portB */1630 rc = altr_init_a10_ecc_block(child, ALTR_A10_SDMMC_IRQ_MASK,1631 a10_sdmmceccb_data.ecc_enable_mask, 1);1632 if (rc)1633 goto exit;1634 1635 /* Setup portB */1636 return altr_portb_setup(device);1637 1638exit:1639 of_node_put(child);1640 return rc;1641}1642 1643static irqreturn_t altr_edac_a10_ecc_irq_portb(int irq, void *dev_id)1644{1645 struct altr_edac_device_dev *ad = dev_id;1646 void __iomem *base = ad->base;1647 const struct edac_device_prv_data *priv = ad->data;1648 1649 if (irq == ad->sb_irq) {1650 writel(priv->ce_clear_mask,1651 base + ALTR_A10_ECC_INTSTAT_OFST);1652 edac_device_handle_ce(ad->edac_dev, 0, 0, ad->edac_dev_name);1653 return IRQ_HANDLED;1654 } else if (irq == ad->db_irq) {1655 writel(priv->ue_clear_mask,1656 base + ALTR_A10_ECC_INTSTAT_OFST);1657 edac_device_handle_ue(ad->edac_dev, 0, 0, ad->edac_dev_name);1658 return IRQ_HANDLED;1659 }1660 1661 WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq);1662 1663 return IRQ_NONE;1664}1665 1666static const struct edac_device_prv_data a10_sdmmcecca_data = {1667 .setup = socfpga_init_sdmmc_ecc,1668 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,1669 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,1670 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,1671 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,1672 .ce_set_mask = ALTR_A10_ECC_SERRPENA,1673 .ue_set_mask = ALTR_A10_ECC_DERRPENA,1674 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,1675 .ecc_irq_handler = altr_edac_a10_ecc_irq,1676 .inject_fops = &altr_edac_a10_device_inject_fops,1677};1678 1679static const struct edac_device_prv_data a10_sdmmceccb_data = {1680 .setup = socfpga_init_sdmmc_ecc,1681 .ce_clear_mask = ALTR_A10_ECC_SERRPENB,1682 .ue_clear_mask = ALTR_A10_ECC_DERRPENB,1683 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,1684 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,1685 .ce_set_mask = ALTR_A10_ECC_TSERRB,1686 .ue_set_mask = ALTR_A10_ECC_TDERRB,1687 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,1688 .ecc_irq_handler = altr_edac_a10_ecc_irq_portb,1689 .inject_fops = &altr_edac_a10_device_inject_fops,1690};1691 1692#endif /* CONFIG_EDAC_ALTERA_SDMMC */1693 1694/********************* Arria10 EDAC Device Functions *************************/1695static const struct of_device_id altr_edac_a10_device_of_match[] = {1696#ifdef CONFIG_EDAC_ALTERA_L2C1697 { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data },1698#endif1699#ifdef CONFIG_EDAC_ALTERA_OCRAM1700 { .compatible = "altr,socfpga-a10-ocram-ecc",1701 .data = &a10_ocramecc_data },1702#endif1703#ifdef CONFIG_EDAC_ALTERA_ETHERNET1704 { .compatible = "altr,socfpga-eth-mac-ecc",1705 .data = &a10_enetecc_data },1706#endif1707#ifdef CONFIG_EDAC_ALTERA_NAND1708 { .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data },1709#endif1710#ifdef CONFIG_EDAC_ALTERA_DMA1711 { .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data },1712#endif1713#ifdef CONFIG_EDAC_ALTERA_USB1714 { .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data },1715#endif1716#ifdef CONFIG_EDAC_ALTERA_QSPI1717 { .compatible = "altr,socfpga-qspi-ecc", .data = &a10_qspiecc_data },1718#endif1719#ifdef CONFIG_EDAC_ALTERA_SDMMC1720 { .compatible = "altr,socfpga-sdmmc-ecc", .data = &a10_sdmmcecca_data },1721#endif1722#ifdef CONFIG_EDAC_ALTERA_SDRAM1723 { .compatible = "altr,sdram-edac-s10", .data = &s10_sdramecc_data },1724#endif1725 {},1726};1727MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match);1728 1729/*1730 * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria51731 * because 2 IRQs are shared among the all ECC peripherals. The ECC1732 * manager manages the IRQs and the children.1733 * Based on xgene_edac.c peripheral code.1734 */1735 1736static ssize_t __maybe_unused1737altr_edac_a10_device_trig(struct file *file, const char __user *user_buf,1738 size_t count, loff_t *ppos)1739{1740 struct edac_device_ctl_info *edac_dci = file->private_data;1741 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;1742 const struct edac_device_prv_data *priv = drvdata->data;1743 void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);1744 unsigned long flags;1745 u8 trig_type;1746 1747 if (!user_buf || get_user(trig_type, user_buf))1748 return -EFAULT;1749 1750 local_irq_save(flags);1751 if (trig_type == ALTR_UE_TRIGGER_CHAR)1752 writel(priv->ue_set_mask, set_addr);1753 else1754 writel(priv->ce_set_mask, set_addr);1755 1756 /* Ensure the interrupt test bits are set */1757 wmb();1758 local_irq_restore(flags);1759 1760 return count;1761}1762 1763/*1764 * The Stratix10 EDAC Error Injection Functions differ from Arria101765 * slightly. A few Arria10 peripherals can use this injection function.1766 * Inject the error into the memory and then readback to trigger the IRQ.1767 */1768static ssize_t __maybe_unused1769altr_edac_a10_device_trig2(struct file *file, const char __user *user_buf,1770 size_t count, loff_t *ppos)1771{1772 struct edac_device_ctl_info *edac_dci = file->private_data;1773 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;1774 const struct edac_device_prv_data *priv = drvdata->data;1775 void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);1776 unsigned long flags;1777 u8 trig_type;1778 1779 if (!user_buf || get_user(trig_type, user_buf))1780 return -EFAULT;1781 1782 local_irq_save(flags);1783 if (trig_type == ALTR_UE_TRIGGER_CHAR) {1784 writel(priv->ue_set_mask, set_addr);1785 } else {1786 /* Setup read/write of 4 bytes */1787 writel(ECC_WORD_WRITE, drvdata->base + ECC_BLK_DBYTECTRL_OFST);1788 /* Setup Address to 0 */1789 writel(0, drvdata->base + ECC_BLK_ADDRESS_OFST);1790 /* Setup accctrl to read & ecc & data override */1791 writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);1792 /* Kick it. */1793 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);1794 /* Setup write for single bit change */1795 writel(readl(drvdata->base + ECC_BLK_RDATA0_OFST) ^ 0x1,1796 drvdata->base + ECC_BLK_WDATA0_OFST);1797 writel(readl(drvdata->base + ECC_BLK_RDATA1_OFST),1798 drvdata->base + ECC_BLK_WDATA1_OFST);1799 writel(readl(drvdata->base + ECC_BLK_RDATA2_OFST),1800 drvdata->base + ECC_BLK_WDATA2_OFST);1801 writel(readl(drvdata->base + ECC_BLK_RDATA3_OFST),1802 drvdata->base + ECC_BLK_WDATA3_OFST);1803 1804 /* Copy Read ECC to Write ECC */1805 writel(readl(drvdata->base + ECC_BLK_RECC0_OFST),1806 drvdata->base + ECC_BLK_WECC0_OFST);1807 writel(readl(drvdata->base + ECC_BLK_RECC1_OFST),1808 drvdata->base + ECC_BLK_WECC1_OFST);1809 /* Setup accctrl to write & ecc override & data override */1810 writel(ECC_WRITE_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);1811 /* Kick it. */1812 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);1813 /* Setup accctrl to read & ecc overwrite & data overwrite */1814 writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);1815 /* Kick it. */1816 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);1817 }1818 1819 /* Ensure the interrupt test bits are set */1820 wmb();1821 local_irq_restore(flags);1822 1823 return count;1824}1825 1826static void altr_edac_a10_irq_handler(struct irq_desc *desc)1827{1828 int dberr, bit, sm_offset, irq_status;1829 struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc);1830 struct irq_chip *chip = irq_desc_get_chip(desc);1831 int irq = irq_desc_get_irq(desc);1832 unsigned long bits;1833 1834 dberr = (irq == edac->db_irq) ? 1 : 0;1835 sm_offset = dberr ? A10_SYSMGR_ECC_INTSTAT_DERR_OFST :1836 A10_SYSMGR_ECC_INTSTAT_SERR_OFST;1837 1838 chained_irq_enter(chip, desc);1839 1840 regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status);1841 1842 bits = irq_status;1843 for_each_set_bit(bit, &bits, 32)1844 generic_handle_domain_irq(edac->domain, dberr * 32 + bit);1845 1846 chained_irq_exit(chip, desc);1847}1848 1849static int validate_parent_available(struct device_node *np)1850{1851 struct device_node *parent;1852 int ret = 0;1853 1854 /* SDRAM must be present for Linux (implied parent) */1855 if (of_device_is_compatible(np, "altr,sdram-edac-s10"))1856 return 0;1857 1858 /* Ensure parent device is enabled if parent node exists */1859 parent = of_parse_phandle(np, "altr,ecc-parent", 0);1860 if (parent && !of_device_is_available(parent))1861 ret = -ENODEV;1862 1863 of_node_put(parent);1864 return ret;1865}1866 1867static int get_s10_sdram_edac_resource(struct device_node *np,1868 struct resource *res)1869{1870 struct device_node *parent;1871 int ret;1872 1873 parent = of_parse_phandle(np, "altr,sdr-syscon", 0);1874 if (!parent)1875 return -ENODEV;1876 1877 ret = of_address_to_resource(parent, 0, res);1878 of_node_put(parent);1879 1880 return ret;1881}1882 1883static int altr_edac_a10_device_add(struct altr_arria10_edac *edac,1884 struct device_node *np)1885{1886 struct edac_device_ctl_info *dci;1887 struct altr_edac_device_dev *altdev;1888 char *ecc_name = (char *)np->name;1889 struct resource res;1890 int edac_idx;1891 int rc = 0;1892 const struct edac_device_prv_data *prv;1893 /* Get matching node and check for valid result */1894 const struct of_device_id *pdev_id =1895 of_match_node(altr_edac_a10_device_of_match, np);1896 if (IS_ERR_OR_NULL(pdev_id))1897 return -ENODEV;1898 1899 /* Get driver specific data for this EDAC device */1900 prv = pdev_id->data;1901 if (IS_ERR_OR_NULL(prv))1902 return -ENODEV;1903 1904 if (validate_parent_available(np))1905 return -ENODEV;1906 1907 if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL))1908 return -ENOMEM;1909 1910 if (of_device_is_compatible(np, "altr,sdram-edac-s10"))1911 rc = get_s10_sdram_edac_resource(np, &res);1912 else1913 rc = of_address_to_resource(np, 0, &res);1914 1915 if (rc < 0) {1916 edac_printk(KERN_ERR, EDAC_DEVICE,1917 "%s: no resource address\n", ecc_name);1918 goto err_release_group;1919 }1920 1921 edac_idx = edac_device_alloc_index();1922 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name,1923 1, ecc_name, 1, 0, edac_idx);1924 1925 if (!dci) {1926 edac_printk(KERN_ERR, EDAC_DEVICE,1927 "%s: Unable to allocate EDAC device\n", ecc_name);1928 rc = -ENOMEM;1929 goto err_release_group;1930 }1931 1932 altdev = dci->pvt_info;1933 dci->dev = edac->dev;1934 altdev->edac_dev_name = ecc_name;1935 altdev->edac_idx = edac_idx;1936 altdev->edac = edac;1937 altdev->edac_dev = dci;1938 altdev->data = prv;1939 altdev->ddev = *edac->dev;1940 dci->dev = &altdev->ddev;1941 dci->ctl_name = "Altera ECC Manager";1942 dci->mod_name = ecc_name;1943 dci->dev_name = ecc_name;1944 1945 altdev->base = devm_ioremap_resource(edac->dev, &res);1946 if (IS_ERR(altdev->base)) {1947 rc = PTR_ERR(altdev->base);1948 goto err_release_group1;1949 }1950 1951 /* Check specific dependencies for the module */1952 if (altdev->data->setup) {1953 rc = altdev->data->setup(altdev);1954 if (rc)1955 goto err_release_group1;1956 }1957 1958 altdev->sb_irq = irq_of_parse_and_map(np, 0);1959 if (!altdev->sb_irq) {1960 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating SBIRQ\n");1961 rc = -ENODEV;1962 goto err_release_group1;1963 }1964 rc = devm_request_irq(edac->dev, altdev->sb_irq, prv->ecc_irq_handler,1965 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,1966 ecc_name, altdev);1967 if (rc) {1968 edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n");1969 goto err_release_group1;1970 }1971 1972#ifdef CONFIG_64BIT1973 /* Use IRQ to determine SError origin instead of assigning IRQ */1974 rc = of_property_read_u32_index(np, "interrupts", 0, &altdev->db_irq);1975 if (rc) {1976 edac_printk(KERN_ERR, EDAC_DEVICE,1977 "Unable to parse DB IRQ index\n");1978 goto err_release_group1;1979 }1980#else1981 altdev->db_irq = irq_of_parse_and_map(np, 1);1982 if (!altdev->db_irq) {1983 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating DBIRQ\n");1984 rc = -ENODEV;1985 goto err_release_group1;1986 }1987 rc = devm_request_irq(edac->dev, altdev->db_irq, prv->ecc_irq_handler,1988 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,1989 ecc_name, altdev);1990 if (rc) {1991 edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n");1992 goto err_release_group1;1993 }1994#endif1995 1996 rc = edac_device_add_device(dci);1997 if (rc) {1998 dev_err(edac->dev, "edac_device_add_device failed\n");1999 rc = -ENOMEM;2000 goto err_release_group1;2001 }2002 2003 altr_create_edacdev_dbgfs(dci, prv);2004 2005 list_add(&altdev->next, &edac->a10_ecc_devices);2006 2007 devres_remove_group(edac->dev, altr_edac_a10_device_add);2008 2009 return 0;2010 2011err_release_group1:2012 edac_device_free_ctl_info(dci);2013err_release_group:2014 devres_release_group(edac->dev, NULL);2015 edac_printk(KERN_ERR, EDAC_DEVICE,2016 "%s:Error setting up EDAC device: %d\n", ecc_name, rc);2017 2018 return rc;2019}2020 2021static void a10_eccmgr_irq_mask(struct irq_data *d)2022{2023 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);2024 2025 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST,2026 BIT(d->hwirq));2027}2028 2029static void a10_eccmgr_irq_unmask(struct irq_data *d)2030{2031 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);2032 2033 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST,2034 BIT(d->hwirq));2035}2036 2037static int a10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq,2038 irq_hw_number_t hwirq)2039{2040 struct altr_arria10_edac *edac = d->host_data;2041 2042 irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq);2043 irq_set_chip_data(irq, edac);2044 irq_set_noprobe(irq);2045 2046 return 0;2047}2048 2049static const struct irq_domain_ops a10_eccmgr_ic_ops = {2050 .map = a10_eccmgr_irqdomain_map,2051 .xlate = irq_domain_xlate_twocell,2052};2053 2054/************** Stratix 10 EDAC Double Bit Error Handler ************/2055#define to_a10edac(p, m) container_of(p, struct altr_arria10_edac, m)2056 2057#ifdef CONFIG_64BIT2058/* panic routine issues reboot on non-zero panic_timeout */2059extern int panic_timeout;2060 2061/*2062 * The double bit error is handled through SError which is fatal. This is2063 * called as a panic notifier to printout ECC error info as part of the panic.2064 */2065static int s10_edac_dberr_handler(struct notifier_block *this,2066 unsigned long event, void *ptr)2067{2068 struct altr_arria10_edac *edac = to_a10edac(this, panic_notifier);2069 int err_addr, dberror;2070 2071 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_ECC_INTSTAT_DERR_OFST,2072 &dberror);2073 regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST, dberror);2074 if (dberror & S10_DBE_IRQ_MASK) {2075 struct list_head *position;2076 struct altr_edac_device_dev *ed;2077 struct arm_smccc_res result;2078 2079 /* Find the matching DBE in the list of devices */2080 list_for_each(position, &edac->a10_ecc_devices) {2081 ed = list_entry(position, struct altr_edac_device_dev,2082 next);2083 if (!(BIT(ed->db_irq) & dberror))2084 continue;2085 2086 writel(ALTR_A10_ECC_DERRPENA,2087 ed->base + ALTR_A10_ECC_INTSTAT_OFST);2088 err_addr = readl(ed->base + ALTR_S10_DERR_ADDRA_OFST);2089 regmap_write(edac->ecc_mgr_map,2090 S10_SYSMGR_UE_ADDR_OFST, err_addr);2091 edac_printk(KERN_ERR, EDAC_DEVICE,2092 "EDAC: [Fatal DBE on %s @ 0x%08X]\n",2093 ed->edac_dev_name, err_addr);2094 break;2095 }2096 /* Notify the System through SMC. Reboot delay = 1 second */2097 panic_timeout = 1;2098 arm_smccc_smc(INTEL_SIP_SMC_ECC_DBE, dberror, 0, 0, 0, 0,2099 0, 0, &result);2100 }2101 2102 return NOTIFY_DONE;2103}2104#endif2105 2106/****************** Arria 10 EDAC Probe Function *********************/2107static int altr_edac_a10_probe(struct platform_device *pdev)2108{2109 struct altr_arria10_edac *edac;2110 struct device_node *child;2111 2112 edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL);2113 if (!edac)2114 return -ENOMEM;2115 2116 edac->dev = &pdev->dev;2117 platform_set_drvdata(pdev, edac);2118 INIT_LIST_HEAD(&edac->a10_ecc_devices);2119 2120 edac->ecc_mgr_map =2121 altr_sysmgr_regmap_lookup_by_phandle(pdev->dev.of_node,2122 "altr,sysmgr-syscon");2123 2124 if (IS_ERR(edac->ecc_mgr_map)) {2125 edac_printk(KERN_ERR, EDAC_DEVICE,2126 "Unable to get syscon altr,sysmgr-syscon\n");2127 return PTR_ERR(edac->ecc_mgr_map);2128 }2129 2130 edac->irq_chip.name = pdev->dev.of_node->name;2131 edac->irq_chip.irq_mask = a10_eccmgr_irq_mask;2132 edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask;2133 edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64,2134 &a10_eccmgr_ic_ops, edac);2135 if (!edac->domain) {2136 dev_err(&pdev->dev, "Error adding IRQ domain\n");2137 return -ENOMEM;2138 }2139 2140 edac->sb_irq = platform_get_irq(pdev, 0);2141 if (edac->sb_irq < 0)2142 return edac->sb_irq;2143 2144 irq_set_chained_handler_and_data(edac->sb_irq,2145 altr_edac_a10_irq_handler,2146 edac);2147 2148#ifdef CONFIG_64BIT2149 {2150 int dberror, err_addr;2151 2152 edac->panic_notifier.notifier_call = s10_edac_dberr_handler;2153 atomic_notifier_chain_register(&panic_notifier_list,2154 &edac->panic_notifier);2155 2156 /* Printout a message if uncorrectable error previously. */2157 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST,2158 &dberror);2159 if (dberror) {2160 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_ADDR_OFST,2161 &err_addr);2162 edac_printk(KERN_ERR, EDAC_DEVICE,2163 "Previous Boot UE detected[0x%X] @ 0x%X\n",2164 dberror, err_addr);2165 /* Reset the sticky registers */2166 regmap_write(edac->ecc_mgr_map,2167 S10_SYSMGR_UE_VAL_OFST, 0);2168 regmap_write(edac->ecc_mgr_map,2169 S10_SYSMGR_UE_ADDR_OFST, 0);2170 }2171 }2172#else2173 edac->db_irq = platform_get_irq(pdev, 1);2174 if (edac->db_irq < 0)2175 return edac->db_irq;2176 2177 irq_set_chained_handler_and_data(edac->db_irq,2178 altr_edac_a10_irq_handler, edac);2179#endif2180 2181 for_each_child_of_node(pdev->dev.of_node, child) {2182 if (!of_device_is_available(child))2183 continue;2184 2185 if (of_match_node(altr_edac_a10_device_of_match, child))2186 altr_edac_a10_device_add(edac, child);2187 2188#ifdef CONFIG_EDAC_ALTERA_SDRAM2189 else if (of_device_is_compatible(child, "altr,sdram-edac-a10"))2190 of_platform_populate(pdev->dev.of_node,2191 altr_sdram_ctrl_of_match,2192 NULL, &pdev->dev);2193#endif2194 }2195 2196 return 0;2197}2198 2199static const struct of_device_id altr_edac_a10_of_match[] = {2200 { .compatible = "altr,socfpga-a10-ecc-manager" },2201 { .compatible = "altr,socfpga-s10-ecc-manager" },2202 {},2203};2204MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match);2205 2206static struct platform_driver altr_edac_a10_driver = {2207 .probe = altr_edac_a10_probe,2208 .driver = {2209 .name = "socfpga_a10_ecc_manager",2210 .of_match_table = altr_edac_a10_of_match,2211 },2212};2213module_platform_driver(altr_edac_a10_driver);2214 2215MODULE_AUTHOR("Thor Thayer");2216MODULE_DESCRIPTION("EDAC Driver for Altera Memories");2217