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1/*2 * Intel 3000/3010 Memory Controller kernel module3 * Copyright (C) 2007 Akamai Technologies, Inc.4 * Shamelessly copied from:5 * Intel D82875P Memory Controller kernel module6 * (C) 2003 Linux Networx (http://lnxi.com)7 *8 * This file may be distributed under the terms of the9 * GNU General Public License.10 */11 12#include <linux/module.h>13#include <linux/init.h>14#include <linux/pci.h>15#include <linux/pci_ids.h>16#include <linux/edac.h>17#include "edac_module.h"18 19#define EDAC_MOD_STR "i3000_edac"20 21#define I3000_RANKS 822#define I3000_RANKS_PER_CHANNEL 423#define I3000_CHANNELS 224 25/* Intel 3000 register addresses - device 0 function 0 - DRAM Controller */26 27#define I3000_MCHBAR 0x44 /* MCH Memory Mapped Register BAR */28#define I3000_MCHBAR_MASK 0xffffc00029#define I3000_MMR_WINDOW_SIZE 1638430 31#define I3000_EDEAP 0x70 /* Extended DRAM Error Address Pointer (8b)32 *33 * 7:1 reserved34 * 0 bit 32 of address35 */36#define I3000_DEAP 0x58 /* DRAM Error Address Pointer (32b)37 *38 * 31:7 address39 * 6:1 reserved40 * 0 Error channel 0/141 */42#define I3000_DEAP_GRAIN (1 << 7)43 44/*45 * Helper functions to decode the DEAP/EDEAP hardware registers.46 *47 * The type promotion here is deliberate; we're deriving an48 * unsigned long pfn and offset from hardware regs which are u8/u32.49 */50 51static inline unsigned long deap_pfn(u8 edeap, u32 deap)52{53 deap >>= PAGE_SHIFT;54 deap |= (edeap & 1) << (32 - PAGE_SHIFT);55 return deap;56}57 58static inline unsigned long deap_offset(u32 deap)59{60 return deap & ~(I3000_DEAP_GRAIN - 1) & ~PAGE_MASK;61}62 63static inline int deap_channel(u32 deap)64{65 return deap & 1;66}67 68#define I3000_DERRSYN 0x5c /* DRAM Error Syndrome (8b)69 *70 * 7:0 DRAM ECC Syndrome71 */72 73#define I3000_ERRSTS 0xc8 /* Error Status Register (16b)74 *75 * 15:12 reserved76 * 11 MCH Thermal Sensor Event77 * for SMI/SCI/SERR78 * 10 reserved79 * 9 LOCK to non-DRAM Memory Flag (LCKF)80 * 8 Received Refresh Timeout Flag (RRTOF)81 * 7:2 reserved82 * 1 Multi-bit DRAM ECC Error Flag (DMERR)83 * 0 Single-bit DRAM ECC Error Flag (DSERR)84 */85#define I3000_ERRSTS_BITS 0x0b03 /* bits which indicate errors */86#define I3000_ERRSTS_UE 0x000287#define I3000_ERRSTS_CE 0x000188 89#define I3000_ERRCMD 0xca /* Error Command (16b)90 *91 * 15:12 reserved92 * 11 SERR on MCH Thermal Sensor Event93 * (TSESERR)94 * 10 reserved95 * 9 SERR on LOCK to non-DRAM Memory96 * (LCKERR)97 * 8 SERR on DRAM Refresh Timeout98 * (DRTOERR)99 * 7:2 reserved100 * 1 SERR Multi-Bit DRAM ECC Error101 * (DMERR)102 * 0 SERR on Single-Bit ECC Error103 * (DSERR)104 */105 106/* Intel MMIO register space - device 0 function 0 - MMR space */107 108#define I3000_DRB_SHIFT 25 /* 32MiB grain */109 110#define I3000_C0DRB 0x100 /* Channel 0 DRAM Rank Boundary (8b x 4)111 *112 * 7:0 Channel 0 DRAM Rank Boundary Address113 */114#define I3000_C1DRB 0x180 /* Channel 1 DRAM Rank Boundary (8b x 4)115 *116 * 7:0 Channel 1 DRAM Rank Boundary Address117 */118 119#define I3000_C0DRA 0x108 /* Channel 0 DRAM Rank Attribute (8b x 2)120 *121 * 7 reserved122 * 6:4 DRAM odd Rank Attribute123 * 3 reserved124 * 2:0 DRAM even Rank Attribute125 *126 * Each attribute defines the page127 * size of the corresponding rank:128 * 000: unpopulated129 * 001: reserved130 * 010: 4 KB131 * 011: 8 KB132 * 100: 16 KB133 * Others: reserved134 */135#define I3000_C1DRA 0x188 /* Channel 1 DRAM Rank Attribute (8b x 2) */136 137static inline unsigned char odd_rank_attrib(unsigned char dra)138{139 return (dra & 0x70) >> 4;140}141 142static inline unsigned char even_rank_attrib(unsigned char dra)143{144 return dra & 0x07;145}146 147#define I3000_C0DRC0 0x120 /* DRAM Controller Mode 0 (32b)148 *149 * 31:30 reserved150 * 29 Initialization Complete (IC)151 * 28:11 reserved152 * 10:8 Refresh Mode Select (RMS)153 * 7 reserved154 * 6:4 Mode Select (SMS)155 * 3:2 reserved156 * 1:0 DRAM Type (DT)157 */158 159#define I3000_C0DRC1 0x124 /* DRAM Controller Mode 1 (32b)160 *161 * 31 Enhanced Addressing Enable (ENHADE)162 * 30:0 reserved163 */164 165enum i3000p_chips {166 I3000 = 0,167};168 169struct i3000_dev_info {170 const char *ctl_name;171};172 173struct i3000_error_info {174 u16 errsts;175 u8 derrsyn;176 u8 edeap;177 u32 deap;178 u16 errsts2;179};180 181static const struct i3000_dev_info i3000_devs[] = {182 [I3000] = {183 .ctl_name = "i3000"},184};185 186static struct pci_dev *mci_pdev;187static int i3000_registered = 1;188static struct edac_pci_ctl_info *i3000_pci;189 190static void i3000_get_error_info(struct mem_ctl_info *mci,191 struct i3000_error_info *info)192{193 struct pci_dev *pdev;194 195 pdev = to_pci_dev(mci->pdev);196 197 /*198 * This is a mess because there is no atomic way to read all the199 * registers at once and the registers can transition from CE being200 * overwritten by UE.201 */202 pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts);203 if (!(info->errsts & I3000_ERRSTS_BITS))204 return;205 pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap);206 pci_read_config_dword(pdev, I3000_DEAP, &info->deap);207 pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn);208 pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts2);209 210 /*211 * If the error is the same for both reads then the first set212 * of reads is valid. If there is a change then there is a CE213 * with no info and the second set of reads is valid and214 * should be UE info.215 */216 if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) {217 pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap);218 pci_read_config_dword(pdev, I3000_DEAP, &info->deap);219 pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn);220 }221 222 /*223 * Clear any error bits.224 * (Yes, we really clear bits by writing 1 to them.)225 */226 pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,227 I3000_ERRSTS_BITS);228}229 230static int i3000_process_error_info(struct mem_ctl_info *mci,231 struct i3000_error_info *info,232 int handle_errors)233{234 int row, multi_chan, channel;235 unsigned long pfn, offset;236 237 multi_chan = mci->csrows[0]->nr_channels - 1;238 239 if (!(info->errsts & I3000_ERRSTS_BITS))240 return 0;241 242 if (!handle_errors)243 return 1;244 245 if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) {246 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,247 -1, -1, -1,248 "UE overwrote CE", "");249 info->errsts = info->errsts2;250 }251 252 pfn = deap_pfn(info->edeap, info->deap);253 offset = deap_offset(info->deap);254 channel = deap_channel(info->deap);255 256 row = edac_mc_find_csrow_by_page(mci, pfn);257 258 if (info->errsts & I3000_ERRSTS_UE)259 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,260 pfn, offset, 0,261 row, -1, -1,262 "i3000 UE", "");263 else264 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,265 pfn, offset, info->derrsyn,266 row, multi_chan ? channel : 0, -1,267 "i3000 CE", "");268 269 return 1;270}271 272static void i3000_check(struct mem_ctl_info *mci)273{274 struct i3000_error_info info;275 276 i3000_get_error_info(mci, &info);277 i3000_process_error_info(mci, &info, 1);278}279 280static int i3000_is_interleaved(const unsigned char *c0dra,281 const unsigned char *c1dra,282 const unsigned char *c0drb,283 const unsigned char *c1drb)284{285 int i;286 287 /*288 * If the channels aren't populated identically then289 * we're not interleaved.290 */291 for (i = 0; i < I3000_RANKS_PER_CHANNEL / 2; i++)292 if (odd_rank_attrib(c0dra[i]) != odd_rank_attrib(c1dra[i]) ||293 even_rank_attrib(c0dra[i]) !=294 even_rank_attrib(c1dra[i]))295 return 0;296 297 /*298 * If the rank boundaries for the two channels are different299 * then we're not interleaved.300 */301 for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++)302 if (c0drb[i] != c1drb[i])303 return 0;304 305 return 1;306}307 308static int i3000_probe1(struct pci_dev *pdev, int dev_idx)309{310 int rc;311 int i, j;312 struct mem_ctl_info *mci = NULL;313 struct edac_mc_layer layers[2];314 unsigned long last_cumul_size, nr_pages;315 int interleaved, nr_channels;316 unsigned char dra[I3000_RANKS / 2], drb[I3000_RANKS];317 unsigned char *c0dra = dra, *c1dra = &dra[I3000_RANKS_PER_CHANNEL / 2];318 unsigned char *c0drb = drb, *c1drb = &drb[I3000_RANKS_PER_CHANNEL];319 unsigned long mchbar;320 void __iomem *window;321 322 edac_dbg(0, "MC:\n");323 324 pci_read_config_dword(pdev, I3000_MCHBAR, (u32 *) & mchbar);325 mchbar &= I3000_MCHBAR_MASK;326 window = ioremap(mchbar, I3000_MMR_WINDOW_SIZE);327 if (!window) {328 printk(KERN_ERR "i3000: cannot map mmio space at 0x%lx\n",329 mchbar);330 return -ENODEV;331 }332 333 c0dra[0] = readb(window + I3000_C0DRA + 0); /* ranks 0,1 */334 c0dra[1] = readb(window + I3000_C0DRA + 1); /* ranks 2,3 */335 c1dra[0] = readb(window + I3000_C1DRA + 0); /* ranks 0,1 */336 c1dra[1] = readb(window + I3000_C1DRA + 1); /* ranks 2,3 */337 338 for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++) {339 c0drb[i] = readb(window + I3000_C0DRB + i);340 c1drb[i] = readb(window + I3000_C1DRB + i);341 }342 343 iounmap(window);344 345 /*346 * Figure out how many channels we have.347 *348 * If we have what the datasheet calls "asymmetric channels"349 * (essentially the same as what was called "virtual single350 * channel mode" in the i82875) then it's a single channel as351 * far as EDAC is concerned.352 */353 interleaved = i3000_is_interleaved(c0dra, c1dra, c0drb, c1drb);354 nr_channels = interleaved ? 2 : 1;355 356 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;357 layers[0].size = I3000_RANKS / nr_channels;358 layers[0].is_virt_csrow = true;359 layers[1].type = EDAC_MC_LAYER_CHANNEL;360 layers[1].size = nr_channels;361 layers[1].is_virt_csrow = false;362 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);363 if (!mci)364 return -ENOMEM;365 366 edac_dbg(3, "MC: init mci\n");367 368 mci->pdev = &pdev->dev;369 mci->mtype_cap = MEM_FLAG_DDR2;370 371 mci->edac_ctl_cap = EDAC_FLAG_SECDED;372 mci->edac_cap = EDAC_FLAG_SECDED;373 374 mci->mod_name = EDAC_MOD_STR;375 mci->ctl_name = i3000_devs[dev_idx].ctl_name;376 mci->dev_name = pci_name(pdev);377 mci->edac_check = i3000_check;378 mci->ctl_page_to_phys = NULL;379 380 /*381 * The dram rank boundary (DRB) reg values are boundary addresses382 * for each DRAM rank with a granularity of 32MB. DRB regs are383 * cumulative; the last one will contain the total memory384 * contained in all ranks.385 *386 * If we're in interleaved mode then we're only walking through387 * the ranks of controller 0, so we double all the values we see.388 */389 for (last_cumul_size = i = 0; i < mci->nr_csrows; i++) {390 u8 value;391 u32 cumul_size;392 struct csrow_info *csrow = mci->csrows[i];393 394 value = drb[i];395 cumul_size = value << (I3000_DRB_SHIFT - PAGE_SHIFT);396 if (interleaved)397 cumul_size <<= 1;398 edac_dbg(3, "MC: (%d) cumul_size 0x%x\n", i, cumul_size);399 if (cumul_size == last_cumul_size)400 continue;401 402 csrow->first_page = last_cumul_size;403 csrow->last_page = cumul_size - 1;404 nr_pages = cumul_size - last_cumul_size;405 last_cumul_size = cumul_size;406 407 for (j = 0; j < nr_channels; j++) {408 struct dimm_info *dimm = csrow->channels[j]->dimm;409 410 dimm->nr_pages = nr_pages / nr_channels;411 dimm->grain = I3000_DEAP_GRAIN;412 dimm->mtype = MEM_DDR2;413 dimm->dtype = DEV_UNKNOWN;414 dimm->edac_mode = EDAC_UNKNOWN;415 }416 }417 418 /*419 * Clear any error bits.420 * (Yes, we really clear bits by writing 1 to them.)421 */422 pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,423 I3000_ERRSTS_BITS);424 425 rc = -ENODEV;426 if (edac_mc_add_mc(mci)) {427 edac_dbg(3, "MC: failed edac_mc_add_mc()\n");428 goto fail;429 }430 431 /* allocating generic PCI control info */432 i3000_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);433 if (!i3000_pci) {434 printk(KERN_WARNING435 "%s(): Unable to create PCI control\n",436 __func__);437 printk(KERN_WARNING438 "%s(): PCI error report via EDAC not setup\n",439 __func__);440 }441 442 /* get this far and it's successful */443 edac_dbg(3, "MC: success\n");444 return 0;445 446fail:447 if (mci)448 edac_mc_free(mci);449 450 return rc;451}452 453/* returns count (>= 0), or negative on error */454static int i3000_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)455{456 int rc;457 458 edac_dbg(0, "MC:\n");459 460 if (pci_enable_device(pdev) < 0)461 return -EIO;462 463 rc = i3000_probe1(pdev, ent->driver_data);464 if (!mci_pdev)465 mci_pdev = pci_dev_get(pdev);466 467 return rc;468}469 470static void i3000_remove_one(struct pci_dev *pdev)471{472 struct mem_ctl_info *mci;473 474 edac_dbg(0, "\n");475 476 if (i3000_pci)477 edac_pci_release_generic_ctl(i3000_pci);478 479 mci = edac_mc_del_mc(&pdev->dev);480 if (!mci)481 return;482 483 edac_mc_free(mci);484}485 486static const struct pci_device_id i3000_pci_tbl[] = {487 {488 PCI_VEND_DEV(INTEL, 3000_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,489 I3000},490 {491 0,492 } /* 0 terminated list. */493};494 495MODULE_DEVICE_TABLE(pci, i3000_pci_tbl);496 497static struct pci_driver i3000_driver = {498 .name = EDAC_MOD_STR,499 .probe = i3000_init_one,500 .remove = i3000_remove_one,501 .id_table = i3000_pci_tbl,502};503 504static int __init i3000_init(void)505{506 int pci_rc;507 508 edac_dbg(3, "MC:\n");509 510 /* Ensure that the OPSTATE is set correctly for POLL or NMI */511 opstate_init();512 513 pci_rc = pci_register_driver(&i3000_driver);514 if (pci_rc < 0)515 goto fail0;516 517 if (!mci_pdev) {518 i3000_registered = 0;519 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,520 PCI_DEVICE_ID_INTEL_3000_HB, NULL);521 if (!mci_pdev) {522 edac_dbg(0, "i3000 pci_get_device fail\n");523 pci_rc = -ENODEV;524 goto fail1;525 }526 527 pci_rc = i3000_init_one(mci_pdev, i3000_pci_tbl);528 if (pci_rc < 0) {529 edac_dbg(0, "i3000 init fail\n");530 pci_rc = -ENODEV;531 goto fail1;532 }533 }534 535 return 0;536 537fail1:538 pci_unregister_driver(&i3000_driver);539 540fail0:541 pci_dev_put(mci_pdev);542 543 return pci_rc;544}545 546static void __exit i3000_exit(void)547{548 edac_dbg(3, "MC:\n");549 550 pci_unregister_driver(&i3000_driver);551 if (!i3000_registered) {552 i3000_remove_one(mci_pdev);553 pci_dev_put(mci_pdev);554 }555}556 557module_init(i3000_init);558module_exit(i3000_exit);559 560MODULE_LICENSE("GPL");561MODULE_AUTHOR("Akamai Technologies Arthur Ulfeldt/Jason Uhlenkott");562MODULE_DESCRIPTION("MC support for Intel 3000 memory hub controllers");563 564module_param(edac_op_state, int, 0444);565MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");566