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1/*2 * Intel 5100 Memory Controllers kernel module3 *4 * This file may be distributed under the terms of the5 * GNU General Public License.6 *7 * This module is based on the following document:8 *9 * Intel 5100X Chipset Memory Controller Hub (MCH) - Datasheet10 * http://download.intel.com/design/chipsets/datashts/318378.pdf11 *12 * The intel 5100 has two independent channels. EDAC core currently13 * can not reflect this configuration so instead the chip-select14 * rows for each respective channel are laid out one after another,15 * the first half belonging to channel 0, the second half belonging16 * to channel 1.17 *18 * This driver is for DDR2 DIMMs, and it uses chip select to select among the19 * several ranks. However, instead of showing memories as ranks, it outputs20 * them as DIMM's. An internal table creates the association between ranks21 * and DIMM's.22 */23#include <linux/module.h>24#include <linux/init.h>25#include <linux/pci.h>26#include <linux/pci_ids.h>27#include <linux/edac.h>28#include <linux/delay.h>29#include <linux/mmzone.h>30#include <linux/debugfs.h>31 32#include "edac_module.h"33 34/* register addresses */35 36/* device 16, func 1 */37#define I5100_MC 0x40 /* Memory Control Register */38#define I5100_MC_SCRBEN_MASK (1 << 7)39#define I5100_MC_SCRBDONE_MASK (1 << 4)40#define I5100_MS 0x44 /* Memory Status Register */41#define I5100_SPDDATA 0x48 /* Serial Presence Detect Status Reg */42#define I5100_SPDCMD 0x4c /* Serial Presence Detect Command Reg */43#define I5100_TOLM 0x6c /* Top of Low Memory */44#define I5100_MIR0 0x80 /* Memory Interleave Range 0 */45#define I5100_MIR1 0x84 /* Memory Interleave Range 1 */46#define I5100_AMIR_0 0x8c /* Adjusted Memory Interleave Range 0 */47#define I5100_AMIR_1 0x90 /* Adjusted Memory Interleave Range 1 */48#define I5100_FERR_NF_MEM 0xa0 /* MC First Non Fatal Errors */49#define I5100_FERR_NF_MEM_M16ERR_MASK (1 << 16)50#define I5100_FERR_NF_MEM_M15ERR_MASK (1 << 15)51#define I5100_FERR_NF_MEM_M14ERR_MASK (1 << 14)52#define I5100_FERR_NF_MEM_M12ERR_MASK (1 << 12)53#define I5100_FERR_NF_MEM_M11ERR_MASK (1 << 11)54#define I5100_FERR_NF_MEM_M10ERR_MASK (1 << 10)55#define I5100_FERR_NF_MEM_M6ERR_MASK (1 << 6)56#define I5100_FERR_NF_MEM_M5ERR_MASK (1 << 5)57#define I5100_FERR_NF_MEM_M4ERR_MASK (1 << 4)58#define I5100_FERR_NF_MEM_M1ERR_MASK (1 << 1)59#define I5100_FERR_NF_MEM_ANY_MASK \60 (I5100_FERR_NF_MEM_M16ERR_MASK | \61 I5100_FERR_NF_MEM_M15ERR_MASK | \62 I5100_FERR_NF_MEM_M14ERR_MASK | \63 I5100_FERR_NF_MEM_M12ERR_MASK | \64 I5100_FERR_NF_MEM_M11ERR_MASK | \65 I5100_FERR_NF_MEM_M10ERR_MASK | \66 I5100_FERR_NF_MEM_M6ERR_MASK | \67 I5100_FERR_NF_MEM_M5ERR_MASK | \68 I5100_FERR_NF_MEM_M4ERR_MASK | \69 I5100_FERR_NF_MEM_M1ERR_MASK)70#define I5100_NERR_NF_MEM 0xa4 /* MC Next Non-Fatal Errors */71#define I5100_EMASK_MEM 0xa8 /* MC Error Mask Register */72#define I5100_MEM0EINJMSK0 0x200 /* Injection Mask0 Register Channel 0 */73#define I5100_MEM1EINJMSK0 0x208 /* Injection Mask0 Register Channel 1 */74#define I5100_MEMXEINJMSK0_EINJEN (1 << 27)75#define I5100_MEM0EINJMSK1 0x204 /* Injection Mask1 Register Channel 0 */76#define I5100_MEM1EINJMSK1 0x206 /* Injection Mask1 Register Channel 1 */77 78/* Device 19, Function 0 */79#define I5100_DINJ0 0x9a80 81/* device 21 and 22, func 0 */82#define I5100_MTR_0 0x154 /* Memory Technology Registers 0-3 */83#define I5100_DMIR 0x15c /* DIMM Interleave Range */84#define I5100_VALIDLOG 0x18c /* Valid Log Markers */85#define I5100_NRECMEMA 0x190 /* Non-Recoverable Memory Error Log Reg A */86#define I5100_NRECMEMB 0x194 /* Non-Recoverable Memory Error Log Reg B */87#define I5100_REDMEMA 0x198 /* Recoverable Memory Data Error Log Reg A */88#define I5100_REDMEMB 0x19c /* Recoverable Memory Data Error Log Reg B */89#define I5100_RECMEMA 0x1a0 /* Recoverable Memory Error Log Reg A */90#define I5100_RECMEMB 0x1a4 /* Recoverable Memory Error Log Reg B */91#define I5100_MTR_4 0x1b0 /* Memory Technology Registers 4,5 */92 93/* bit field accessors */94 95static inline u32 i5100_mc_scrben(u32 mc)96{97 return mc >> 7 & 1;98}99 100static inline u32 i5100_mc_errdeten(u32 mc)101{102 return mc >> 5 & 1;103}104 105static inline u32 i5100_mc_scrbdone(u32 mc)106{107 return mc >> 4 & 1;108}109 110static inline u16 i5100_spddata_rdo(u16 a)111{112 return a >> 15 & 1;113}114 115static inline u16 i5100_spddata_sbe(u16 a)116{117 return a >> 13 & 1;118}119 120static inline u16 i5100_spddata_busy(u16 a)121{122 return a >> 12 & 1;123}124 125static inline u16 i5100_spddata_data(u16 a)126{127 return a & ((1 << 8) - 1);128}129 130static inline u32 i5100_spdcmd_create(u32 dti, u32 ckovrd, u32 sa, u32 ba,131 u32 data, u32 cmd)132{133 return ((dti & ((1 << 4) - 1)) << 28) |134 ((ckovrd & 1) << 27) |135 ((sa & ((1 << 3) - 1)) << 24) |136 ((ba & ((1 << 8) - 1)) << 16) |137 ((data & ((1 << 8) - 1)) << 8) |138 (cmd & 1);139}140 141static inline u16 i5100_tolm_tolm(u16 a)142{143 return a >> 12 & ((1 << 4) - 1);144}145 146static inline u16 i5100_mir_limit(u16 a)147{148 return a >> 4 & ((1 << 12) - 1);149}150 151static inline u16 i5100_mir_way1(u16 a)152{153 return a >> 1 & 1;154}155 156static inline u16 i5100_mir_way0(u16 a)157{158 return a & 1;159}160 161static inline u32 i5100_ferr_nf_mem_chan_indx(u32 a)162{163 return a >> 28 & 1;164}165 166static inline u32 i5100_ferr_nf_mem_any(u32 a)167{168 return a & I5100_FERR_NF_MEM_ANY_MASK;169}170 171static inline u32 i5100_nerr_nf_mem_any(u32 a)172{173 return i5100_ferr_nf_mem_any(a);174}175 176static inline u32 i5100_dmir_limit(u32 a)177{178 return a >> 16 & ((1 << 11) - 1);179}180 181static inline u32 i5100_dmir_rank(u32 a, u32 i)182{183 return a >> (4 * i) & ((1 << 2) - 1);184}185 186static inline u16 i5100_mtr_present(u16 a)187{188 return a >> 10 & 1;189}190 191static inline u16 i5100_mtr_ethrottle(u16 a)192{193 return a >> 9 & 1;194}195 196static inline u16 i5100_mtr_width(u16 a)197{198 return a >> 8 & 1;199}200 201static inline u16 i5100_mtr_numbank(u16 a)202{203 return a >> 6 & 1;204}205 206static inline u16 i5100_mtr_numrow(u16 a)207{208 return a >> 2 & ((1 << 2) - 1);209}210 211static inline u16 i5100_mtr_numcol(u16 a)212{213 return a & ((1 << 2) - 1);214}215 216 217static inline u32 i5100_validlog_redmemvalid(u32 a)218{219 return a >> 2 & 1;220}221 222static inline u32 i5100_validlog_recmemvalid(u32 a)223{224 return a >> 1 & 1;225}226 227static inline u32 i5100_validlog_nrecmemvalid(u32 a)228{229 return a & 1;230}231 232static inline u32 i5100_nrecmema_merr(u32 a)233{234 return a >> 15 & ((1 << 5) - 1);235}236 237static inline u32 i5100_nrecmema_bank(u32 a)238{239 return a >> 12 & ((1 << 3) - 1);240}241 242static inline u32 i5100_nrecmema_rank(u32 a)243{244 return a >> 8 & ((1 << 3) - 1);245}246 247static inline u32 i5100_nrecmemb_cas(u32 a)248{249 return a >> 16 & ((1 << 13) - 1);250}251 252static inline u32 i5100_nrecmemb_ras(u32 a)253{254 return a & ((1 << 16) - 1);255}256 257static inline u32 i5100_recmema_merr(u32 a)258{259 return i5100_nrecmema_merr(a);260}261 262static inline u32 i5100_recmema_bank(u32 a)263{264 return i5100_nrecmema_bank(a);265}266 267static inline u32 i5100_recmema_rank(u32 a)268{269 return i5100_nrecmema_rank(a);270}271 272static inline u32 i5100_recmemb_cas(u32 a)273{274 return i5100_nrecmemb_cas(a);275}276 277static inline u32 i5100_recmemb_ras(u32 a)278{279 return i5100_nrecmemb_ras(a);280}281 282/* some generic limits */283#define I5100_MAX_RANKS_PER_CHAN 6284#define I5100_CHANNELS 2285#define I5100_MAX_RANKS_PER_DIMM 4286#define I5100_DIMM_ADDR_LINES (6 - 3) /* 64 bits / 8 bits per byte */287#define I5100_MAX_DIMM_SLOTS_PER_CHAN 4288#define I5100_MAX_RANK_INTERLEAVE 4289#define I5100_MAX_DMIRS 5290#define I5100_SCRUB_REFRESH_RATE (5 * 60 * HZ)291 292struct i5100_priv {293 /* ranks on each dimm -- 0 maps to not present -- obtained via SPD */294 int dimm_numrank[I5100_CHANNELS][I5100_MAX_DIMM_SLOTS_PER_CHAN];295 296 /*297 * mainboard chip select map -- maps i5100 chip selects to298 * DIMM slot chip selects. In the case of only 4 ranks per299 * channel, the mapping is fairly obvious but not unique.300 * we map -1 -> NC and assume both channels use the same301 * map...302 *303 */304 int dimm_csmap[I5100_MAX_DIMM_SLOTS_PER_CHAN][I5100_MAX_RANKS_PER_DIMM];305 306 /* memory interleave range */307 struct {308 u64 limit;309 unsigned way[2];310 } mir[I5100_CHANNELS];311 312 /* adjusted memory interleave range register */313 unsigned amir[I5100_CHANNELS];314 315 /* dimm interleave range */316 struct {317 unsigned rank[I5100_MAX_RANK_INTERLEAVE];318 u64 limit;319 } dmir[I5100_CHANNELS][I5100_MAX_DMIRS];320 321 /* memory technology registers... */322 struct {323 unsigned present; /* 0 or 1 */324 unsigned ethrottle; /* 0 or 1 */325 unsigned width; /* 4 or 8 bits */326 unsigned numbank; /* 2 or 3 lines */327 unsigned numrow; /* 13 .. 16 lines */328 unsigned numcol; /* 11 .. 12 lines */329 } mtr[I5100_CHANNELS][I5100_MAX_RANKS_PER_CHAN];330 331 u64 tolm; /* top of low memory in bytes */332 unsigned ranksperchan; /* number of ranks per channel */333 334 struct pci_dev *mc; /* device 16 func 1 */335 struct pci_dev *einj; /* device 19 func 0 */336 struct pci_dev *ch0mm; /* device 21 func 0 */337 struct pci_dev *ch1mm; /* device 22 func 0 */338 339 struct delayed_work i5100_scrubbing;340 int scrub_enable;341 342 /* Error injection */343 u8 inject_channel;344 u8 inject_hlinesel;345 u8 inject_deviceptr1;346 u8 inject_deviceptr2;347 u16 inject_eccmask1;348 u16 inject_eccmask2;349 350 struct dentry *debugfs;351};352 353static struct dentry *i5100_debugfs;354 355/* map a rank/chan to a slot number on the mainboard */356static int i5100_rank_to_slot(const struct mem_ctl_info *mci,357 int chan, int rank)358{359 const struct i5100_priv *priv = mci->pvt_info;360 int i;361 362 for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) {363 int j;364 const int numrank = priv->dimm_numrank[chan][i];365 366 for (j = 0; j < numrank; j++)367 if (priv->dimm_csmap[i][j] == rank)368 return i * 2 + chan;369 }370 371 return -1;372}373 374static const char *i5100_err_msg(unsigned err)375{376 static const char *merrs[] = {377 "unknown", /* 0 */378 "uncorrectable data ECC on replay", /* 1 */379 "unknown", /* 2 */380 "unknown", /* 3 */381 "aliased uncorrectable demand data ECC", /* 4 */382 "aliased uncorrectable spare-copy data ECC", /* 5 */383 "aliased uncorrectable patrol data ECC", /* 6 */384 "unknown", /* 7 */385 "unknown", /* 8 */386 "unknown", /* 9 */387 "non-aliased uncorrectable demand data ECC", /* 10 */388 "non-aliased uncorrectable spare-copy data ECC", /* 11 */389 "non-aliased uncorrectable patrol data ECC", /* 12 */390 "unknown", /* 13 */391 "correctable demand data ECC", /* 14 */392 "correctable spare-copy data ECC", /* 15 */393 "correctable patrol data ECC", /* 16 */394 "unknown", /* 17 */395 "SPD protocol error", /* 18 */396 "unknown", /* 19 */397 "spare copy initiated", /* 20 */398 "spare copy completed", /* 21 */399 };400 unsigned i;401 402 for (i = 0; i < ARRAY_SIZE(merrs); i++)403 if (1 << i & err)404 return merrs[i];405 406 return "none";407}408 409/* convert csrow index into a rank (per channel -- 0..5) */410static unsigned int i5100_csrow_to_rank(const struct mem_ctl_info *mci,411 unsigned int csrow)412{413 const struct i5100_priv *priv = mci->pvt_info;414 415 return csrow % priv->ranksperchan;416}417 418/* convert csrow index into a channel (0..1) */419static unsigned int i5100_csrow_to_chan(const struct mem_ctl_info *mci,420 unsigned int csrow)421{422 const struct i5100_priv *priv = mci->pvt_info;423 424 return csrow / priv->ranksperchan;425}426 427static void i5100_handle_ce(struct mem_ctl_info *mci,428 int chan,429 unsigned bank,430 unsigned rank,431 unsigned long syndrome,432 unsigned cas,433 unsigned ras,434 const char *msg)435{436 char detail[80];437 438 /* Form out message */439 snprintf(detail, sizeof(detail),440 "bank %u, cas %u, ras %u\n",441 bank, cas, ras);442 443 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,444 0, 0, syndrome,445 chan, rank, -1,446 msg, detail);447}448 449static void i5100_handle_ue(struct mem_ctl_info *mci,450 int chan,451 unsigned bank,452 unsigned rank,453 unsigned long syndrome,454 unsigned cas,455 unsigned ras,456 const char *msg)457{458 char detail[80];459 460 /* Form out message */461 snprintf(detail, sizeof(detail),462 "bank %u, cas %u, ras %u\n",463 bank, cas, ras);464 465 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,466 0, 0, syndrome,467 chan, rank, -1,468 msg, detail);469}470 471static void i5100_read_log(struct mem_ctl_info *mci, int chan,472 u32 ferr, u32 nerr)473{474 struct i5100_priv *priv = mci->pvt_info;475 struct pci_dev *pdev = (chan) ? priv->ch1mm : priv->ch0mm;476 u32 dw;477 u32 dw2;478 unsigned syndrome = 0;479 unsigned merr;480 unsigned bank;481 unsigned rank;482 unsigned cas;483 unsigned ras;484 485 pci_read_config_dword(pdev, I5100_VALIDLOG, &dw);486 487 if (i5100_validlog_redmemvalid(dw)) {488 pci_read_config_dword(pdev, I5100_REDMEMA, &dw2);489 syndrome = dw2;490 pci_read_config_dword(pdev, I5100_REDMEMB, &dw2);491 }492 493 if (i5100_validlog_recmemvalid(dw)) {494 const char *msg;495 496 pci_read_config_dword(pdev, I5100_RECMEMA, &dw2);497 merr = i5100_recmema_merr(dw2);498 bank = i5100_recmema_bank(dw2);499 rank = i5100_recmema_rank(dw2);500 501 pci_read_config_dword(pdev, I5100_RECMEMB, &dw2);502 cas = i5100_recmemb_cas(dw2);503 ras = i5100_recmemb_ras(dw2);504 505 /* FIXME: not really sure if this is what merr is...506 */507 if (!merr)508 msg = i5100_err_msg(ferr);509 else510 msg = i5100_err_msg(nerr);511 512 i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg);513 }514 515 if (i5100_validlog_nrecmemvalid(dw)) {516 const char *msg;517 518 pci_read_config_dword(pdev, I5100_NRECMEMA, &dw2);519 merr = i5100_nrecmema_merr(dw2);520 bank = i5100_nrecmema_bank(dw2);521 rank = i5100_nrecmema_rank(dw2);522 523 pci_read_config_dword(pdev, I5100_NRECMEMB, &dw2);524 cas = i5100_nrecmemb_cas(dw2);525 ras = i5100_nrecmemb_ras(dw2);526 527 /* FIXME: not really sure if this is what merr is...528 */529 if (!merr)530 msg = i5100_err_msg(ferr);531 else532 msg = i5100_err_msg(nerr);533 534 i5100_handle_ue(mci, chan, bank, rank, syndrome, cas, ras, msg);535 }536 537 pci_write_config_dword(pdev, I5100_VALIDLOG, dw);538}539 540static void i5100_check_error(struct mem_ctl_info *mci)541{542 struct i5100_priv *priv = mci->pvt_info;543 u32 dw, dw2;544 545 pci_read_config_dword(priv->mc, I5100_FERR_NF_MEM, &dw);546 if (i5100_ferr_nf_mem_any(dw)) {547 548 pci_read_config_dword(priv->mc, I5100_NERR_NF_MEM, &dw2);549 550 i5100_read_log(mci, i5100_ferr_nf_mem_chan_indx(dw),551 i5100_ferr_nf_mem_any(dw),552 i5100_nerr_nf_mem_any(dw2));553 554 pci_write_config_dword(priv->mc, I5100_NERR_NF_MEM, dw2);555 }556 pci_write_config_dword(priv->mc, I5100_FERR_NF_MEM, dw);557}558 559/* The i5100 chipset will scrub the entire memory once, then560 * set a done bit. Continuous scrubbing is achieved by enqueing561 * delayed work to a workqueue, checking every few minutes if562 * the scrubbing has completed and if so reinitiating it.563 */564 565static void i5100_refresh_scrubbing(struct work_struct *work)566{567 struct delayed_work *i5100_scrubbing = to_delayed_work(work);568 struct i5100_priv *priv = container_of(i5100_scrubbing,569 struct i5100_priv,570 i5100_scrubbing);571 u32 dw;572 573 pci_read_config_dword(priv->mc, I5100_MC, &dw);574 575 if (priv->scrub_enable) {576 577 pci_read_config_dword(priv->mc, I5100_MC, &dw);578 579 if (i5100_mc_scrbdone(dw)) {580 dw |= I5100_MC_SCRBEN_MASK;581 pci_write_config_dword(priv->mc, I5100_MC, dw);582 pci_read_config_dword(priv->mc, I5100_MC, &dw);583 }584 585 schedule_delayed_work(&(priv->i5100_scrubbing),586 I5100_SCRUB_REFRESH_RATE);587 }588}589/*590 * The bandwidth is based on experimentation, feel free to refine it.591 */592static int i5100_set_scrub_rate(struct mem_ctl_info *mci, u32 bandwidth)593{594 struct i5100_priv *priv = mci->pvt_info;595 u32 dw;596 597 pci_read_config_dword(priv->mc, I5100_MC, &dw);598 if (bandwidth) {599 priv->scrub_enable = 1;600 dw |= I5100_MC_SCRBEN_MASK;601 schedule_delayed_work(&(priv->i5100_scrubbing),602 I5100_SCRUB_REFRESH_RATE);603 } else {604 priv->scrub_enable = 0;605 dw &= ~I5100_MC_SCRBEN_MASK;606 cancel_delayed_work(&(priv->i5100_scrubbing));607 }608 pci_write_config_dword(priv->mc, I5100_MC, dw);609 610 pci_read_config_dword(priv->mc, I5100_MC, &dw);611 612 bandwidth = 5900000 * i5100_mc_scrben(dw);613 614 return bandwidth;615}616 617static int i5100_get_scrub_rate(struct mem_ctl_info *mci)618{619 struct i5100_priv *priv = mci->pvt_info;620 u32 dw;621 622 pci_read_config_dword(priv->mc, I5100_MC, &dw);623 624 return 5900000 * i5100_mc_scrben(dw);625}626 627static struct pci_dev *pci_get_device_func(unsigned vendor,628 unsigned device,629 unsigned func)630{631 struct pci_dev *ret = NULL;632 633 while (1) {634 ret = pci_get_device(vendor, device, ret);635 636 if (!ret)637 break;638 639 if (PCI_FUNC(ret->devfn) == func)640 break;641 }642 643 return ret;644}645 646static unsigned long i5100_npages(struct mem_ctl_info *mci, unsigned int csrow)647{648 struct i5100_priv *priv = mci->pvt_info;649 const unsigned int chan_rank = i5100_csrow_to_rank(mci, csrow);650 const unsigned int chan = i5100_csrow_to_chan(mci, csrow);651 unsigned addr_lines;652 653 /* dimm present? */654 if (!priv->mtr[chan][chan_rank].present)655 return 0ULL;656 657 addr_lines =658 I5100_DIMM_ADDR_LINES +659 priv->mtr[chan][chan_rank].numcol +660 priv->mtr[chan][chan_rank].numrow +661 priv->mtr[chan][chan_rank].numbank;662 663 return (unsigned long)664 ((unsigned long long) (1ULL << addr_lines) / PAGE_SIZE);665}666 667static void i5100_init_mtr(struct mem_ctl_info *mci)668{669 struct i5100_priv *priv = mci->pvt_info;670 struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm };671 int i;672 673 for (i = 0; i < I5100_CHANNELS; i++) {674 int j;675 struct pci_dev *pdev = mms[i];676 677 for (j = 0; j < I5100_MAX_RANKS_PER_CHAN; j++) {678 const unsigned addr =679 (j < 4) ? I5100_MTR_0 + j * 2 :680 I5100_MTR_4 + (j - 4) * 2;681 u16 w;682 683 pci_read_config_word(pdev, addr, &w);684 685 priv->mtr[i][j].present = i5100_mtr_present(w);686 priv->mtr[i][j].ethrottle = i5100_mtr_ethrottle(w);687 priv->mtr[i][j].width = 4 + 4 * i5100_mtr_width(w);688 priv->mtr[i][j].numbank = 2 + i5100_mtr_numbank(w);689 priv->mtr[i][j].numrow = 13 + i5100_mtr_numrow(w);690 priv->mtr[i][j].numcol = 10 + i5100_mtr_numcol(w);691 }692 }693}694 695/*696 * FIXME: make this into a real i2c adapter (so that dimm-decode697 * will work)?698 */699static int i5100_read_spd_byte(const struct mem_ctl_info *mci,700 u8 ch, u8 slot, u8 addr, u8 *byte)701{702 struct i5100_priv *priv = mci->pvt_info;703 u16 w;704 705 pci_read_config_word(priv->mc, I5100_SPDDATA, &w);706 if (i5100_spddata_busy(w))707 return -1;708 709 pci_write_config_dword(priv->mc, I5100_SPDCMD,710 i5100_spdcmd_create(0xa, 1, ch * 4 + slot, addr,711 0, 0));712 713 /* wait up to 100ms */714 udelay(100);715 while (1) {716 pci_read_config_word(priv->mc, I5100_SPDDATA, &w);717 if (!i5100_spddata_busy(w))718 break;719 udelay(100);720 }721 722 if (!i5100_spddata_rdo(w) || i5100_spddata_sbe(w))723 return -1;724 725 *byte = i5100_spddata_data(w);726 727 return 0;728}729 730/*731 * fill dimm chip select map732 *733 * FIXME:734 * o not the only way to may chip selects to dimm slots735 * o investigate if there is some way to obtain this map from the bios736 */737static void i5100_init_dimm_csmap(struct mem_ctl_info *mci)738{739 struct i5100_priv *priv = mci->pvt_info;740 int i;741 742 for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) {743 int j;744 745 for (j = 0; j < I5100_MAX_RANKS_PER_DIMM; j++)746 priv->dimm_csmap[i][j] = -1; /* default NC */747 }748 749 /* only 2 chip selects per slot... */750 if (priv->ranksperchan == 4) {751 priv->dimm_csmap[0][0] = 0;752 priv->dimm_csmap[0][1] = 3;753 priv->dimm_csmap[1][0] = 1;754 priv->dimm_csmap[1][1] = 2;755 priv->dimm_csmap[2][0] = 2;756 priv->dimm_csmap[3][0] = 3;757 } else {758 priv->dimm_csmap[0][0] = 0;759 priv->dimm_csmap[0][1] = 1;760 priv->dimm_csmap[1][0] = 2;761 priv->dimm_csmap[1][1] = 3;762 priv->dimm_csmap[2][0] = 4;763 priv->dimm_csmap[2][1] = 5;764 }765}766 767static void i5100_init_dimm_layout(struct pci_dev *pdev,768 struct mem_ctl_info *mci)769{770 struct i5100_priv *priv = mci->pvt_info;771 int i;772 773 for (i = 0; i < I5100_CHANNELS; i++) {774 int j;775 776 for (j = 0; j < I5100_MAX_DIMM_SLOTS_PER_CHAN; j++) {777 u8 rank;778 779 if (i5100_read_spd_byte(mci, i, j, 5, &rank) < 0)780 priv->dimm_numrank[i][j] = 0;781 else782 priv->dimm_numrank[i][j] = (rank & 3) + 1;783 }784 }785 786 i5100_init_dimm_csmap(mci);787}788 789static void i5100_init_interleaving(struct pci_dev *pdev,790 struct mem_ctl_info *mci)791{792 u16 w;793 u32 dw;794 struct i5100_priv *priv = mci->pvt_info;795 struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm };796 int i;797 798 pci_read_config_word(pdev, I5100_TOLM, &w);799 priv->tolm = (u64) i5100_tolm_tolm(w) * 256 * 1024 * 1024;800 801 pci_read_config_word(pdev, I5100_MIR0, &w);802 priv->mir[0].limit = (u64) i5100_mir_limit(w) << 28;803 priv->mir[0].way[1] = i5100_mir_way1(w);804 priv->mir[0].way[0] = i5100_mir_way0(w);805 806 pci_read_config_word(pdev, I5100_MIR1, &w);807 priv->mir[1].limit = (u64) i5100_mir_limit(w) << 28;808 priv->mir[1].way[1] = i5100_mir_way1(w);809 priv->mir[1].way[0] = i5100_mir_way0(w);810 811 pci_read_config_word(pdev, I5100_AMIR_0, &w);812 priv->amir[0] = w;813 pci_read_config_word(pdev, I5100_AMIR_1, &w);814 priv->amir[1] = w;815 816 for (i = 0; i < I5100_CHANNELS; i++) {817 int j;818 819 for (j = 0; j < 5; j++) {820 int k;821 822 pci_read_config_dword(mms[i], I5100_DMIR + j * 4, &dw);823 824 priv->dmir[i][j].limit =825 (u64) i5100_dmir_limit(dw) << 28;826 for (k = 0; k < I5100_MAX_RANKS_PER_DIMM; k++)827 priv->dmir[i][j].rank[k] =828 i5100_dmir_rank(dw, k);829 }830 }831 832 i5100_init_mtr(mci);833}834 835static void i5100_init_csrows(struct mem_ctl_info *mci)836{837 struct i5100_priv *priv = mci->pvt_info;838 struct dimm_info *dimm;839 840 mci_for_each_dimm(mci, dimm) {841 const unsigned long npages = i5100_npages(mci, dimm->idx);842 const unsigned int chan = i5100_csrow_to_chan(mci, dimm->idx);843 const unsigned int rank = i5100_csrow_to_rank(mci, dimm->idx);844 845 if (!npages)846 continue;847 848 dimm->nr_pages = npages;849 dimm->grain = 32;850 dimm->dtype = (priv->mtr[chan][rank].width == 4) ?851 DEV_X4 : DEV_X8;852 dimm->mtype = MEM_RDDR2;853 dimm->edac_mode = EDAC_SECDED;854 snprintf(dimm->label, sizeof(dimm->label), "DIMM%u",855 i5100_rank_to_slot(mci, chan, rank));856 857 edac_dbg(2, "dimm channel %d, rank %d, size %ld\n",858 chan, rank, (long)PAGES_TO_MiB(npages));859 }860}861 862/****************************************************************************863 * Error injection routines864 ****************************************************************************/865 866static void i5100_do_inject(struct mem_ctl_info *mci)867{868 struct i5100_priv *priv = mci->pvt_info;869 u32 mask0;870 u16 mask1;871 872 /* MEM[1:0]EINJMSK0873 * 31 - ADDRMATCHEN874 * 29:28 - HLINESEL875 * 00 Reserved876 * 01 Lower half of cache line877 * 10 Upper half of cache line878 * 11 Both upper and lower parts of cache line879 * 27 - EINJEN880 * 25:19 - XORMASK1 for deviceptr1881 * 9:5 - SEC2RAM for deviceptr2882 * 4:0 - FIR2RAM for deviceptr1883 */884 mask0 = ((priv->inject_hlinesel & 0x3) << 28) |885 I5100_MEMXEINJMSK0_EINJEN |886 ((priv->inject_eccmask1 & 0xffff) << 10) |887 ((priv->inject_deviceptr2 & 0x1f) << 5) |888 (priv->inject_deviceptr1 & 0x1f);889 890 /* MEM[1:0]EINJMSK1891 * 15:0 - XORMASK2 for deviceptr2892 */893 mask1 = priv->inject_eccmask2;894 895 if (priv->inject_channel == 0) {896 pci_write_config_dword(priv->mc, I5100_MEM0EINJMSK0, mask0);897 pci_write_config_word(priv->mc, I5100_MEM0EINJMSK1, mask1);898 } else {899 pci_write_config_dword(priv->mc, I5100_MEM1EINJMSK0, mask0);900 pci_write_config_word(priv->mc, I5100_MEM1EINJMSK1, mask1);901 }902 903 /* Error Injection Response Function904 * Intel 5100 Memory Controller Hub Chipset (318378) datasheet905 * hints about this register but carry no data about them. All906 * data regarding device 19 is based on experimentation and the907 * Intel 7300 Chipset Memory Controller Hub (318082) datasheet908 * which appears to be accurate for the i5100 in this area.909 *910 * The injection code don't work without setting this register.911 * The register needs to be flipped off then on else the hardware912 * will only perform the first injection.913 *914 * Stop condition bits 7:4915 * 1010 - Stop after one injection916 * 1011 - Never stop injecting faults917 *918 * Start condition bits 3:0919 * 1010 - Never start920 * 1011 - Start immediately921 */922 pci_write_config_byte(priv->einj, I5100_DINJ0, 0xaa);923 pci_write_config_byte(priv->einj, I5100_DINJ0, 0xab);924}925 926#define to_mci(k) container_of(k, struct mem_ctl_info, dev)927static ssize_t inject_enable_write(struct file *file, const char __user *data,928 size_t count, loff_t *ppos)929{930 struct device *dev = file->private_data;931 struct mem_ctl_info *mci = to_mci(dev);932 933 i5100_do_inject(mci);934 935 return count;936}937 938static const struct file_operations i5100_inject_enable_fops = {939 .open = simple_open,940 .write = inject_enable_write,941 .llseek = generic_file_llseek,942};943 944static int i5100_setup_debugfs(struct mem_ctl_info *mci)945{946 struct i5100_priv *priv = mci->pvt_info;947 948 if (!i5100_debugfs)949 return -ENODEV;950 951 priv->debugfs = edac_debugfs_create_dir_at(mci->bus->name, i5100_debugfs);952 953 if (!priv->debugfs)954 return -ENOMEM;955 956 edac_debugfs_create_x8("inject_channel", S_IRUGO | S_IWUSR, priv->debugfs,957 &priv->inject_channel);958 edac_debugfs_create_x8("inject_hlinesel", S_IRUGO | S_IWUSR, priv->debugfs,959 &priv->inject_hlinesel);960 edac_debugfs_create_x8("inject_deviceptr1", S_IRUGO | S_IWUSR, priv->debugfs,961 &priv->inject_deviceptr1);962 edac_debugfs_create_x8("inject_deviceptr2", S_IRUGO | S_IWUSR, priv->debugfs,963 &priv->inject_deviceptr2);964 edac_debugfs_create_x16("inject_eccmask1", S_IRUGO | S_IWUSR, priv->debugfs,965 &priv->inject_eccmask1);966 edac_debugfs_create_x16("inject_eccmask2", S_IRUGO | S_IWUSR, priv->debugfs,967 &priv->inject_eccmask2);968 edac_debugfs_create_file("inject_enable", S_IWUSR, priv->debugfs,969 &mci->dev, &i5100_inject_enable_fops);970 971 return 0;972 973}974 975static int i5100_init_one(struct pci_dev *pdev, const struct pci_device_id *id)976{977 int rc;978 struct mem_ctl_info *mci;979 struct edac_mc_layer layers[2];980 struct i5100_priv *priv;981 struct pci_dev *ch0mm, *ch1mm, *einj;982 int ret = 0;983 u32 dw;984 int ranksperch;985 986 if (PCI_FUNC(pdev->devfn) != 1)987 return -ENODEV;988 989 rc = pci_enable_device(pdev);990 if (rc < 0) {991 ret = rc;992 goto bail;993 }994 995 /* ECC enabled? */996 pci_read_config_dword(pdev, I5100_MC, &dw);997 if (!i5100_mc_errdeten(dw)) {998 printk(KERN_INFO "i5100_edac: ECC not enabled.\n");999 ret = -ENODEV;1000 goto bail_pdev;1001 }1002 1003 /* figure out how many ranks, from strapped state of 48GB_Mode input */1004 pci_read_config_dword(pdev, I5100_MS, &dw);1005 ranksperch = !!(dw & (1 << 8)) * 2 + 4;1006 1007 /* enable error reporting... */1008 pci_read_config_dword(pdev, I5100_EMASK_MEM, &dw);1009 dw &= ~I5100_FERR_NF_MEM_ANY_MASK;1010 pci_write_config_dword(pdev, I5100_EMASK_MEM, dw);1011 1012 /* device 21, func 0, Channel 0 Memory Map, Error Flag/Mask, etc... */1013 ch0mm = pci_get_device_func(PCI_VENDOR_ID_INTEL,1014 PCI_DEVICE_ID_INTEL_5100_21, 0);1015 if (!ch0mm) {1016 ret = -ENODEV;1017 goto bail_pdev;1018 }1019 1020 rc = pci_enable_device(ch0mm);1021 if (rc < 0) {1022 ret = rc;1023 goto bail_ch0;1024 }1025 1026 /* device 22, func 0, Channel 1 Memory Map, Error Flag/Mask, etc... */1027 ch1mm = pci_get_device_func(PCI_VENDOR_ID_INTEL,1028 PCI_DEVICE_ID_INTEL_5100_22, 0);1029 if (!ch1mm) {1030 ret = -ENODEV;1031 goto bail_disable_ch0;1032 }1033 1034 rc = pci_enable_device(ch1mm);1035 if (rc < 0) {1036 ret = rc;1037 goto bail_ch1;1038 }1039 1040 layers[0].type = EDAC_MC_LAYER_CHANNEL;1041 layers[0].size = 2;1042 layers[0].is_virt_csrow = false;1043 layers[1].type = EDAC_MC_LAYER_SLOT;1044 layers[1].size = ranksperch;1045 layers[1].is_virt_csrow = true;1046 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,1047 sizeof(*priv));1048 if (!mci) {1049 ret = -ENOMEM;1050 goto bail_disable_ch1;1051 }1052 1053 1054 /* device 19, func 0, Error injection */1055 einj = pci_get_device_func(PCI_VENDOR_ID_INTEL,1056 PCI_DEVICE_ID_INTEL_5100_19, 0);1057 if (!einj) {1058 ret = -ENODEV;1059 goto bail_mc_free;1060 }1061 1062 rc = pci_enable_device(einj);1063 if (rc < 0) {1064 ret = rc;1065 goto bail_einj;1066 }1067 1068 mci->pdev = &pdev->dev;1069 1070 priv = mci->pvt_info;1071 priv->ranksperchan = ranksperch;1072 priv->mc = pdev;1073 priv->ch0mm = ch0mm;1074 priv->ch1mm = ch1mm;1075 priv->einj = einj;1076 1077 INIT_DELAYED_WORK(&(priv->i5100_scrubbing), i5100_refresh_scrubbing);1078 1079 /* If scrubbing was already enabled by the bios, start maintaining it */1080 pci_read_config_dword(pdev, I5100_MC, &dw);1081 if (i5100_mc_scrben(dw)) {1082 priv->scrub_enable = 1;1083 schedule_delayed_work(&(priv->i5100_scrubbing),1084 I5100_SCRUB_REFRESH_RATE);1085 }1086 1087 i5100_init_dimm_layout(pdev, mci);1088 i5100_init_interleaving(pdev, mci);1089 1090 mci->mtype_cap = MEM_FLAG_FB_DDR2;1091 mci->edac_ctl_cap = EDAC_FLAG_SECDED;1092 mci->edac_cap = EDAC_FLAG_SECDED;1093 mci->mod_name = "i5100_edac.c";1094 mci->ctl_name = "i5100";1095 mci->dev_name = pci_name(pdev);1096 mci->ctl_page_to_phys = NULL;1097 1098 mci->edac_check = i5100_check_error;1099 mci->set_sdram_scrub_rate = i5100_set_scrub_rate;1100 mci->get_sdram_scrub_rate = i5100_get_scrub_rate;1101 1102 priv->inject_channel = 0;1103 priv->inject_hlinesel = 0;1104 priv->inject_deviceptr1 = 0;1105 priv->inject_deviceptr2 = 0;1106 priv->inject_eccmask1 = 0;1107 priv->inject_eccmask2 = 0;1108 1109 i5100_init_csrows(mci);1110 1111 /* this strange construction seems to be in every driver, dunno why */1112 switch (edac_op_state) {1113 case EDAC_OPSTATE_POLL:1114 case EDAC_OPSTATE_NMI:1115 break;1116 default:1117 edac_op_state = EDAC_OPSTATE_POLL;1118 break;1119 }1120 1121 if (edac_mc_add_mc(mci)) {1122 ret = -ENODEV;1123 goto bail_scrub;1124 }1125 1126 i5100_setup_debugfs(mci);1127 1128 return ret;1129 1130bail_scrub:1131 priv->scrub_enable = 0;1132 cancel_delayed_work_sync(&(priv->i5100_scrubbing));1133 pci_disable_device(einj);1134 1135bail_einj:1136 pci_dev_put(einj);1137 1138bail_mc_free:1139 edac_mc_free(mci);1140 1141bail_disable_ch1:1142 pci_disable_device(ch1mm);1143 1144bail_ch1:1145 pci_dev_put(ch1mm);1146 1147bail_disable_ch0:1148 pci_disable_device(ch0mm);1149 1150bail_ch0:1151 pci_dev_put(ch0mm);1152 1153bail_pdev:1154 pci_disable_device(pdev);1155 1156bail:1157 return ret;1158}1159 1160static void i5100_remove_one(struct pci_dev *pdev)1161{1162 struct mem_ctl_info *mci;1163 struct i5100_priv *priv;1164 1165 mci = edac_mc_del_mc(&pdev->dev);1166 1167 if (!mci)1168 return;1169 1170 priv = mci->pvt_info;1171 1172 edac_debugfs_remove_recursive(priv->debugfs);1173 1174 priv->scrub_enable = 0;1175 cancel_delayed_work_sync(&(priv->i5100_scrubbing));1176 1177 pci_disable_device(pdev);1178 pci_disable_device(priv->ch0mm);1179 pci_disable_device(priv->ch1mm);1180 pci_disable_device(priv->einj);1181 pci_dev_put(priv->ch0mm);1182 pci_dev_put(priv->ch1mm);1183 pci_dev_put(priv->einj);1184 1185 edac_mc_free(mci);1186}1187 1188static const struct pci_device_id i5100_pci_tbl[] = {1189 /* Device 16, Function 0, Channel 0 Memory Map, Error Flag/Mask, ... */1190 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5100_16) },1191 { 0, }1192};1193MODULE_DEVICE_TABLE(pci, i5100_pci_tbl);1194 1195static struct pci_driver i5100_driver = {1196 .name = KBUILD_BASENAME,1197 .probe = i5100_init_one,1198 .remove = i5100_remove_one,1199 .id_table = i5100_pci_tbl,1200};1201 1202static int __init i5100_init(void)1203{1204 int pci_rc;1205 1206 i5100_debugfs = edac_debugfs_create_dir_at("i5100_edac", NULL);1207 1208 pci_rc = pci_register_driver(&i5100_driver);1209 return (pci_rc < 0) ? pci_rc : 0;1210}1211 1212static void __exit i5100_exit(void)1213{1214 edac_debugfs_remove(i5100_debugfs);1215 1216 pci_unregister_driver(&i5100_driver);1217}1218 1219module_init(i5100_init);1220module_exit(i5100_exit);1221 1222MODULE_LICENSE("GPL");1223MODULE_AUTHOR("Arthur Jones <ajones@riverbed.com>");1224MODULE_DESCRIPTION("MC Driver for Intel I5100 memory controllers");1225