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1/*2 * Intel 5400 class Memory Controllers kernel module (Seaburg)3 *4 * This file may be distributed under the terms of the5 * GNU General Public License.6 *7 * Copyright (c) 2008 by:8 * Ben Woodard <woodard@redhat.com>9 * Mauro Carvalho Chehab10 *11 * Red Hat Inc. https://www.redhat.com12 *13 * Forked and adapted from the i5000_edac driver which was14 * written by Douglas Thompson Linux Networx <norsk5@xmission.com>15 *16 * This module is based on the following document:17 *18 * Intel 5400 Chipset Memory Controller Hub (MCH) - Datasheet19 * http://developer.intel.com/design/chipsets/datashts/313070.htm20 *21 * This Memory Controller manages DDR2 FB-DIMMs. It has 2 branches, each with22 * 2 channels operating in lockstep no-mirror mode. Each channel can have up to23 * 4 dimm's, each with up to 8GB.24 *25 */26 27#include <linux/module.h>28#include <linux/init.h>29#include <linux/pci.h>30#include <linux/pci_ids.h>31#include <linux/slab.h>32#include <linux/edac.h>33#include <linux/mmzone.h>34 35#include "edac_module.h"36 37/*38 * Alter this version for the I5400 module when modifications are made39 */40#define I5400_REVISION " Ver: 1.0.0"41 42#define EDAC_MOD_STR "i5400_edac"43 44#define i5400_printk(level, fmt, arg...) \45 edac_printk(level, "i5400", fmt, ##arg)46 47#define i5400_mc_printk(mci, level, fmt, arg...) \48 edac_mc_chipset_printk(mci, level, "i5400", fmt, ##arg)49 50/* Limits for i5400 */51#define MAX_BRANCHES 252#define CHANNELS_PER_BRANCH 253#define DIMMS_PER_CHANNEL 454#define MAX_CHANNELS (MAX_BRANCHES * CHANNELS_PER_BRANCH)55 56/* Device 16,57 * Function 0: System Address58 * Function 1: Memory Branch Map, Control, Errors Register59 * Function 2: FSB Error Registers60 *61 * All 3 functions of Device 16 (0,1,2) share the SAME DID and62 * uses PCI_DEVICE_ID_INTEL_5400_ERR for device 16 (0,1,2),63 * PCI_DEVICE_ID_INTEL_5400_FBD0 and PCI_DEVICE_ID_INTEL_5400_FBD164 * for device 21 (0,1).65 */66 67 /* OFFSETS for Function 0 */68#define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */69#define MAXCH 0x56 /* Max Channel Number */70#define MAXDIMMPERCH 0x57 /* Max DIMM PER Channel Number */71 72 /* OFFSETS for Function 1 */73#define TOLM 0x6C74#define REDMEMB 0x7C75#define REC_ECC_LOCATOR_ODD(x) ((x) & 0x3fe00) /* bits [17:9] indicate ODD, [8:0] indicate EVEN */76#define MIR0 0x8077#define MIR1 0x8478#define AMIR0 0x8c79#define AMIR1 0x9080 81 /* Fatal error registers */82#define FERR_FAT_FBD 0x98 /* also called as FERR_FAT_FB_DIMM at datasheet */83#define FERR_FAT_FBDCHAN (3<<28) /* channel index where the highest-order error occurred */84 85#define NERR_FAT_FBD 0x9c86#define FERR_NF_FBD 0xa0 /* also called as FERR_NFAT_FB_DIMM at datasheet */87 88 /* Non-fatal error register */89#define NERR_NF_FBD 0xa490 91 /* Enable error mask */92#define EMASK_FBD 0xa893 94#define ERR0_FBD 0xac95#define ERR1_FBD 0xb096#define ERR2_FBD 0xb497#define MCERR_FBD 0xb898 99 /* No OFFSETS for Device 16 Function 2 */100 101/*102 * Device 21,103 * Function 0: Memory Map Branch 0104 *105 * Device 22,106 * Function 0: Memory Map Branch 1107 */108 109 /* OFFSETS for Function 0 */110#define AMBPRESENT_0 0x64111#define AMBPRESENT_1 0x66112#define MTR0 0x80113#define MTR1 0x82114#define MTR2 0x84115#define MTR3 0x86116 117 /* OFFSETS for Function 1 */118#define NRECFGLOG 0x74119#define RECFGLOG 0x78120#define NRECMEMA 0xbe121#define NRECMEMB 0xc0122#define NRECFB_DIMMA 0xc4123#define NRECFB_DIMMB 0xc8124#define NRECFB_DIMMC 0xcc125#define NRECFB_DIMMD 0xd0126#define NRECFB_DIMME 0xd4127#define NRECFB_DIMMF 0xd8128#define REDMEMA 0xdC129#define RECMEMA 0xf0130#define RECMEMB 0xf4131#define RECFB_DIMMA 0xf8132#define RECFB_DIMMB 0xec133#define RECFB_DIMMC 0xf0134#define RECFB_DIMMD 0xf4135#define RECFB_DIMME 0xf8136#define RECFB_DIMMF 0xfC137 138/*139 * Error indicator bits and masks140 * Error masks are according with Table 5-17 of i5400 datasheet141 */142 143enum error_mask {144 EMASK_M1 = 1<<0, /* Memory Write error on non-redundant retry */145 EMASK_M2 = 1<<1, /* Memory or FB-DIMM configuration CRC read error */146 EMASK_M3 = 1<<2, /* Reserved */147 EMASK_M4 = 1<<3, /* Uncorrectable Data ECC on Replay */148 EMASK_M5 = 1<<4, /* Aliased Uncorrectable Non-Mirrored Demand Data ECC */149 EMASK_M6 = 1<<5, /* Unsupported on i5400 */150 EMASK_M7 = 1<<6, /* Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */151 EMASK_M8 = 1<<7, /* Aliased Uncorrectable Patrol Data ECC */152 EMASK_M9 = 1<<8, /* Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC */153 EMASK_M10 = 1<<9, /* Unsupported on i5400 */154 EMASK_M11 = 1<<10, /* Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */155 EMASK_M12 = 1<<11, /* Non-Aliased Uncorrectable Patrol Data ECC */156 EMASK_M13 = 1<<12, /* Memory Write error on first attempt */157 EMASK_M14 = 1<<13, /* FB-DIMM Configuration Write error on first attempt */158 EMASK_M15 = 1<<14, /* Memory or FB-DIMM configuration CRC read error */159 EMASK_M16 = 1<<15, /* Channel Failed-Over Occurred */160 EMASK_M17 = 1<<16, /* Correctable Non-Mirrored Demand Data ECC */161 EMASK_M18 = 1<<17, /* Unsupported on i5400 */162 EMASK_M19 = 1<<18, /* Correctable Resilver- or Spare-Copy Data ECC */163 EMASK_M20 = 1<<19, /* Correctable Patrol Data ECC */164 EMASK_M21 = 1<<20, /* FB-DIMM Northbound parity error on FB-DIMM Sync Status */165 EMASK_M22 = 1<<21, /* SPD protocol Error */166 EMASK_M23 = 1<<22, /* Non-Redundant Fast Reset Timeout */167 EMASK_M24 = 1<<23, /* Refresh error */168 EMASK_M25 = 1<<24, /* Memory Write error on redundant retry */169 EMASK_M26 = 1<<25, /* Redundant Fast Reset Timeout */170 EMASK_M27 = 1<<26, /* Correctable Counter Threshold Exceeded */171 EMASK_M28 = 1<<27, /* DIMM-Spare Copy Completed */172 EMASK_M29 = 1<<28, /* DIMM-Isolation Completed */173};174 175/*176 * Names to translate bit error into something useful177 */178static const char *error_name[] = {179 [0] = "Memory Write error on non-redundant retry",180 [1] = "Memory or FB-DIMM configuration CRC read error",181 /* Reserved */182 [3] = "Uncorrectable Data ECC on Replay",183 [4] = "Aliased Uncorrectable Non-Mirrored Demand Data ECC",184 /* M6 Unsupported on i5400 */185 [6] = "Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",186 [7] = "Aliased Uncorrectable Patrol Data ECC",187 [8] = "Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC",188 /* M10 Unsupported on i5400 */189 [10] = "Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",190 [11] = "Non-Aliased Uncorrectable Patrol Data ECC",191 [12] = "Memory Write error on first attempt",192 [13] = "FB-DIMM Configuration Write error on first attempt",193 [14] = "Memory or FB-DIMM configuration CRC read error",194 [15] = "Channel Failed-Over Occurred",195 [16] = "Correctable Non-Mirrored Demand Data ECC",196 /* M18 Unsupported on i5400 */197 [18] = "Correctable Resilver- or Spare-Copy Data ECC",198 [19] = "Correctable Patrol Data ECC",199 [20] = "FB-DIMM Northbound parity error on FB-DIMM Sync Status",200 [21] = "SPD protocol Error",201 [22] = "Non-Redundant Fast Reset Timeout",202 [23] = "Refresh error",203 [24] = "Memory Write error on redundant retry",204 [25] = "Redundant Fast Reset Timeout",205 [26] = "Correctable Counter Threshold Exceeded",206 [27] = "DIMM-Spare Copy Completed",207 [28] = "DIMM-Isolation Completed",208};209 210/* Fatal errors */211#define ERROR_FAT_MASK (EMASK_M1 | \212 EMASK_M2 | \213 EMASK_M23)214 215/* Correctable errors */216#define ERROR_NF_CORRECTABLE (EMASK_M27 | \217 EMASK_M20 | \218 EMASK_M19 | \219 EMASK_M18 | \220 EMASK_M17 | \221 EMASK_M16)222#define ERROR_NF_DIMM_SPARE (EMASK_M29 | \223 EMASK_M28)224#define ERROR_NF_SPD_PROTOCOL (EMASK_M22)225#define ERROR_NF_NORTH_CRC (EMASK_M21)226 227/* Recoverable errors */228#define ERROR_NF_RECOVERABLE (EMASK_M26 | \229 EMASK_M25 | \230 EMASK_M24 | \231 EMASK_M15 | \232 EMASK_M14 | \233 EMASK_M13 | \234 EMASK_M12 | \235 EMASK_M11 | \236 EMASK_M9 | \237 EMASK_M8 | \238 EMASK_M7 | \239 EMASK_M5)240 241/* uncorrectable errors */242#define ERROR_NF_UNCORRECTABLE (EMASK_M4)243 244/* mask to all non-fatal errors */245#define ERROR_NF_MASK (ERROR_NF_CORRECTABLE | \246 ERROR_NF_UNCORRECTABLE | \247 ERROR_NF_RECOVERABLE | \248 ERROR_NF_DIMM_SPARE | \249 ERROR_NF_SPD_PROTOCOL | \250 ERROR_NF_NORTH_CRC)251 252/*253 * Define error masks for the several registers254 */255 256/* Enable all fatal and non fatal errors */257#define ENABLE_EMASK_ALL (ERROR_FAT_MASK | ERROR_NF_MASK)258 259/* mask for fatal error registers */260#define FERR_FAT_MASK ERROR_FAT_MASK261 262/* masks for non-fatal error register */263static inline int to_nf_mask(unsigned int mask)264{265 return (mask & EMASK_M29) | (mask >> 3);266};267 268static inline int from_nf_ferr(unsigned int mask)269{270 return (mask & EMASK_M29) | /* Bit 28 */271 (mask & ((1 << 28) - 1) << 3); /* Bits 0 to 27 */272};273 274#define FERR_NF_MASK to_nf_mask(ERROR_NF_MASK)275#define FERR_NF_CORRECTABLE to_nf_mask(ERROR_NF_CORRECTABLE)276#define FERR_NF_DIMM_SPARE to_nf_mask(ERROR_NF_DIMM_SPARE)277#define FERR_NF_SPD_PROTOCOL to_nf_mask(ERROR_NF_SPD_PROTOCOL)278#define FERR_NF_NORTH_CRC to_nf_mask(ERROR_NF_NORTH_CRC)279#define FERR_NF_RECOVERABLE to_nf_mask(ERROR_NF_RECOVERABLE)280#define FERR_NF_UNCORRECTABLE to_nf_mask(ERROR_NF_UNCORRECTABLE)281 282/*283 * Defines to extract the various fields from the284 * MTRx - Memory Technology Registers285 */286#define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 10))287#define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 9))288#define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 8)) ? 8 : 4)289#define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 6)) ? 8 : 4)290#define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2)291#define MTR_DIMM_RANK(mtr) (((mtr) >> 5) & 0x1)292#define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1)293#define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3)294#define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13)295#define MTR_DIMM_COLS(mtr) ((mtr) & 0x3)296#define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10)297 298/* This applies to FERR_NF_FB-DIMM as well as FERR_FAT_FB-DIMM */299static inline int extract_fbdchan_indx(u32 x)300{301 return (x>>28) & 0x3;302}303 304/* Device name and register DID (Device ID) */305struct i5400_dev_info {306 const char *ctl_name; /* name for this device */307 u16 fsb_mapping_errors; /* DID for the branchmap,control */308};309 310/* Table of devices attributes supported by this driver */311static const struct i5400_dev_info i5400_devs[] = {312 {313 .ctl_name = "I5400",314 .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_5400_ERR,315 },316};317 318struct i5400_dimm_info {319 int megabytes; /* size, 0 means not present */320};321 322/* driver private data structure */323struct i5400_pvt {324 struct pci_dev *system_address; /* 16.0 */325 struct pci_dev *branchmap_werrors; /* 16.1 */326 struct pci_dev *fsb_error_regs; /* 16.2 */327 struct pci_dev *branch_0; /* 21.0 */328 struct pci_dev *branch_1; /* 22.0 */329 330 u16 tolm; /* top of low memory */331 union {332 u64 ambase; /* AMB BAR */333 struct {334 u32 ambase_bottom;335 u32 ambase_top;336 } u __packed;337 };338 339 u16 mir0, mir1;340 341 u16 b0_mtr[DIMMS_PER_CHANNEL]; /* Memory Technlogy Reg */342 u16 b0_ambpresent0; /* Branch 0, Channel 0 */343 u16 b0_ambpresent1; /* Brnach 0, Channel 1 */344 345 u16 b1_mtr[DIMMS_PER_CHANNEL]; /* Memory Technlogy Reg */346 u16 b1_ambpresent0; /* Branch 1, Channel 8 */347 u16 b1_ambpresent1; /* Branch 1, Channel 1 */348 349 /* DIMM information matrix, allocating architecture maximums */350 struct i5400_dimm_info dimm_info[DIMMS_PER_CHANNEL][MAX_CHANNELS];351 352 /* Actual values for this controller */353 int maxch; /* Max channels */354 int maxdimmperch; /* Max DIMMs per channel */355};356 357/* I5400 MCH error information retrieved from Hardware */358struct i5400_error_info {359 /* These registers are always read from the MC */360 u32 ferr_fat_fbd; /* First Errors Fatal */361 u32 nerr_fat_fbd; /* Next Errors Fatal */362 u32 ferr_nf_fbd; /* First Errors Non-Fatal */363 u32 nerr_nf_fbd; /* Next Errors Non-Fatal */364 365 /* These registers are input ONLY if there was a Recoverable Error */366 u32 redmemb; /* Recoverable Mem Data Error log B */367 u16 recmema; /* Recoverable Mem Error log A */368 u32 recmemb; /* Recoverable Mem Error log B */369 370 /* These registers are input ONLY if there was a Non-Rec Error */371 u16 nrecmema; /* Non-Recoverable Mem log A */372 u32 nrecmemb; /* Non-Recoverable Mem log B */373 374};375 376/* note that nrec_rdwr changed from NRECMEMA to NRECMEMB between the 5000 and377 5400 better to use an inline function than a macro in this case */378static inline int nrec_bank(struct i5400_error_info *info)379{380 return ((info->nrecmema) >> 12) & 0x7;381}382static inline int nrec_rank(struct i5400_error_info *info)383{384 return ((info->nrecmema) >> 8) & 0xf;385}386static inline int nrec_buf_id(struct i5400_error_info *info)387{388 return ((info->nrecmema)) & 0xff;389}390static inline int nrec_rdwr(struct i5400_error_info *info)391{392 return (info->nrecmemb) >> 31;393}394/* This applies to both NREC and REC string so it can be used with nrec_rdwr395 and rec_rdwr */396static inline const char *rdwr_str(int rdwr)397{398 return rdwr ? "Write" : "Read";399}400static inline int nrec_cas(struct i5400_error_info *info)401{402 return ((info->nrecmemb) >> 16) & 0x1fff;403}404static inline int nrec_ras(struct i5400_error_info *info)405{406 return (info->nrecmemb) & 0xffff;407}408static inline int rec_bank(struct i5400_error_info *info)409{410 return ((info->recmema) >> 12) & 0x7;411}412static inline int rec_rank(struct i5400_error_info *info)413{414 return ((info->recmema) >> 8) & 0xf;415}416static inline int rec_rdwr(struct i5400_error_info *info)417{418 return (info->recmemb) >> 31;419}420static inline int rec_cas(struct i5400_error_info *info)421{422 return ((info->recmemb) >> 16) & 0x1fff;423}424static inline int rec_ras(struct i5400_error_info *info)425{426 return (info->recmemb) & 0xffff;427}428 429static struct edac_pci_ctl_info *i5400_pci;430 431/*432 * i5400_get_error_info Retrieve the hardware error information from433 * the hardware and cache it in the 'info'434 * structure435 */436static void i5400_get_error_info(struct mem_ctl_info *mci,437 struct i5400_error_info *info)438{439 struct i5400_pvt *pvt;440 u32 value;441 442 pvt = mci->pvt_info;443 444 /* read in the 1st FATAL error register */445 pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value);446 447 /* Mask only the bits that the doc says are valid448 */449 value &= (FERR_FAT_FBDCHAN | FERR_FAT_MASK);450 451 /* If there is an error, then read in the452 NEXT FATAL error register and the Memory Error Log Register A453 */454 if (value & FERR_FAT_MASK) {455 info->ferr_fat_fbd = value;456 457 /* harvest the various error data we need */458 pci_read_config_dword(pvt->branchmap_werrors,459 NERR_FAT_FBD, &info->nerr_fat_fbd);460 pci_read_config_word(pvt->branchmap_werrors,461 NRECMEMA, &info->nrecmema);462 pci_read_config_dword(pvt->branchmap_werrors,463 NRECMEMB, &info->nrecmemb);464 465 /* Clear the error bits, by writing them back */466 pci_write_config_dword(pvt->branchmap_werrors,467 FERR_FAT_FBD, value);468 } else {469 info->ferr_fat_fbd = 0;470 info->nerr_fat_fbd = 0;471 info->nrecmema = 0;472 info->nrecmemb = 0;473 }474 475 /* read in the 1st NON-FATAL error register */476 pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value);477 478 /* If there is an error, then read in the 1st NON-FATAL error479 * register as well */480 if (value & FERR_NF_MASK) {481 info->ferr_nf_fbd = value;482 483 /* harvest the various error data we need */484 pci_read_config_dword(pvt->branchmap_werrors,485 NERR_NF_FBD, &info->nerr_nf_fbd);486 pci_read_config_word(pvt->branchmap_werrors,487 RECMEMA, &info->recmema);488 pci_read_config_dword(pvt->branchmap_werrors,489 RECMEMB, &info->recmemb);490 pci_read_config_dword(pvt->branchmap_werrors,491 REDMEMB, &info->redmemb);492 493 /* Clear the error bits, by writing them back */494 pci_write_config_dword(pvt->branchmap_werrors,495 FERR_NF_FBD, value);496 } else {497 info->ferr_nf_fbd = 0;498 info->nerr_nf_fbd = 0;499 info->recmema = 0;500 info->recmemb = 0;501 info->redmemb = 0;502 }503}504 505/*506 * i5400_proccess_non_recoverable_info(struct mem_ctl_info *mci,507 * struct i5400_error_info *info,508 * int handle_errors);509 *510 * handle the Intel FATAL and unrecoverable errors, if any511 */512static void i5400_proccess_non_recoverable_info(struct mem_ctl_info *mci,513 struct i5400_error_info *info,514 unsigned long allErrors)515{516 char msg[EDAC_MC_LABEL_LEN + 1 + 90 + 80];517 int branch;518 int channel;519 int bank;520 int buf_id;521 int rank;522 int rdwr;523 int ras, cas;524 int errnum;525 char *type = NULL;526 enum hw_event_mc_err_type tp_event = HW_EVENT_ERR_UNCORRECTED;527 528 if (!allErrors)529 return; /* if no error, return now */530 531 if (allErrors & ERROR_FAT_MASK) {532 type = "FATAL";533 tp_event = HW_EVENT_ERR_FATAL;534 } else if (allErrors & FERR_NF_UNCORRECTABLE)535 type = "NON-FATAL uncorrected";536 else537 type = "NON-FATAL recoverable";538 539 /* ONLY ONE of the possible error bits will be set, as per the docs */540 541 branch = extract_fbdchan_indx(info->ferr_fat_fbd);542 channel = branch;543 544 /* Use the NON-Recoverable macros to extract data */545 bank = nrec_bank(info);546 rank = nrec_rank(info);547 buf_id = nrec_buf_id(info);548 rdwr = nrec_rdwr(info);549 ras = nrec_ras(info);550 cas = nrec_cas(info);551 552 edac_dbg(0, "\t\t%s DIMM= %d Channels= %d,%d (Branch= %d DRAM Bank= %d Buffer ID = %d rdwr= %s ras= %d cas= %d)\n",553 type, rank, channel, channel + 1, branch >> 1, bank,554 buf_id, rdwr_str(rdwr), ras, cas);555 556 /* Only 1 bit will be on */557 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name));558 559 /* Form out message */560 snprintf(msg, sizeof(msg),561 "Bank=%d Buffer ID = %d RAS=%d CAS=%d Err=0x%lx (%s)",562 bank, buf_id, ras, cas, allErrors, error_name[errnum]);563 564 edac_mc_handle_error(tp_event, mci, 1, 0, 0, 0,565 branch >> 1, -1, rank,566 rdwr ? "Write error" : "Read error",567 msg);568}569 570/*571 * i5400_process_fatal_error_info(struct mem_ctl_info *mci,572 * struct i5400_error_info *info,573 * int handle_errors);574 *575 * handle the Intel NON-FATAL errors, if any576 */577static void i5400_process_nonfatal_error_info(struct mem_ctl_info *mci,578 struct i5400_error_info *info)579{580 char msg[EDAC_MC_LABEL_LEN + 1 + 90 + 80];581 unsigned long allErrors;582 int branch;583 int channel;584 int bank;585 int rank;586 int rdwr;587 int ras, cas;588 int errnum;589 590 /* mask off the Error bits that are possible */591 allErrors = from_nf_ferr(info->ferr_nf_fbd & FERR_NF_MASK);592 if (!allErrors)593 return; /* if no error, return now */594 595 /* ONLY ONE of the possible error bits will be set, as per the docs */596 597 if (allErrors & (ERROR_NF_UNCORRECTABLE | ERROR_NF_RECOVERABLE)) {598 i5400_proccess_non_recoverable_info(mci, info, allErrors);599 return;600 }601 602 /* Correctable errors */603 if (allErrors & ERROR_NF_CORRECTABLE) {604 edac_dbg(0, "\tCorrected bits= 0x%lx\n", allErrors);605 606 branch = extract_fbdchan_indx(info->ferr_nf_fbd);607 608 channel = 0;609 if (REC_ECC_LOCATOR_ODD(info->redmemb))610 channel = 1;611 612 /* Convert channel to be based from zero, instead of613 * from branch base of 0 */614 channel += branch;615 616 bank = rec_bank(info);617 rank = rec_rank(info);618 rdwr = rec_rdwr(info);619 ras = rec_ras(info);620 cas = rec_cas(info);621 622 /* Only 1 bit will be on */623 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name));624 625 edac_dbg(0, "\t\tDIMM= %d Channel= %d (Branch %d DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",626 rank, channel, branch >> 1, bank,627 rdwr_str(rdwr), ras, cas);628 629 /* Form out message */630 snprintf(msg, sizeof(msg),631 "Corrected error (Branch=%d DRAM-Bank=%d RDWR=%s "632 "RAS=%d CAS=%d, CE Err=0x%lx (%s))",633 branch >> 1, bank, rdwr_str(rdwr), ras, cas,634 allErrors, error_name[errnum]);635 636 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0,637 branch >> 1, channel % 2, rank,638 rdwr ? "Write error" : "Read error",639 msg);640 641 return;642 }643 644 /* Miscellaneous errors */645 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name));646 647 branch = extract_fbdchan_indx(info->ferr_nf_fbd);648 649 i5400_mc_printk(mci, KERN_EMERG,650 "Non-Fatal misc error (Branch=%d Err=%#lx (%s))",651 branch >> 1, allErrors, error_name[errnum]);652}653 654/*655 * i5400_process_error_info Process the error info that is656 * in the 'info' structure, previously retrieved from hardware657 */658static void i5400_process_error_info(struct mem_ctl_info *mci,659 struct i5400_error_info *info)660{ u32 allErrors;661 662 /* First handle any fatal errors that occurred */663 allErrors = (info->ferr_fat_fbd & FERR_FAT_MASK);664 i5400_proccess_non_recoverable_info(mci, info, allErrors);665 666 /* now handle any non-fatal errors that occurred */667 i5400_process_nonfatal_error_info(mci, info);668}669 670/*671 * i5400_clear_error Retrieve any error from the hardware672 * but do NOT process that error.673 * Used for 'clearing' out of previous errors674 * Called by the Core module.675 */676static void i5400_clear_error(struct mem_ctl_info *mci)677{678 struct i5400_error_info info;679 680 i5400_get_error_info(mci, &info);681}682 683/*684 * i5400_check_error Retrieve and process errors reported by the685 * hardware. Called by the Core module.686 */687static void i5400_check_error(struct mem_ctl_info *mci)688{689 struct i5400_error_info info;690 691 i5400_get_error_info(mci, &info);692 i5400_process_error_info(mci, &info);693}694 695/*696 * i5400_put_devices 'put' all the devices that we have697 * reserved via 'get'698 */699static void i5400_put_devices(struct mem_ctl_info *mci)700{701 struct i5400_pvt *pvt;702 703 pvt = mci->pvt_info;704 705 /* Decrement usage count for devices */706 pci_dev_put(pvt->branch_1);707 pci_dev_put(pvt->branch_0);708 pci_dev_put(pvt->fsb_error_regs);709 pci_dev_put(pvt->branchmap_werrors);710}711 712/*713 * i5400_get_devices Find and perform 'get' operation on the MCH's714 * device/functions we want to reference for this driver715 *716 * Need to 'get' device 16 func 1 and func 2717 */718static int i5400_get_devices(struct mem_ctl_info *mci, int dev_idx)719{720 struct i5400_pvt *pvt;721 struct pci_dev *pdev;722 723 pvt = mci->pvt_info;724 pvt->branchmap_werrors = NULL;725 pvt->fsb_error_regs = NULL;726 pvt->branch_0 = NULL;727 pvt->branch_1 = NULL;728 729 /* Attempt to 'get' the MCH register we want */730 pdev = NULL;731 while (1) {732 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,733 PCI_DEVICE_ID_INTEL_5400_ERR, pdev);734 if (!pdev) {735 /* End of list, leave */736 i5400_printk(KERN_ERR,737 "'system address,Process Bus' "738 "device not found:"739 "vendor 0x%x device 0x%x ERR func 1 "740 "(broken BIOS?)\n",741 PCI_VENDOR_ID_INTEL,742 PCI_DEVICE_ID_INTEL_5400_ERR);743 return -ENODEV;744 }745 746 /* Store device 16 func 1 */747 if (PCI_FUNC(pdev->devfn) == 1)748 break;749 }750 pvt->branchmap_werrors = pdev;751 752 pdev = NULL;753 while (1) {754 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,755 PCI_DEVICE_ID_INTEL_5400_ERR, pdev);756 if (!pdev) {757 /* End of list, leave */758 i5400_printk(KERN_ERR,759 "'system address,Process Bus' "760 "device not found:"761 "vendor 0x%x device 0x%x ERR func 2 "762 "(broken BIOS?)\n",763 PCI_VENDOR_ID_INTEL,764 PCI_DEVICE_ID_INTEL_5400_ERR);765 766 pci_dev_put(pvt->branchmap_werrors);767 return -ENODEV;768 }769 770 /* Store device 16 func 2 */771 if (PCI_FUNC(pdev->devfn) == 2)772 break;773 }774 pvt->fsb_error_regs = pdev;775 776 edac_dbg(1, "System Address, processor bus- PCI Bus ID: %s %x:%x\n",777 pci_name(pvt->system_address),778 pvt->system_address->vendor, pvt->system_address->device);779 edac_dbg(1, "Branchmap, control and errors - PCI Bus ID: %s %x:%x\n",780 pci_name(pvt->branchmap_werrors),781 pvt->branchmap_werrors->vendor,782 pvt->branchmap_werrors->device);783 edac_dbg(1, "FSB Error Regs - PCI Bus ID: %s %x:%x\n",784 pci_name(pvt->fsb_error_regs),785 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device);786 787 pvt->branch_0 = pci_get_device(PCI_VENDOR_ID_INTEL,788 PCI_DEVICE_ID_INTEL_5400_FBD0, NULL);789 if (!pvt->branch_0) {790 i5400_printk(KERN_ERR,791 "MC: 'BRANCH 0' device not found:"792 "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",793 PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_FBD0);794 795 pci_dev_put(pvt->fsb_error_regs);796 pci_dev_put(pvt->branchmap_werrors);797 return -ENODEV;798 }799 800 /* If this device claims to have more than 2 channels then801 * fetch Branch 1's information802 */803 if (pvt->maxch < CHANNELS_PER_BRANCH)804 return 0;805 806 pvt->branch_1 = pci_get_device(PCI_VENDOR_ID_INTEL,807 PCI_DEVICE_ID_INTEL_5400_FBD1, NULL);808 if (!pvt->branch_1) {809 i5400_printk(KERN_ERR,810 "MC: 'BRANCH 1' device not found:"811 "vendor 0x%x device 0x%x Func 0 "812 "(broken BIOS?)\n",813 PCI_VENDOR_ID_INTEL,814 PCI_DEVICE_ID_INTEL_5400_FBD1);815 816 pci_dev_put(pvt->branch_0);817 pci_dev_put(pvt->fsb_error_regs);818 pci_dev_put(pvt->branchmap_werrors);819 return -ENODEV;820 }821 822 return 0;823}824 825/*826 * determine_amb_present827 *828 * the information is contained in DIMMS_PER_CHANNEL different829 * registers determining which of the DIMMS_PER_CHANNEL requires830 * knowing which channel is in question831 *832 * 2 branches, each with 2 channels833 * b0_ambpresent0 for channel '0'834 * b0_ambpresent1 for channel '1'835 * b1_ambpresent0 for channel '2'836 * b1_ambpresent1 for channel '3'837 */838static int determine_amb_present_reg(struct i5400_pvt *pvt, int channel)839{840 int amb_present;841 842 if (channel < CHANNELS_PER_BRANCH) {843 if (channel & 0x1)844 amb_present = pvt->b0_ambpresent1;845 else846 amb_present = pvt->b0_ambpresent0;847 } else {848 if (channel & 0x1)849 amb_present = pvt->b1_ambpresent1;850 else851 amb_present = pvt->b1_ambpresent0;852 }853 854 return amb_present;855}856 857/*858 * determine_mtr(pvt, dimm, channel)859 *860 * return the proper MTR register as determine by the dimm and desired channel861 */862static int determine_mtr(struct i5400_pvt *pvt, int dimm, int channel)863{864 int mtr;865 int n;866 867 /* There is one MTR for each slot pair of FB-DIMMs,868 Each slot pair may be at branch 0 or branch 1.869 */870 n = dimm;871 872 if (n >= DIMMS_PER_CHANNEL) {873 edac_dbg(0, "ERROR: trying to access an invalid dimm: %d\n",874 dimm);875 return 0;876 }877 878 if (channel < CHANNELS_PER_BRANCH)879 mtr = pvt->b0_mtr[n];880 else881 mtr = pvt->b1_mtr[n];882 883 return mtr;884}885 886/*887 */888static void decode_mtr(int slot_row, u16 mtr)889{890 int ans;891 892 ans = MTR_DIMMS_PRESENT(mtr);893 894 edac_dbg(2, "\tMTR%d=0x%x: DIMMs are %sPresent\n",895 slot_row, mtr, ans ? "" : "NOT ");896 if (!ans)897 return;898 899 edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));900 901 edac_dbg(2, "\t\tELECTRICAL THROTTLING is %s\n",902 MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled");903 904 edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));905 edac_dbg(2, "\t\tNUMRANK: %s\n",906 MTR_DIMM_RANK(mtr) ? "double" : "single");907 edac_dbg(2, "\t\tNUMROW: %s\n",908 MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" :909 MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" :910 MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" :911 "65,536 - 16 rows");912 edac_dbg(2, "\t\tNUMCOL: %s\n",913 MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" :914 MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" :915 MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" :916 "reserved");917}918 919static void handle_channel(struct i5400_pvt *pvt, int dimm, int channel,920 struct i5400_dimm_info *dinfo)921{922 int mtr;923 int amb_present_reg;924 int addrBits;925 926 mtr = determine_mtr(pvt, dimm, channel);927 if (MTR_DIMMS_PRESENT(mtr)) {928 amb_present_reg = determine_amb_present_reg(pvt, channel);929 930 /* Determine if there is a DIMM present in this DIMM slot */931 if (amb_present_reg & (1 << dimm)) {932 /* Start with the number of bits for a Bank933 * on the DRAM */934 addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr);935 /* Add thenumber of ROW bits */936 addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);937 /* add the number of COLUMN bits */938 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);939 /* add the number of RANK bits */940 addrBits += MTR_DIMM_RANK(mtr);941 942 addrBits += 6; /* add 64 bits per DIMM */943 addrBits -= 20; /* divide by 2^^20 */944 addrBits -= 3; /* 8 bits per bytes */945 946 dinfo->megabytes = 1 << addrBits;947 }948 }949}950 951/*952 * calculate_dimm_size953 *954 * also will output a DIMM matrix map, if debug is enabled, for viewing955 * how the DIMMs are populated956 */957static void calculate_dimm_size(struct i5400_pvt *pvt)958{959 struct i5400_dimm_info *dinfo;960 int dimm, max_dimms;961 char *p, *mem_buffer;962 int space, n;963 int channel, branch;964 965 /* ================= Generate some debug output ================= */966 space = PAGE_SIZE;967 mem_buffer = p = kmalloc(space, GFP_KERNEL);968 if (p == NULL) {969 i5400_printk(KERN_ERR, "MC: %s:%s() kmalloc() failed\n",970 __FILE__, __func__);971 return;972 }973 974 /* Scan all the actual DIMMS975 * and calculate the information for each DIMM976 * Start with the highest dimm first, to display it first977 * and work toward the 0th dimm978 */979 max_dimms = pvt->maxdimmperch;980 for (dimm = max_dimms - 1; dimm >= 0; dimm--) {981 982 /* on an odd dimm, first output a 'boundary' marker,983 * then reset the message buffer */984 if (dimm & 0x1) {985 n = snprintf(p, space, "---------------------------"986 "-------------------------------");987 p += n;988 space -= n;989 edac_dbg(2, "%s\n", mem_buffer);990 p = mem_buffer;991 space = PAGE_SIZE;992 }993 n = snprintf(p, space, "dimm %2d ", dimm);994 p += n;995 space -= n;996 997 for (channel = 0; channel < pvt->maxch; channel++) {998 dinfo = &pvt->dimm_info[dimm][channel];999 handle_channel(pvt, dimm, channel, dinfo);1000 n = snprintf(p, space, "%4d MB | ", dinfo->megabytes);1001 p += n;1002 space -= n;1003 }1004 edac_dbg(2, "%s\n", mem_buffer);1005 p = mem_buffer;1006 space = PAGE_SIZE;1007 }1008 1009 /* Output the last bottom 'boundary' marker */1010 n = snprintf(p, space, "---------------------------"1011 "-------------------------------");1012 p += n;1013 space -= n;1014 edac_dbg(2, "%s\n", mem_buffer);1015 p = mem_buffer;1016 space = PAGE_SIZE;1017 1018 /* now output the 'channel' labels */1019 n = snprintf(p, space, " ");1020 p += n;1021 space -= n;1022 for (channel = 0; channel < pvt->maxch; channel++) {1023 n = snprintf(p, space, "channel %d | ", channel);1024 p += n;1025 space -= n;1026 }1027 1028 space -= n;1029 edac_dbg(2, "%s\n", mem_buffer);1030 p = mem_buffer;1031 space = PAGE_SIZE;1032 1033 n = snprintf(p, space, " ");1034 p += n;1035 for (branch = 0; branch < MAX_BRANCHES; branch++) {1036 n = snprintf(p, space, " branch %d | ", branch);1037 p += n;1038 space -= n;1039 }1040 1041 /* output the last message and free buffer */1042 edac_dbg(2, "%s\n", mem_buffer);1043 kfree(mem_buffer);1044}1045 1046/*1047 * i5400_get_mc_regs read in the necessary registers and1048 * cache locally1049 *1050 * Fills in the private data members1051 */1052static void i5400_get_mc_regs(struct mem_ctl_info *mci)1053{1054 struct i5400_pvt *pvt;1055 u32 actual_tolm;1056 u16 limit;1057 int slot_row;1058 int way0, way1;1059 1060 pvt = mci->pvt_info;1061 1062 pci_read_config_dword(pvt->system_address, AMBASE,1063 &pvt->u.ambase_bottom);1064 pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32),1065 &pvt->u.ambase_top);1066 1067 edac_dbg(2, "AMBASE= 0x%lx MAXCH= %d MAX-DIMM-Per-CH= %d\n",1068 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch);1069 1070 /* Get the Branch Map regs */1071 pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm);1072 pvt->tolm >>= 12;1073 edac_dbg(2, "\nTOLM (number of 256M regions) =%u (0x%x)\n",1074 pvt->tolm, pvt->tolm);1075 1076 actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28));1077 edac_dbg(2, "Actual TOLM byte addr=%u.%03u GB (0x%x)\n",1078 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28);1079 1080 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0);1081 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1);1082 1083 /* Get the MIR[0-1] regs */1084 limit = (pvt->mir0 >> 4) & 0x0fff;1085 way0 = pvt->mir0 & 0x1;1086 way1 = pvt->mir0 & 0x2;1087 edac_dbg(2, "MIR0: limit= 0x%x WAY1= %u WAY0= %x\n",1088 limit, way1, way0);1089 limit = (pvt->mir1 >> 4) & 0xfff;1090 way0 = pvt->mir1 & 0x1;1091 way1 = pvt->mir1 & 0x2;1092 edac_dbg(2, "MIR1: limit= 0x%x WAY1= %u WAY0= %x\n",1093 limit, way1, way0);1094 1095 /* Get the set of MTR[0-3] regs by each branch */1096 for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++) {1097 int where = MTR0 + (slot_row * sizeof(u16));1098 1099 /* Branch 0 set of MTR registers */1100 pci_read_config_word(pvt->branch_0, where,1101 &pvt->b0_mtr[slot_row]);1102 1103 edac_dbg(2, "MTR%d where=0x%x B0 value=0x%x\n",1104 slot_row, where, pvt->b0_mtr[slot_row]);1105 1106 if (pvt->maxch < CHANNELS_PER_BRANCH) {1107 pvt->b1_mtr[slot_row] = 0;1108 continue;1109 }1110 1111 /* Branch 1 set of MTR registers */1112 pci_read_config_word(pvt->branch_1, where,1113 &pvt->b1_mtr[slot_row]);1114 edac_dbg(2, "MTR%d where=0x%x B1 value=0x%x\n",1115 slot_row, where, pvt->b1_mtr[slot_row]);1116 }1117 1118 /* Read and dump branch 0's MTRs */1119 edac_dbg(2, "Memory Technology Registers:\n");1120 edac_dbg(2, " Branch 0:\n");1121 for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++)1122 decode_mtr(slot_row, pvt->b0_mtr[slot_row]);1123 1124 pci_read_config_word(pvt->branch_0, AMBPRESENT_0,1125 &pvt->b0_ambpresent0);1126 edac_dbg(2, "\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0);1127 pci_read_config_word(pvt->branch_0, AMBPRESENT_1,1128 &pvt->b0_ambpresent1);1129 edac_dbg(2, "\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);1130 1131 /* Only if we have 2 branchs (4 channels) */1132 if (pvt->maxch < CHANNELS_PER_BRANCH) {1133 pvt->b1_ambpresent0 = 0;1134 pvt->b1_ambpresent1 = 0;1135 } else {1136 /* Read and dump branch 1's MTRs */1137 edac_dbg(2, " Branch 1:\n");1138 for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++)1139 decode_mtr(slot_row, pvt->b1_mtr[slot_row]);1140 1141 pci_read_config_word(pvt->branch_1, AMBPRESENT_0,1142 &pvt->b1_ambpresent0);1143 edac_dbg(2, "\t\tAMB-Branch 1-present0 0x%x:\n",1144 pvt->b1_ambpresent0);1145 pci_read_config_word(pvt->branch_1, AMBPRESENT_1,1146 &pvt->b1_ambpresent1);1147 edac_dbg(2, "\t\tAMB-Branch 1-present1 0x%x:\n",1148 pvt->b1_ambpresent1);1149 }1150 1151 /* Go and determine the size of each DIMM and place in an1152 * orderly matrix */1153 calculate_dimm_size(pvt);1154}1155 1156/*1157 * i5400_init_dimms Initialize the 'dimms' table within1158 * the mci control structure with the1159 * addressing of memory.1160 *1161 * return:1162 * 0 success1163 * 1 no actual memory found on this MC1164 */1165static int i5400_init_dimms(struct mem_ctl_info *mci)1166{1167 struct i5400_pvt *pvt;1168 struct dimm_info *dimm;1169 int ndimms;1170 int mtr;1171 int size_mb;1172 int channel, slot;1173 1174 pvt = mci->pvt_info;1175 1176 ndimms = 0;1177 1178 /*1179 * FIXME: remove pvt->dimm_info[slot][channel] and use the 31180 * layers here.1181 */1182 for (channel = 0; channel < mci->layers[0].size * mci->layers[1].size;1183 channel++) {1184 for (slot = 0; slot < mci->layers[2].size; slot++) {1185 mtr = determine_mtr(pvt, slot, channel);1186 1187 /* if no DIMMS on this slot, continue */1188 if (!MTR_DIMMS_PRESENT(mtr))1189 continue;1190 1191 dimm = edac_get_dimm(mci, channel / 2, channel % 2, slot);1192 1193 size_mb = pvt->dimm_info[slot][channel].megabytes;1194 1195 edac_dbg(2, "dimm (branch %d channel %d slot %d): %d.%03d GB\n",1196 channel / 2, channel % 2, slot,1197 size_mb / 1000, size_mb % 1000);1198 1199 dimm->nr_pages = size_mb << 8;1200 dimm->grain = 8;1201 dimm->dtype = MTR_DRAM_WIDTH(mtr) == 8 ?1202 DEV_X8 : DEV_X4;1203 dimm->mtype = MEM_FB_DDR2;1204 /*1205 * The eccc mechanism is SDDC (aka SECC), with1206 * is similar to Chipkill.1207 */1208 dimm->edac_mode = MTR_DRAM_WIDTH(mtr) == 8 ?1209 EDAC_S8ECD8ED : EDAC_S4ECD4ED;1210 ndimms++;1211 }1212 }1213 1214 /*1215 * When just one memory is provided, it should be at location (0,0,0).1216 * With such single-DIMM mode, the SDCC algorithm degrades to SECDEC+.1217 */1218 if (ndimms == 1)1219 mci->dimms[0]->edac_mode = EDAC_SECDED;1220 1221 return (ndimms == 0);1222}1223 1224/*1225 * i5400_enable_error_reporting1226 * Turn on the memory reporting features of the hardware1227 */1228static void i5400_enable_error_reporting(struct mem_ctl_info *mci)1229{1230 struct i5400_pvt *pvt;1231 u32 fbd_error_mask;1232 1233 pvt = mci->pvt_info;1234 1235 /* Read the FBD Error Mask Register */1236 pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD,1237 &fbd_error_mask);1238 1239 /* Enable with a '0' */1240 fbd_error_mask &= ~(ENABLE_EMASK_ALL);1241 1242 pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD,1243 fbd_error_mask);1244}1245 1246/*1247 * i5400_probe1 Probe for ONE instance of device to see if it is1248 * present.1249 * return:1250 * 0 for FOUND a device1251 * < 0 for error code1252 */1253static int i5400_probe1(struct pci_dev *pdev, int dev_idx)1254{1255 struct mem_ctl_info *mci;1256 struct i5400_pvt *pvt;1257 struct edac_mc_layer layers[3];1258 1259 if (dev_idx >= ARRAY_SIZE(i5400_devs))1260 return -EINVAL;1261 1262 edac_dbg(0, "MC: pdev bus %u dev=0x%x fn=0x%x\n",1263 pdev->bus->number,1264 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));1265 1266 /* We only are looking for func 0 of the set */1267 if (PCI_FUNC(pdev->devfn) != 0)1268 return -ENODEV;1269 1270 /*1271 * allocate a new MC control structure1272 *1273 * This drivers uses the DIMM slot as "csrow" and the rest as "channel".1274 */1275 layers[0].type = EDAC_MC_LAYER_BRANCH;1276 layers[0].size = MAX_BRANCHES;1277 layers[0].is_virt_csrow = false;1278 layers[1].type = EDAC_MC_LAYER_CHANNEL;1279 layers[1].size = CHANNELS_PER_BRANCH;1280 layers[1].is_virt_csrow = false;1281 layers[2].type = EDAC_MC_LAYER_SLOT;1282 layers[2].size = DIMMS_PER_CHANNEL;1283 layers[2].is_virt_csrow = true;1284 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));1285 if (mci == NULL)1286 return -ENOMEM;1287 1288 edac_dbg(0, "MC: mci = %p\n", mci);1289 1290 mci->pdev = &pdev->dev; /* record ptr to the generic device */1291 1292 pvt = mci->pvt_info;1293 pvt->system_address = pdev; /* Record this device in our private */1294 pvt->maxch = MAX_CHANNELS;1295 pvt->maxdimmperch = DIMMS_PER_CHANNEL;1296 1297 /* 'get' the pci devices we want to reserve for our use */1298 if (i5400_get_devices(mci, dev_idx))1299 goto fail0;1300 1301 /* Time to get serious */1302 i5400_get_mc_regs(mci); /* retrieve the hardware registers */1303 1304 mci->mc_idx = 0;1305 mci->mtype_cap = MEM_FLAG_FB_DDR2;1306 mci->edac_ctl_cap = EDAC_FLAG_NONE;1307 mci->edac_cap = EDAC_FLAG_NONE;1308 mci->mod_name = "i5400_edac.c";1309 mci->ctl_name = i5400_devs[dev_idx].ctl_name;1310 mci->dev_name = pci_name(pdev);1311 mci->ctl_page_to_phys = NULL;1312 1313 /* Set the function pointer to an actual operation function */1314 mci->edac_check = i5400_check_error;1315 1316 /* initialize the MC control structure 'dimms' table1317 * with the mapping and control information */1318 if (i5400_init_dimms(mci)) {1319 edac_dbg(0, "MC: Setting mci->edac_cap to EDAC_FLAG_NONE because i5400_init_dimms() returned nonzero value\n");1320 mci->edac_cap = EDAC_FLAG_NONE; /* no dimms found */1321 } else {1322 edac_dbg(1, "MC: Enable error reporting now\n");1323 i5400_enable_error_reporting(mci);1324 }1325 1326 /* add this new MC control structure to EDAC's list of MCs */1327 if (edac_mc_add_mc(mci)) {1328 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");1329 /* FIXME: perhaps some code should go here that disables error1330 * reporting if we just enabled it1331 */1332 goto fail1;1333 }1334 1335 i5400_clear_error(mci);1336 1337 /* allocating generic PCI control info */1338 i5400_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);1339 if (!i5400_pci) {1340 printk(KERN_WARNING1341 "%s(): Unable to create PCI control\n",1342 __func__);1343 printk(KERN_WARNING1344 "%s(): PCI error report via EDAC not setup\n",1345 __func__);1346 }1347 1348 return 0;1349 1350 /* Error exit unwinding stack */1351fail1:1352 1353 i5400_put_devices(mci);1354 1355fail0:1356 edac_mc_free(mci);1357 return -ENODEV;1358}1359 1360/*1361 * i5400_init_one constructor for one instance of device1362 *1363 * returns:1364 * negative on error1365 * count (>= 0)1366 */1367static int i5400_init_one(struct pci_dev *pdev, const struct pci_device_id *id)1368{1369 int rc;1370 1371 edac_dbg(0, "MC:\n");1372 1373 /* wake up device */1374 rc = pci_enable_device(pdev);1375 if (rc)1376 return rc;1377 1378 /* now probe and enable the device */1379 return i5400_probe1(pdev, id->driver_data);1380}1381 1382/*1383 * i5400_remove_one destructor for one instance of device1384 *1385 */1386static void i5400_remove_one(struct pci_dev *pdev)1387{1388 struct mem_ctl_info *mci;1389 1390 edac_dbg(0, "\n");1391 1392 if (i5400_pci)1393 edac_pci_release_generic_ctl(i5400_pci);1394 1395 mci = edac_mc_del_mc(&pdev->dev);1396 if (!mci)1397 return;1398 1399 /* retrieve references to resources, and free those resources */1400 i5400_put_devices(mci);1401 1402 pci_disable_device(pdev);1403 1404 edac_mc_free(mci);1405}1406 1407/*1408 * pci_device_id table for which devices we are looking for1409 *1410 * The "E500P" device is the first device supported.1411 */1412static const struct pci_device_id i5400_pci_tbl[] = {1413 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_ERR)},1414 {0,} /* 0 terminated list. */1415};1416 1417MODULE_DEVICE_TABLE(pci, i5400_pci_tbl);1418 1419/*1420 * i5400_driver pci_driver structure for this module1421 *1422 */1423static struct pci_driver i5400_driver = {1424 .name = "i5400_edac",1425 .probe = i5400_init_one,1426 .remove = i5400_remove_one,1427 .id_table = i5400_pci_tbl,1428};1429 1430/*1431 * i5400_init Module entry function1432 * Try to initialize this module for its devices1433 */1434static int __init i5400_init(void)1435{1436 int pci_rc;1437 1438 edac_dbg(2, "MC:\n");1439 1440 /* Ensure that the OPSTATE is set correctly for POLL or NMI */1441 opstate_init();1442 1443 pci_rc = pci_register_driver(&i5400_driver);1444 1445 return (pci_rc < 0) ? pci_rc : 0;1446}1447 1448/*1449 * i5400_exit() Module exit function1450 * Unregister the driver1451 */1452static void __exit i5400_exit(void)1453{1454 edac_dbg(2, "MC:\n");1455 pci_unregister_driver(&i5400_driver);1456}1457 1458module_init(i5400_init);1459module_exit(i5400_exit);1460 1461MODULE_LICENSE("GPL");1462MODULE_AUTHOR("Ben Woodard <woodard@redhat.com>");1463MODULE_AUTHOR("Mauro Carvalho Chehab");1464MODULE_AUTHOR("Red Hat Inc. (https://www.redhat.com)");1465MODULE_DESCRIPTION("MC Driver for Intel I5400 memory controllers - "1466 I5400_REVISION);1467 1468module_param(edac_op_state, int, 0444);1469MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");1470