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1/*2 * Freescale Memory Controller kernel module3 *4 * Author: York Sun <york.sun@nxp.com>5 *6 * Copyright 2016 NXP Semiconductor7 *8 * Derived from mpc85xx_edac.c9 * Author: Dave Jiang <djiang@mvista.com>10 *11 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under12 * the terms of the GNU General Public License version 2. This program13 * is licensed "as is" without any warranty of any kind, whether express14 * or implied.15 */16 17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt18 19#include "edac_module.h"20#include "fsl_ddr_edac.h"21 22static const struct of_device_id fsl_ddr_mc_err_of_match[] = {23 { .compatible = "fsl,qoriq-memory-controller", },24 {},25};26MODULE_DEVICE_TABLE(of, fsl_ddr_mc_err_of_match);27 28static struct platform_driver fsl_ddr_mc_err_driver = {29 .probe = fsl_mc_err_probe,30 .remove_new = fsl_mc_err_remove,31 .driver = {32 .name = "fsl_ddr_mc_err",33 .of_match_table = fsl_ddr_mc_err_of_match,34 },35};36 37static int __init fsl_ddr_mc_init(void)38{39 int res;40 41 if (ghes_get_devices())42 return -EBUSY;43 44 /* make sure error reporting method is sane */45 switch (edac_op_state) {46 case EDAC_OPSTATE_POLL:47 case EDAC_OPSTATE_INT:48 break;49 default:50 edac_op_state = EDAC_OPSTATE_INT;51 break;52 }53 54 res = platform_driver_register(&fsl_ddr_mc_err_driver);55 if (res) {56 pr_err("MC fails to register\n");57 return res;58 }59 60 return 0;61}62 63module_init(fsl_ddr_mc_init);64 65static void __exit fsl_ddr_mc_exit(void)66{67 platform_driver_unregister(&fsl_ddr_mc_err_driver);68}69 70module_exit(fsl_ddr_mc_exit);71 72MODULE_DESCRIPTION("Freescale Layerscape EDAC driver");73MODULE_LICENSE("GPL");74MODULE_AUTHOR("NXP Semiconductor");75module_param(edac_op_state, int, 0444);76MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll, 2=Interrupt");77