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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Freescale MPC85xx Memory Controller kernel module4 * Author: Dave Jiang <djiang@mvista.com>5 *6 * 2006-2007 (c) MontaVista Software, Inc.7 */8#ifndef _MPC85XX_EDAC_H_9#define _MPC85XX_EDAC_H_10 11#define MPC85XX_REVISION " Ver: 2.0.0"12#define EDAC_MOD_STR "MPC85xx_edac"13 14#define mpc85xx_printk(level, fmt, arg...) \15 edac_printk(level, "MPC85xx", fmt, ##arg)16 17/*18 * L2 Err defines19 */20#define MPC85XX_L2_ERRINJHI 0x000021#define MPC85XX_L2_ERRINJLO 0x000422#define MPC85XX_L2_ERRINJCTL 0x000823#define MPC85XX_L2_CAPTDATAHI 0x002024#define MPC85XX_L2_CAPTDATALO 0x002425#define MPC85XX_L2_CAPTECC 0x002826#define MPC85XX_L2_ERRDET 0x004027#define MPC85XX_L2_ERRDIS 0x004428#define MPC85XX_L2_ERRINTEN 0x004829#define MPC85XX_L2_ERRATTR 0x004c30#define MPC85XX_L2_ERRADDR 0x005031#define MPC85XX_L2_ERRCTL 0x005832 33/* Error Interrupt Enable */34#define L2_EIE_L2CFGINTEN 0x135#define L2_EIE_SBECCINTEN 0x436#define L2_EIE_MBECCINTEN 0x837#define L2_EIE_TPARINTEN 0x1038#define L2_EIE_MASK (L2_EIE_L2CFGINTEN | L2_EIE_SBECCINTEN | \39 L2_EIE_MBECCINTEN | L2_EIE_TPARINTEN)40 41/* Error Detect */42#define L2_EDE_L2CFGERR 0x143#define L2_EDE_SBECCERR 0x444#define L2_EDE_MBECCERR 0x845#define L2_EDE_TPARERR 0x1046#define L2_EDE_MULL2ERR 0x8000000047 48#define L2_EDE_CE_MASK L2_EDE_SBECCERR49#define L2_EDE_UE_MASK (L2_EDE_L2CFGERR | L2_EDE_MBECCERR | \50 L2_EDE_TPARERR)51#define L2_EDE_MASK (L2_EDE_L2CFGERR | L2_EDE_SBECCERR | \52 L2_EDE_MBECCERR | L2_EDE_TPARERR | L2_EDE_MULL2ERR)53 54/*55 * PCI Err defines56 */57#define PCI_EDE_TOE 0x0000000158#define PCI_EDE_SCM 0x0000000259#define PCI_EDE_IRMSV 0x0000000460#define PCI_EDE_ORMSV 0x0000000861#define PCI_EDE_OWMSV 0x0000001062#define PCI_EDE_TGT_ABRT 0x0000002063#define PCI_EDE_MST_ABRT 0x0000004064#define PCI_EDE_TGT_PERR 0x0000008065#define PCI_EDE_MST_PERR 0x0000010066#define PCI_EDE_RCVD_SERR 0x0000020067#define PCI_EDE_ADDR_PERR 0x0000040068#define PCI_EDE_MULTI_ERR 0x8000000069 70#define PCI_EDE_PERR_MASK (PCI_EDE_TGT_PERR | PCI_EDE_MST_PERR | \71 PCI_EDE_ADDR_PERR)72 73#define MPC85XX_PCI_ERR_DR 0x000074#define MPC85XX_PCI_ERR_CAP_DR 0x000475#define MPC85XX_PCI_ERR_EN 0x000876#define PEX_ERR_ICCAIE_EN_BIT 0x0002000077#define MPC85XX_PCI_ERR_ATTRIB 0x000c78#define MPC85XX_PCI_ERR_ADDR 0x001079#define PEX_ERR_ICCAD_DISR_BIT 0x0002000080#define MPC85XX_PCI_ERR_EXT_ADDR 0x001481#define MPC85XX_PCI_ERR_DL 0x001882#define MPC85XX_PCI_ERR_DH 0x001c83#define MPC85XX_PCI_GAS_TIMR 0x002084#define MPC85XX_PCI_PCIX_TIMR 0x002485#define MPC85XX_PCIE_ERR_CAP_R0 0x002886#define MPC85XX_PCIE_ERR_CAP_R1 0x002c87#define MPC85XX_PCIE_ERR_CAP_R2 0x003088#define MPC85XX_PCIE_ERR_CAP_R3 0x003489 90struct mpc85xx_l2_pdata {91 char *name;92 int edac_idx;93 void __iomem *l2_vbase;94 int irq;95};96 97struct mpc85xx_pci_pdata {98 char *name;99 bool is_pcie;100 int edac_idx;101 void __iomem *pci_vbase;102 int irq;103};104 105#endif106