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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Common codes for both the skx_edac driver and Intel 10nm server EDAC driver.4 * Originally split out from the skx_edac driver.5 *6 * Copyright (c) 2018, Intel Corporation.7 */8 9#ifndef _SKX_COMM_EDAC_H10#define _SKX_COMM_EDAC_H11 12#include <linux/bits.h>13#include <asm/mce.h>14 15#define MSG_SIZE 102416 17/*18 * Debug macros19 */20#define skx_printk(level, fmt, arg...) \21 edac_printk(level, "skx", fmt, ##arg)22 23#define skx_mc_printk(mci, level, fmt, arg...) \24 edac_mc_chipset_printk(mci, level, "skx", fmt, ##arg)25 26/*27 * Get a bit field at register value <v>, from bit <lo> to bit <hi>28 */29#define GET_BITFIELD(v, lo, hi) \30 (((v) & GENMASK_ULL((hi), (lo))) >> (lo))31 32#define SKX_NUM_IMC 2 /* Memory controllers per socket */33#define SKX_NUM_CHANNELS 3 /* Channels per memory controller */34#define SKX_NUM_DIMMS 2 /* Max DIMMS per channel */35 36#define I10NM_NUM_DDR_IMC 1237#define I10NM_NUM_DDR_CHANNELS 238#define I10NM_NUM_DDR_DIMMS 239 40#define I10NM_NUM_HBM_IMC 1641#define I10NM_NUM_HBM_CHANNELS 242#define I10NM_NUM_HBM_DIMMS 143 44#define I10NM_NUM_IMC (I10NM_NUM_DDR_IMC + I10NM_NUM_HBM_IMC)45#define I10NM_NUM_CHANNELS MAX(I10NM_NUM_DDR_CHANNELS, I10NM_NUM_HBM_CHANNELS)46#define I10NM_NUM_DIMMS MAX(I10NM_NUM_DDR_DIMMS, I10NM_NUM_HBM_DIMMS)47 48#define NUM_IMC MAX(SKX_NUM_IMC, I10NM_NUM_IMC)49#define NUM_CHANNELS MAX(SKX_NUM_CHANNELS, I10NM_NUM_CHANNELS)50#define NUM_DIMMS MAX(SKX_NUM_DIMMS, I10NM_NUM_DIMMS)51 52#define IS_DIMM_PRESENT(r) GET_BITFIELD(r, 15, 15)53#define IS_NVDIMM_PRESENT(r, i) GET_BITFIELD(r, i, i)54 55#define MCI_MISC_ECC_MODE(m) (((m) >> 59) & 15)56#define MCI_MISC_ECC_DDRT 8 /* read from DDRT */57 58/*59 * According to Intel Architecture spec vol 3B,60 * Table 15-10 "IA32_MCi_Status [15:0] Compound Error Code Encoding"61 * memory errors should fit one of these masks:62 * 000f 0000 1mmm cccc (binary)63 * 000f 0010 1mmm cccc (binary) [RAM used as cache]64 * where:65 * f = Correction Report Filtering Bit. If 1, subsequent errors66 * won't be shown67 * mmm = error type68 * cccc = channel69 */70#define MCACOD_MEM_ERR_MASK 0xef8071/*72 * Errors from either the memory of the 1-level memory system or the73 * 2nd level memory (the slow "far" memory) of the 2-level memory system.74 */75#define MCACOD_MEM_CTL_ERR 0x8076/*77 * Errors from the 1st level memory (the fast "near" memory as cache)78 * of the 2-level memory system.79 */80#define MCACOD_EXT_MEM_ERR 0x28081 82/*83 * Each cpu socket contains some pci devices that provide global84 * information, and also some that are local to each of the two85 * memory controllers on the die.86 */87struct skx_dev {88 struct list_head list;89 u8 bus[4];90 int seg;91 struct pci_dev *sad_all;92 struct pci_dev *util_all;93 struct pci_dev *uracu; /* for i10nm CPU */94 struct pci_dev *pcu_cr3; /* for HBM memory detection */95 u32 mcroute;96 struct skx_imc {97 struct mem_ctl_info *mci;98 struct pci_dev *mdev; /* for i10nm CPU */99 void __iomem *mbase; /* for i10nm CPU */100 int chan_mmio_sz; /* for i10nm CPU */101 int num_channels; /* channels per memory controller */102 int num_dimms; /* dimms per channel */103 bool hbm_mc;104 u8 mc; /* system wide mc# */105 u8 lmc; /* socket relative mc# */106 u8 src_id, node_id;107 struct skx_channel {108 struct pci_dev *cdev;109 struct pci_dev *edev;110 u32 retry_rd_err_log_s;111 u32 retry_rd_err_log_d;112 u32 retry_rd_err_log_d2;113 struct skx_dimm {114 u8 close_pg;115 u8 bank_xor_enable;116 u8 fine_grain_bank;117 u8 rowbits;118 u8 colbits;119 } dimms[NUM_DIMMS];120 } chan[NUM_CHANNELS];121 } imc[NUM_IMC];122};123 124struct skx_pvt {125 struct skx_imc *imc;126};127 128enum type {129 SKX,130 I10NM,131 SPR,132 GNR133};134 135enum {136 INDEX_SOCKET,137 INDEX_MEMCTRL,138 INDEX_CHANNEL,139 INDEX_DIMM,140 INDEX_CS,141 INDEX_NM_FIRST,142 INDEX_NM_MEMCTRL = INDEX_NM_FIRST,143 INDEX_NM_CHANNEL,144 INDEX_NM_DIMM,145 INDEX_NM_CS,146 INDEX_MAX147};148 149#define BIT_NM_MEMCTRL BIT_ULL(INDEX_NM_MEMCTRL)150#define BIT_NM_CHANNEL BIT_ULL(INDEX_NM_CHANNEL)151#define BIT_NM_DIMM BIT_ULL(INDEX_NM_DIMM)152#define BIT_NM_CS BIT_ULL(INDEX_NM_CS)153 154struct decoded_addr {155 struct mce *mce;156 struct skx_dev *dev;157 u64 addr;158 int socket;159 int imc;160 int channel;161 u64 chan_addr;162 int sktways;163 int chanways;164 int dimm;165 int cs;166 int rank;167 int channel_rank;168 u64 rank_address;169 int row;170 int column;171 int bank_address;172 int bank_group;173 bool decoded_by_adxl;174};175 176struct pci_bdf {177 u32 bus : 8;178 u32 dev : 5;179 u32 fun : 3;180};181 182struct res_config {183 enum type type;184 /* Configuration agent device ID */185 unsigned int decs_did;186 /* Default bus number configuration register offset */187 int busno_cfg_offset;188 /* DDR memory controllers per socket */189 int ddr_imc_num;190 /* DDR channels per DDR memory controller */191 int ddr_chan_num;192 /* DDR DIMMs per DDR memory channel */193 int ddr_dimm_num;194 /* Per DDR channel memory-mapped I/O size */195 int ddr_chan_mmio_sz;196 /* HBM memory controllers per socket */197 int hbm_imc_num;198 /* HBM channels per HBM memory controller */199 int hbm_chan_num;200 /* HBM DIMMs per HBM memory channel */201 int hbm_dimm_num;202 /* Per HBM channel memory-mapped I/O size */203 int hbm_chan_mmio_sz;204 bool support_ddr5;205 /* SAD device BDF */206 struct pci_bdf sad_all_bdf;207 /* PCU device BDF */208 struct pci_bdf pcu_cr3_bdf;209 /* UTIL device BDF */210 struct pci_bdf util_all_bdf;211 /* URACU device BDF */212 struct pci_bdf uracu_bdf;213 /* DDR mdev device BDF */214 struct pci_bdf ddr_mdev_bdf;215 /* HBM mdev device BDF */216 struct pci_bdf hbm_mdev_bdf;217 int sad_all_offset;218 /* Offsets of retry_rd_err_log registers */219 u32 *offsets_scrub;220 u32 *offsets_scrub_hbm0;221 u32 *offsets_scrub_hbm1;222 u32 *offsets_demand;223 u32 *offsets_demand2;224 u32 *offsets_demand_hbm0;225 u32 *offsets_demand_hbm1;226};227 228typedef int (*get_dimm_config_f)(struct mem_ctl_info *mci,229 struct res_config *cfg);230typedef bool (*skx_decode_f)(struct decoded_addr *res);231typedef void (*skx_show_retry_log_f)(struct decoded_addr *res, char *msg, int len, bool scrub_err);232 233int skx_adxl_get(void);234void skx_adxl_put(void);235void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log);236void skx_set_mem_cfg(bool mem_cfg_2lm);237 238int skx_get_src_id(struct skx_dev *d, int off, u8 *id);239int skx_get_node_id(struct skx_dev *d, u8 *id);240 241int skx_get_all_bus_mappings(struct res_config *cfg, struct list_head **list);242 243int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm);244 245int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm,246 struct skx_imc *imc, int chan, int dimmno,247 struct res_config *cfg);248 249int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc,250 int chan, int dimmno, const char *mod_str);251 252int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev,253 const char *ctl_name, const char *mod_str,254 get_dimm_config_f get_dimm_config,255 struct res_config *cfg);256 257int skx_mce_check_error(struct notifier_block *nb, unsigned long val,258 void *data);259 260void skx_remove(void);261 262#ifdef CONFIG_EDAC_DEBUG263void skx_setup_debug(const char *name);264void skx_teardown_debug(void);265#else266static inline void skx_setup_debug(const char *name) {}267static inline void skx_teardown_debug(void) {}268#endif269 270#endif /* _SKX_COMM_EDAC_H */271