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1// SPDX-License-Identifier: GPL-2.0-only2#include <linux/efi.h>3 4#include <asm/boot.h>5#include <asm/desc.h>6#include <asm/efi.h>7 8#include "efistub.h"9#include "x86-stub.h"10 11bool efi_no5lvl;12 13static void (*la57_toggle)(void *cr3);14 15static const struct desc_struct gdt[] = {16 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(DESC_CODE32, 0, 0xfffff),17 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(DESC_CODE64, 0, 0xfffff),18};19 20/*21 * Enabling (or disabling) 5 level paging is tricky, because it can only be22 * done from 32-bit mode with paging disabled. This means not only that the23 * code itself must be running from 32-bit addressable physical memory, but24 * also that the root page table must be 32-bit addressable, as programming25 * a 64-bit value into CR3 when running in 32-bit mode is not supported.26 */27efi_status_t efi_setup_5level_paging(void)28{29 u8 tmpl_size = (u8 *)&trampoline_ljmp_imm_offset - (u8 *)&trampoline_32bit_src;30 efi_status_t status;31 u8 *la57_code;32 33 if (!efi_is_64bit())34 return EFI_SUCCESS;35 36 /* check for 5 level paging support */37 if (native_cpuid_eax(0) < 7 ||38 !(native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31))))39 return EFI_SUCCESS;40 41 /* allocate some 32-bit addressable memory for code and a page table */42 status = efi_allocate_pages(2 * PAGE_SIZE, (unsigned long *)&la57_code,43 U32_MAX);44 if (status != EFI_SUCCESS)45 return status;46 47 la57_toggle = memcpy(la57_code, trampoline_32bit_src, tmpl_size);48 memset(la57_code + tmpl_size, 0x90, PAGE_SIZE - tmpl_size);49 50 /*51 * To avoid the need to allocate a 32-bit addressable stack, the52 * trampoline uses a LJMP instruction to switch back to long mode.53 * LJMP takes an absolute destination address, which needs to be54 * fixed up at runtime.55 */56 *(u32 *)&la57_code[trampoline_ljmp_imm_offset] += (unsigned long)la57_code;57 58 efi_adjust_memory_range_protection((unsigned long)la57_toggle, PAGE_SIZE);59 60 return EFI_SUCCESS;61}62 63void efi_5level_switch(void)64{65 bool want_la57 = IS_ENABLED(CONFIG_X86_5LEVEL) && !efi_no5lvl;66 bool have_la57 = native_read_cr4() & X86_CR4_LA57;67 bool need_toggle = want_la57 ^ have_la57;68 u64 *pgt = (void *)la57_toggle + PAGE_SIZE;69 u64 *cr3 = (u64 *)__native_read_cr3();70 u64 *new_cr3;71 72 if (!la57_toggle || !need_toggle)73 return;74 75 if (!have_la57) {76 /*77 * 5 level paging will be enabled, so a root level page needs78 * to be allocated from the 32-bit addressable physical region,79 * with its first entry referring to the existing hierarchy.80 */81 new_cr3 = memset(pgt, 0, PAGE_SIZE);82 new_cr3[0] = (u64)cr3 | _PAGE_TABLE_NOENC;83 } else {84 /* take the new root table pointer from the current entry #0 */85 new_cr3 = (u64 *)(cr3[0] & PAGE_MASK);86 87 /* copy the new root table if it is not 32-bit addressable */88 if ((u64)new_cr3 > U32_MAX)89 new_cr3 = memcpy(pgt, new_cr3, PAGE_SIZE);90 }91 92 native_load_gdt(&(struct desc_ptr){ sizeof(gdt) - 1, (u64)gdt });93 94 la57_toggle(new_cr3);95}96