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1/* SPDX-License-Identifier: GPL-2.0-only */2/* Copyright (c) 2010-2015,2019 The Linux Foundation. All rights reserved.3 */4#ifndef __QCOM_SCM_INT_H5#define __QCOM_SCM_INT_H6 7struct device;8struct qcom_tzmem_pool;9 10enum qcom_scm_convention {11 SMC_CONVENTION_UNKNOWN,12 SMC_CONVENTION_LEGACY,13 SMC_CONVENTION_ARM_32,14 SMC_CONVENTION_ARM_64,15};16 17extern enum qcom_scm_convention qcom_scm_convention;18 19#define MAX_QCOM_SCM_ARGS 1020#define MAX_QCOM_SCM_RETS 321 22enum qcom_scm_arg_types {23 QCOM_SCM_VAL,24 QCOM_SCM_RO,25 QCOM_SCM_RW,26 QCOM_SCM_BUFVAL,27};28 29#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\30 (((a) & 0x3) << 4) | \31 (((b) & 0x3) << 6) | \32 (((c) & 0x3) << 8) | \33 (((d) & 0x3) << 10) | \34 (((e) & 0x3) << 12) | \35 (((f) & 0x3) << 14) | \36 (((g) & 0x3) << 16) | \37 (((h) & 0x3) << 18) | \38 (((i) & 0x3) << 20) | \39 (((j) & 0x3) << 22) | \40 ((num) & 0xf))41 42#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)43 44 45/**46 * struct qcom_scm_desc47 * @arginfo: Metadata describing the arguments in args[]48 * @args: The array of arguments for the secure syscall49 */50struct qcom_scm_desc {51 u32 svc;52 u32 cmd;53 u32 arginfo;54 u64 args[MAX_QCOM_SCM_ARGS];55 u32 owner;56};57 58/**59 * struct qcom_scm_res60 * @result: The values returned by the secure syscall61 */62struct qcom_scm_res {63 u64 result[MAX_QCOM_SCM_RETS];64};65 66int qcom_scm_wait_for_wq_completion(u32 wq_ctx);67int scm_get_wq_ctx(u32 *wq_ctx, u32 *flags, u32 *more_pending);68 69#define SCM_SMC_FNID(s, c) ((((s) & 0xFF) << 8) | ((c) & 0xFF))70int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,71 enum qcom_scm_convention qcom_convention,72 struct qcom_scm_res *res, bool atomic);73#define scm_smc_call(dev, desc, res, atomic) \74 __scm_smc_call((dev), (desc), qcom_scm_convention, (res), (atomic))75 76#define SCM_LEGACY_FNID(s, c) (((s) << 10) | ((c) & 0x3ff))77int scm_legacy_call_atomic(struct device *dev, const struct qcom_scm_desc *desc,78 struct qcom_scm_res *res);79int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc,80 struct qcom_scm_res *res);81 82struct qcom_tzmem_pool *qcom_scm_get_tzmem_pool(void);83 84#define QCOM_SCM_SVC_BOOT 0x0185#define QCOM_SCM_BOOT_SET_ADDR 0x0186#define QCOM_SCM_BOOT_TERMINATE_PC 0x0287#define QCOM_SCM_BOOT_SDI_CONFIG 0x0988#define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x1089#define QCOM_SCM_BOOT_SET_ADDR_MC 0x1190#define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a91#define QCOM_SCM_FLUSH_FLAG_MASK 0x392#define QCOM_SCM_BOOT_MAX_CPUS 493#define QCOM_SCM_BOOT_MC_FLAG_AARCH64 BIT(0)94#define QCOM_SCM_BOOT_MC_FLAG_COLDBOOT BIT(1)95#define QCOM_SCM_BOOT_MC_FLAG_WARMBOOT BIT(2)96 97#define QCOM_SCM_SVC_PIL 0x0298#define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x0199#define QCOM_SCM_PIL_PAS_MEM_SETUP 0x02100#define QCOM_SCM_PIL_PAS_AUTH_AND_RESET 0x05101#define QCOM_SCM_PIL_PAS_SHUTDOWN 0x06102#define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x07103#define QCOM_SCM_PIL_PAS_MSS_RESET 0x0a104 105#define QCOM_SCM_SVC_IO 0x05106#define QCOM_SCM_IO_READ 0x01107#define QCOM_SCM_IO_WRITE 0x02108 109#define QCOM_SCM_SVC_INFO 0x06110#define QCOM_SCM_INFO_IS_CALL_AVAIL 0x01111 112#define QCOM_SCM_SVC_MP 0x0c113#define QCOM_SCM_MP_RESTORE_SEC_CFG 0x02114#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE 0x03115#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT 0x04116#define QCOM_SCM_MP_IOMMU_SET_CP_POOL_SIZE 0x05117#define QCOM_SCM_MP_VIDEO_VAR 0x08118#define QCOM_SCM_MP_ASSIGN 0x16119#define QCOM_SCM_MP_SHM_BRIDGE_ENABLE 0x1c120#define QCOM_SCM_MP_SHM_BRIDGE_DELETE 0x1d121#define QCOM_SCM_MP_SHM_BRIDGE_CREATE 0x1e122 123#define QCOM_SCM_SVC_OCMEM 0x0f124#define QCOM_SCM_OCMEM_LOCK_CMD 0x01125#define QCOM_SCM_OCMEM_UNLOCK_CMD 0x02126 127#define QCOM_SCM_SVC_ES 0x10 /* Enterprise Security */128#define QCOM_SCM_ES_INVALIDATE_ICE_KEY 0x03129#define QCOM_SCM_ES_CONFIG_SET_ICE_KEY 0x04130 131#define QCOM_SCM_SVC_HDCP 0x11132#define QCOM_SCM_HDCP_INVOKE 0x01133 134#define QCOM_SCM_SVC_LMH 0x13135#define QCOM_SCM_LMH_LIMIT_PROFILE_CHANGE 0x01136#define QCOM_SCM_LMH_LIMIT_DCVSH 0x10137 138#define QCOM_SCM_SVC_SMMU_PROGRAM 0x15139#define QCOM_SCM_SMMU_PT_FORMAT 0x01140#define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x03141#define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02142 143#define QCOM_SCM_SVC_WAITQ 0x24144#define QCOM_SCM_WAITQ_RESUME 0x02145#define QCOM_SCM_WAITQ_GET_WQ_CTX 0x03146 147#define QCOM_SCM_SVC_GPU 0x28148#define QCOM_SCM_SVC_GPU_INIT_REGS 0x01149 150/* common error codes */151#define QCOM_SCM_V2_EBUSY -12152#define QCOM_SCM_ENOMEM -5153#define QCOM_SCM_EOPNOTSUPP -4154#define QCOM_SCM_EINVAL_ADDR -3155#define QCOM_SCM_EINVAL_ARG -2156#define QCOM_SCM_ERROR -1157#define QCOM_SCM_INTERRUPTED 1158#define QCOM_SCM_WAITQ_SLEEP 2159 160static inline int qcom_scm_remap_error(int err)161{162 switch (err) {163 case QCOM_SCM_ERROR:164 return -EIO;165 case QCOM_SCM_EINVAL_ADDR:166 case QCOM_SCM_EINVAL_ARG:167 return -EINVAL;168 case QCOM_SCM_EOPNOTSUPP:169 return -EOPNOTSUPP;170 case QCOM_SCM_ENOMEM:171 return -ENOMEM;172 case QCOM_SCM_V2_EBUSY:173 return -EBUSY;174 }175 return -EINVAL;176}177 178#endif179