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1/* SPDX-License-Identifier: BSD-3-Clause */2/*3 * Texas Instruments System Control Interface (TISCI) Protocol4 *5 * Communication protocol with TI SCI hardware6 * The system works in a message response protocol7 * See: https://software-dl.ti.com/tisci/esd/latest/index.html for details8 *9 * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/10 */11 12#ifndef __TI_SCI_H13#define __TI_SCI_H14 15/* Generic Messages */16#define TI_SCI_MSG_ENABLE_WDT 0x000017#define TI_SCI_MSG_WAKE_RESET 0x000118#define TI_SCI_MSG_VERSION 0x000219#define TI_SCI_MSG_WAKE_REASON 0x000320#define TI_SCI_MSG_GOODBYE 0x000421#define TI_SCI_MSG_SYS_RESET 0x000522 23/* Device requests */24#define TI_SCI_MSG_SET_DEVICE_STATE 0x020025#define TI_SCI_MSG_GET_DEVICE_STATE 0x020126#define TI_SCI_MSG_SET_DEVICE_RESETS 0x020227 28/* Clock requests */29#define TI_SCI_MSG_SET_CLOCK_STATE 0x010030#define TI_SCI_MSG_GET_CLOCK_STATE 0x010131#define TI_SCI_MSG_SET_CLOCK_PARENT 0x010232#define TI_SCI_MSG_GET_CLOCK_PARENT 0x010333#define TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 0x010434#define TI_SCI_MSG_SET_CLOCK_FREQ 0x010c35#define TI_SCI_MSG_QUERY_CLOCK_FREQ 0x010d36#define TI_SCI_MSG_GET_CLOCK_FREQ 0x010e37 38/* Resource Management Requests */39#define TI_SCI_MSG_GET_RESOURCE_RANGE 0x150040 41/* IRQ requests */42#define TI_SCI_MSG_SET_IRQ 0x100043#define TI_SCI_MSG_FREE_IRQ 0x100144 45/* NAVSS resource management */46/* Ringacc requests */47#define TI_SCI_MSG_RM_RING_ALLOCATE 0x110048#define TI_SCI_MSG_RM_RING_FREE 0x110149#define TI_SCI_MSG_RM_RING_RECONFIG 0x110250#define TI_SCI_MSG_RM_RING_RESET 0x110351#define TI_SCI_MSG_RM_RING_CFG 0x111052 53/* PSI-L requests */54#define TI_SCI_MSG_RM_PSIL_PAIR 0x128055#define TI_SCI_MSG_RM_PSIL_UNPAIR 0x128156 57#define TI_SCI_MSG_RM_UDMAP_TX_ALLOC 0x120058#define TI_SCI_MSG_RM_UDMAP_TX_FREE 0x120159#define TI_SCI_MSG_RM_UDMAP_RX_ALLOC 0x121060#define TI_SCI_MSG_RM_UDMAP_RX_FREE 0x121161#define TI_SCI_MSG_RM_UDMAP_FLOW_CFG 0x122062#define TI_SCI_MSG_RM_UDMAP_OPT_FLOW_CFG 0x122163 64#define TISCI_MSG_RM_UDMAP_TX_CH_CFG 0x120565#define TISCI_MSG_RM_UDMAP_TX_CH_GET_CFG 0x120666#define TISCI_MSG_RM_UDMAP_RX_CH_CFG 0x121567#define TISCI_MSG_RM_UDMAP_RX_CH_GET_CFG 0x121668#define TISCI_MSG_RM_UDMAP_FLOW_CFG 0x123069#define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG 0x123170#define TISCI_MSG_RM_UDMAP_FLOW_GET_CFG 0x123271#define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_GET_CFG 0x123372 73/* Processor Control requests */74#define TI_SCI_MSG_PROC_REQUEST 0xc00075#define TI_SCI_MSG_PROC_RELEASE 0xc00176#define TI_SCI_MSG_PROC_HANDOVER 0xc00577#define TI_SCI_MSG_SET_CONFIG 0xc10078#define TI_SCI_MSG_SET_CTRL 0xc10179#define TI_SCI_MSG_GET_STATUS 0xc40080 81/**82 * struct ti_sci_msg_hdr - Generic Message Header for All messages and responses83 * @type: Type of messages: One of TI_SCI_MSG* values84 * @host: Host of the message85 * @seq: Message identifier indicating a transfer sequence86 * @flags: Flag for the message87 */88struct ti_sci_msg_hdr {89 u16 type;90 u8 host;91 u8 seq;92#define TI_SCI_MSG_FLAG(val) (1 << (val))93#define TI_SCI_FLAG_REQ_GENERIC_NORESPONSE 0x094#define TI_SCI_FLAG_REQ_ACK_ON_RECEIVED TI_SCI_MSG_FLAG(0)95#define TI_SCI_FLAG_REQ_ACK_ON_PROCESSED TI_SCI_MSG_FLAG(1)96#define TI_SCI_FLAG_RESP_GENERIC_NACK 0x097#define TI_SCI_FLAG_RESP_GENERIC_ACK TI_SCI_MSG_FLAG(1)98 /* Additional Flags */99 u32 flags;100} __packed;101 102/**103 * struct ti_sci_msg_resp_version - Response for a message104 * @hdr: Generic header105 * @firmware_description: String describing the firmware106 * @firmware_revision: Firmware revision107 * @abi_major: Major version of the ABI that firmware supports108 * @abi_minor: Minor version of the ABI that firmware supports109 *110 * In general, ABI version changes follow the rule that minor version increments111 * are backward compatible. Major revision changes in ABI may not be112 * backward compatible.113 *114 * Response to a generic message with message type TI_SCI_MSG_VERSION115 */116struct ti_sci_msg_resp_version {117 struct ti_sci_msg_hdr hdr;118 char firmware_description[32];119 u16 firmware_revision;120 u8 abi_major;121 u8 abi_minor;122} __packed;123 124/**125 * struct ti_sci_msg_req_reboot - Reboot the SoC126 * @hdr: Generic Header127 *128 * Request type is TI_SCI_MSG_SYS_RESET, responded with a generic129 * ACK/NACK message.130 */131struct ti_sci_msg_req_reboot {132 struct ti_sci_msg_hdr hdr;133} __packed;134 135/**136 * struct ti_sci_msg_req_set_device_state - Set the desired state of the device137 * @hdr: Generic header138 * @id: Indicates which device to modify139 * @reserved: Reserved space in message, must be 0 for backward compatibility140 * @state: The desired state of the device.141 *142 * Certain flags can also be set to alter the device state:143 * + MSG_FLAG_DEVICE_WAKE_ENABLED - Configure the device to be a wake source.144 * The meaning of this flag will vary slightly from device to device and from145 * SoC to SoC but it generally allows the device to wake the SoC out of deep146 * suspend states.147 * + MSG_FLAG_DEVICE_RESET_ISO - Enable reset isolation for this device.148 * + MSG_FLAG_DEVICE_EXCLUSIVE - Claim this device exclusively. When passed149 * with STATE_RETENTION or STATE_ON, it will claim the device exclusively.150 * If another host already has this device set to STATE_RETENTION or STATE_ON,151 * the message will fail. Once successful, other hosts attempting to set152 * STATE_RETENTION or STATE_ON will fail.153 *154 * Request type is TI_SCI_MSG_SET_DEVICE_STATE, responded with a generic155 * ACK/NACK message.156 */157struct ti_sci_msg_req_set_device_state {158 /* Additional hdr->flags options */159#define MSG_FLAG_DEVICE_WAKE_ENABLED TI_SCI_MSG_FLAG(8)160#define MSG_FLAG_DEVICE_RESET_ISO TI_SCI_MSG_FLAG(9)161#define MSG_FLAG_DEVICE_EXCLUSIVE TI_SCI_MSG_FLAG(10)162 struct ti_sci_msg_hdr hdr;163 u32 id;164 u32 reserved;165 166#define MSG_DEVICE_SW_STATE_AUTO_OFF 0167#define MSG_DEVICE_SW_STATE_RETENTION 1168#define MSG_DEVICE_SW_STATE_ON 2169 u8 state;170} __packed;171 172/**173 * struct ti_sci_msg_req_get_device_state - Request to get device.174 * @hdr: Generic header175 * @id: Device Identifier176 *177 * Request type is TI_SCI_MSG_GET_DEVICE_STATE, responded device state178 * information179 */180struct ti_sci_msg_req_get_device_state {181 struct ti_sci_msg_hdr hdr;182 u32 id;183} __packed;184 185/**186 * struct ti_sci_msg_resp_get_device_state - Response to get device request.187 * @hdr: Generic header188 * @context_loss_count: Indicates how many times the device has lost context. A189 * driver can use this monotonic counter to determine if the device has190 * lost context since the last time this message was exchanged.191 * @resets: Programmed state of the reset lines.192 * @programmed_state: The state as programmed by set_device.193 * - Uses the MSG_DEVICE_SW_* macros194 * @current_state: The actual state of the hardware.195 *196 * Response to request TI_SCI_MSG_GET_DEVICE_STATE.197 */198struct ti_sci_msg_resp_get_device_state {199 struct ti_sci_msg_hdr hdr;200 u32 context_loss_count;201 u32 resets;202 u8 programmed_state;203#define MSG_DEVICE_HW_STATE_OFF 0204#define MSG_DEVICE_HW_STATE_ON 1205#define MSG_DEVICE_HW_STATE_TRANS 2206 u8 current_state;207} __packed;208 209/**210 * struct ti_sci_msg_req_set_device_resets - Set the desired resets211 * configuration of the device212 * @hdr: Generic header213 * @id: Indicates which device to modify214 * @resets: A bit field of resets for the device. The meaning, behavior,215 * and usage of the reset flags are device specific. 0 for a bit216 * indicates releasing the reset represented by that bit while 1217 * indicates keeping it held.218 *219 * Request type is TI_SCI_MSG_SET_DEVICE_RESETS, responded with a generic220 * ACK/NACK message.221 */222struct ti_sci_msg_req_set_device_resets {223 struct ti_sci_msg_hdr hdr;224 u32 id;225 u32 resets;226} __packed;227 228/**229 * struct ti_sci_msg_req_set_clock_state - Request to setup a Clock state230 * @hdr: Generic Header, Certain flags can be set specific to the clocks:231 * MSG_FLAG_CLOCK_ALLOW_SSC: Allow this clock to be modified232 * via spread spectrum clocking.233 * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE: Allow this clock's234 * frequency to be changed while it is running so long as it235 * is within the min/max limits.236 * MSG_FLAG_CLOCK_INPUT_TERM: Enable input termination, this237 * is only applicable to clock inputs on the SoC pseudo-device.238 * @dev_id: Device identifier this request is for239 * @clk_id: Clock identifier for the device for this request.240 * Each device has it's own set of clock inputs. This indexes241 * which clock input to modify. Set to 255 if clock ID is242 * greater than or equal to 255.243 * @request_state: Request the state for the clock to be set to.244 * MSG_CLOCK_SW_STATE_UNREQ: The IP does not require this clock,245 * it can be disabled, regardless of the state of the device246 * MSG_CLOCK_SW_STATE_AUTO: Allow the System Controller to247 * automatically manage the state of this clock. If the device248 * is enabled, then the clock is enabled. If the device is set249 * to off or retention, then the clock is internally set as not250 * being required by the device.(default)251 * MSG_CLOCK_SW_STATE_REQ: Configure the clock to be enabled,252 * regardless of the state of the device.253 * @clk_id_32: Clock identifier for the device for this request.254 * Only to be used if the clock ID is greater than or equal to255 * 255.256 *257 * Normally, all required clocks are managed by TISCI entity, this is used258 * only for specific control *IF* required. Auto managed state is259 * MSG_CLOCK_SW_STATE_AUTO, in other states, TISCI entity assume remote260 * will explicitly control.261 *262 * Request type is TI_SCI_MSG_SET_CLOCK_STATE, response is a generic263 * ACK or NACK message.264 */265struct ti_sci_msg_req_set_clock_state {266 /* Additional hdr->flags options */267#define MSG_FLAG_CLOCK_ALLOW_SSC TI_SCI_MSG_FLAG(8)268#define MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE TI_SCI_MSG_FLAG(9)269#define MSG_FLAG_CLOCK_INPUT_TERM TI_SCI_MSG_FLAG(10)270 struct ti_sci_msg_hdr hdr;271 u32 dev_id;272 u8 clk_id;273#define MSG_CLOCK_SW_STATE_UNREQ 0274#define MSG_CLOCK_SW_STATE_AUTO 1275#define MSG_CLOCK_SW_STATE_REQ 2276 u8 request_state;277 u32 clk_id_32;278} __packed;279 280/**281 * struct ti_sci_msg_req_get_clock_state - Request for clock state282 * @hdr: Generic Header283 * @dev_id: Device identifier this request is for284 * @clk_id: Clock identifier for the device for this request.285 * Each device has it's own set of clock inputs. This indexes286 * which clock input to get state of. Set to 255 if the clock287 * ID is greater than or equal to 255.288 * @clk_id_32: Clock identifier for the device for the request.289 * Only to be used if the clock ID is greater than or equal to290 * 255.291 *292 * Request type is TI_SCI_MSG_GET_CLOCK_STATE, response is state293 * of the clock294 */295struct ti_sci_msg_req_get_clock_state {296 struct ti_sci_msg_hdr hdr;297 u32 dev_id;298 u8 clk_id;299 u32 clk_id_32;300} __packed;301 302/**303 * struct ti_sci_msg_resp_get_clock_state - Response to get clock state304 * @hdr: Generic Header305 * @programmed_state: Any programmed state of the clock. This is one of306 * MSG_CLOCK_SW_STATE* values.307 * @current_state: Current state of the clock. This is one of:308 * MSG_CLOCK_HW_STATE_NOT_READY: Clock is not ready309 * MSG_CLOCK_HW_STATE_READY: Clock is ready310 *311 * Response to TI_SCI_MSG_GET_CLOCK_STATE.312 */313struct ti_sci_msg_resp_get_clock_state {314 struct ti_sci_msg_hdr hdr;315 u8 programmed_state;316#define MSG_CLOCK_HW_STATE_NOT_READY 0317#define MSG_CLOCK_HW_STATE_READY 1318 u8 current_state;319} __packed;320 321/**322 * struct ti_sci_msg_req_set_clock_parent - Set the clock parent323 * @hdr: Generic Header324 * @dev_id: Device identifier this request is for325 * @clk_id: Clock identifier for the device for this request.326 * Each device has it's own set of clock inputs. This indexes327 * which clock input to modify. Set to 255 if clock ID is328 * greater than or equal to 255.329 * @parent_id: The new clock parent is selectable by an index via this330 * parameter. Set to 255 if clock ID is greater than or331 * equal to 255.332 * @clk_id_32: Clock identifier if @clk_id field is 255.333 * @parent_id_32: Parent identifier if @parent_id is 255.334 *335 * Request type is TI_SCI_MSG_SET_CLOCK_PARENT, response is generic336 * ACK / NACK message.337 */338struct ti_sci_msg_req_set_clock_parent {339 struct ti_sci_msg_hdr hdr;340 u32 dev_id;341 u8 clk_id;342 u8 parent_id;343 u32 clk_id_32;344 u32 parent_id_32;345} __packed;346 347/**348 * struct ti_sci_msg_req_get_clock_parent - Get the clock parent349 * @hdr: Generic Header350 * @dev_id: Device identifier this request is for351 * @clk_id: Clock identifier for the device for this request.352 * Each device has it's own set of clock inputs. This indexes353 * which clock input to get the parent for. If this field354 * contains 255, the actual clock identifier is stored in355 * @clk_id_32.356 * @clk_id_32: Clock identifier if the @clk_id field contains 255.357 *358 * Request type is TI_SCI_MSG_GET_CLOCK_PARENT, response is parent information359 */360struct ti_sci_msg_req_get_clock_parent {361 struct ti_sci_msg_hdr hdr;362 u32 dev_id;363 u8 clk_id;364 u32 clk_id_32;365} __packed;366 367/**368 * struct ti_sci_msg_resp_get_clock_parent - Response with clock parent369 * @hdr: Generic Header370 * @parent_id: The current clock parent. If set to 255, the current parent371 * ID can be found from the @parent_id_32 field.372 * @parent_id_32: Current clock parent if @parent_id field is set to373 * 255.374 *375 * Response to TI_SCI_MSG_GET_CLOCK_PARENT.376 */377struct ti_sci_msg_resp_get_clock_parent {378 struct ti_sci_msg_hdr hdr;379 u8 parent_id;380 u32 parent_id_32;381} __packed;382 383/**384 * struct ti_sci_msg_req_get_clock_num_parents - Request to get clock parents385 * @hdr: Generic header386 * @dev_id: Device identifier this request is for387 * @clk_id: Clock identifier for the device for this request. Set to388 * 255 if clock ID is greater than or equal to 255.389 * @clk_id_32: Clock identifier if the @clk_id field contains 255.390 *391 * This request provides information about how many clock parent options392 * are available for a given clock to a device. This is typically used393 * for input clocks.394 *395 * Request type is TI_SCI_MSG_GET_NUM_CLOCK_PARENTS, response is appropriate396 * message, or NACK in case of inability to satisfy request.397 */398struct ti_sci_msg_req_get_clock_num_parents {399 struct ti_sci_msg_hdr hdr;400 u32 dev_id;401 u8 clk_id;402 u32 clk_id_32;403} __packed;404 405/**406 * struct ti_sci_msg_resp_get_clock_num_parents - Response for get clk parents407 * @hdr: Generic header408 * @num_parents: Number of clock parents. If set to 255, the actual409 * number of parents is stored into @num_parents_32410 * field instead.411 * @num_parents_32: Number of clock parents if @num_parents field is412 * set to 255.413 *414 * Response to TI_SCI_MSG_GET_NUM_CLOCK_PARENTS415 */416struct ti_sci_msg_resp_get_clock_num_parents {417 struct ti_sci_msg_hdr hdr;418 u8 num_parents;419 u32 num_parents_32;420} __packed;421 422/**423 * struct ti_sci_msg_req_query_clock_freq - Request to query a frequency424 * @hdr: Generic Header425 * @dev_id: Device identifier this request is for426 * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum427 * allowable programmed frequency and does not account for clock428 * tolerances and jitter.429 * @target_freq_hz: The target clock frequency. A frequency will be found430 * as close to this target frequency as possible.431 * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum432 * allowable programmed frequency and does not account for clock433 * tolerances and jitter.434 * @clk_id: Clock identifier for the device for this request. Set to435 * 255 if clock identifier is greater than or equal to 255.436 * @clk_id_32: Clock identifier if @clk_id is set to 255.437 *438 * NOTE: Normally clock frequency management is automatically done by TISCI439 * entity. In case of specific requests, TISCI evaluates capability to achieve440 * requested frequency within provided range and responds with441 * result message.442 *443 * Request type is TI_SCI_MSG_QUERY_CLOCK_FREQ, response is appropriate message,444 * or NACK in case of inability to satisfy request.445 */446struct ti_sci_msg_req_query_clock_freq {447 struct ti_sci_msg_hdr hdr;448 u32 dev_id;449 u64 min_freq_hz;450 u64 target_freq_hz;451 u64 max_freq_hz;452 u8 clk_id;453 u32 clk_id_32;454} __packed;455 456/**457 * struct ti_sci_msg_resp_query_clock_freq - Response to a clock frequency query458 * @hdr: Generic Header459 * @freq_hz: Frequency that is the best match in Hz.460 *461 * Response to request type TI_SCI_MSG_QUERY_CLOCK_FREQ. NOTE: if the request462 * cannot be satisfied, the message will be of type NACK.463 */464struct ti_sci_msg_resp_query_clock_freq {465 struct ti_sci_msg_hdr hdr;466 u64 freq_hz;467} __packed;468 469/**470 * struct ti_sci_msg_req_set_clock_freq - Request to setup a clock frequency471 * @hdr: Generic Header472 * @dev_id: Device identifier this request is for473 * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum474 * allowable programmed frequency and does not account for clock475 * tolerances and jitter.476 * @target_freq_hz: The target clock frequency. The clock will be programmed477 * at a rate as close to this target frequency as possible.478 * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum479 * allowable programmed frequency and does not account for clock480 * tolerances and jitter.481 * @clk_id: Clock identifier for the device for this request. Set to482 * 255 if clock ID is greater than or equal to 255.483 * @clk_id_32: Clock identifier if @clk_id field is set to 255.484 *485 * NOTE: Normally clock frequency management is automatically done by TISCI486 * entity. In case of specific requests, TISCI evaluates capability to achieve487 * requested range and responds with success/failure message.488 *489 * This sets the desired frequency for a clock within an allowable490 * range. This message will fail on an enabled clock unless491 * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE is set for the clock. Additionally,492 * if other clocks have their frequency modified due to this message,493 * they also must have the MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE or be disabled.494 *495 * Calling set frequency on a clock input to the SoC pseudo-device will496 * inform the PMMC of that clock's frequency. Setting a frequency of497 * zero will indicate the clock is disabled.498 *499 * Calling set frequency on clock outputs from the SoC pseudo-device will500 * function similarly to setting the clock frequency on a device.501 *502 * Request type is TI_SCI_MSG_SET_CLOCK_FREQ, response is a generic ACK/NACK503 * message.504 */505struct ti_sci_msg_req_set_clock_freq {506 struct ti_sci_msg_hdr hdr;507 u32 dev_id;508 u64 min_freq_hz;509 u64 target_freq_hz;510 u64 max_freq_hz;511 u8 clk_id;512 u32 clk_id_32;513} __packed;514 515/**516 * struct ti_sci_msg_req_get_clock_freq - Request to get the clock frequency517 * @hdr: Generic Header518 * @dev_id: Device identifier this request is for519 * @clk_id: Clock identifier for the device for this request. Set to520 * 255 if clock ID is greater than or equal to 255.521 * @clk_id_32: Clock identifier if @clk_id field is set to 255.522 *523 * NOTE: Normally clock frequency management is automatically done by TISCI524 * entity. In some cases, clock frequencies are configured by host.525 *526 * Request type is TI_SCI_MSG_GET_CLOCK_FREQ, responded with clock frequency527 * that the clock is currently at.528 */529struct ti_sci_msg_req_get_clock_freq {530 struct ti_sci_msg_hdr hdr;531 u32 dev_id;532 u8 clk_id;533 u32 clk_id_32;534} __packed;535 536/**537 * struct ti_sci_msg_resp_get_clock_freq - Response of clock frequency request538 * @hdr: Generic Header539 * @freq_hz: Frequency that the clock is currently on, in Hz.540 *541 * Response to request type TI_SCI_MSG_GET_CLOCK_FREQ.542 */543struct ti_sci_msg_resp_get_clock_freq {544 struct ti_sci_msg_hdr hdr;545 u64 freq_hz;546} __packed;547 548#define TI_SCI_IRQ_SECONDARY_HOST_INVALID 0xff549 550/**551 * struct ti_sci_msg_req_get_resource_range - Request to get a host's assigned552 * range of resources.553 * @hdr: Generic Header554 * @type: Unique resource assignment type555 * @subtype: Resource assignment subtype within the resource type.556 * @secondary_host: Host processing entity to which the resources are557 * allocated. This is required only when the destination558 * host id id different from ti sci interface host id,559 * else TI_SCI_IRQ_SECONDARY_HOST_INVALID can be passed.560 *561 * Request type is TI_SCI_MSG_GET_RESOURCE_RANGE. Responded with requested562 * resource range which is of type TI_SCI_MSG_GET_RESOURCE_RANGE.563 */564struct ti_sci_msg_req_get_resource_range {565 struct ti_sci_msg_hdr hdr;566#define MSG_RM_RESOURCE_TYPE_MASK GENMASK(9, 0)567#define MSG_RM_RESOURCE_SUBTYPE_MASK GENMASK(5, 0)568 u16 type;569 u8 subtype;570 u8 secondary_host;571} __packed;572 573/**574 * struct ti_sci_msg_resp_get_resource_range - Response to resource get range.575 * @hdr: Generic Header576 * @range_start: Start index of the first resource range.577 * @range_num: Number of resources in the first range.578 * @range_start_sec: Start index of the second resource range.579 * @range_num_sec: Number of resources in the second range.580 *581 * Response to request TI_SCI_MSG_GET_RESOURCE_RANGE.582 */583struct ti_sci_msg_resp_get_resource_range {584 struct ti_sci_msg_hdr hdr;585 u16 range_start;586 u16 range_num;587 u16 range_start_sec;588 u16 range_num_sec;589} __packed;590 591/**592 * struct ti_sci_msg_req_manage_irq - Request to configure/release the route593 * between the dev and the host.594 * @hdr: Generic Header595 * @valid_params: Bit fields defining the validity of interrupt source596 * parameters. If a bit is not set, then corresponding597 * field is not valid and will not be used for route set.598 * Bit field definitions:599 * 0 - Valid bit for @dst_id600 * 1 - Valid bit for @dst_host_irq601 * 2 - Valid bit for @ia_id602 * 3 - Valid bit for @vint603 * 4 - Valid bit for @global_event604 * 5 - Valid bit for @vint_status_bit_index605 * 31 - Valid bit for @secondary_host606 * @src_id: IRQ source peripheral ID.607 * @src_index: IRQ source index within the peripheral608 * @dst_id: IRQ Destination ID. Based on the architecture it can be609 * IRQ controller or host processor ID.610 * @dst_host_irq: IRQ number of the destination host IRQ controller611 * @ia_id: Device ID of the interrupt aggregator in which the612 * vint resides.613 * @vint: Virtual interrupt number if the interrupt route614 * is through an interrupt aggregator.615 * @global_event: Global event that is to be mapped to interrupt616 * aggregator virtual interrupt status bit.617 * @vint_status_bit: Virtual interrupt status bit if the interrupt route618 * utilizes an interrupt aggregator status bit.619 * @secondary_host: Host ID of the IRQ destination computing entity. This is620 * required only when destination host id is different621 * from ti sci interface host id.622 *623 * Request type is TI_SCI_MSG_SET/RELEASE_IRQ.624 * Response is generic ACK / NACK message.625 */626struct ti_sci_msg_req_manage_irq {627 struct ti_sci_msg_hdr hdr;628#define MSG_FLAG_DST_ID_VALID TI_SCI_MSG_FLAG(0)629#define MSG_FLAG_DST_HOST_IRQ_VALID TI_SCI_MSG_FLAG(1)630#define MSG_FLAG_IA_ID_VALID TI_SCI_MSG_FLAG(2)631#define MSG_FLAG_VINT_VALID TI_SCI_MSG_FLAG(3)632#define MSG_FLAG_GLB_EVNT_VALID TI_SCI_MSG_FLAG(4)633#define MSG_FLAG_VINT_STS_BIT_VALID TI_SCI_MSG_FLAG(5)634#define MSG_FLAG_SHOST_VALID TI_SCI_MSG_FLAG(31)635 u32 valid_params;636 u16 src_id;637 u16 src_index;638 u16 dst_id;639 u16 dst_host_irq;640 u16 ia_id;641 u16 vint;642 u16 global_event;643 u8 vint_status_bit;644 u8 secondary_host;645} __packed;646 647/**648 * struct ti_sci_msg_rm_ring_cfg_req - Configure a Navigator Subsystem ring649 *650 * Configures the non-real-time registers of a Navigator Subsystem ring.651 * @hdr: Generic Header652 * @valid_params: Bitfield defining validity of ring configuration parameters.653 * The ring configuration fields are not valid, and will not be used for654 * ring configuration, if their corresponding valid bit is zero.655 * Valid bit usage:656 * 0 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_lo657 * 1 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_hi658 * 2 - Valid bit for @tisci_msg_rm_ring_cfg_req count659 * 3 - Valid bit for @tisci_msg_rm_ring_cfg_req mode660 * 4 - Valid bit for @tisci_msg_rm_ring_cfg_req size661 * 5 - Valid bit for @tisci_msg_rm_ring_cfg_req order_id662 * 6 - Valid bit for @tisci_msg_rm_ring_cfg_req virtid663 * 7 - Valid bit for @tisci_msg_rm_ring_cfg_req ASEL664 * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated665 * @index: ring index to be configured.666 * @addr_lo: 32 LSBs of ring base address to be programmed into the ring's667 * RING_BA_LO register668 * @addr_hi: 16 MSBs of ring base address to be programmed into the ring's669 * RING_BA_HI register.670 * @count: Number of ring elements. Must be even if mode is CREDENTIALS or QM671 * modes.672 * @mode: Specifies the mode the ring is to be configured.673 * @size: Specifies encoded ring element size. To calculate the encoded size use674 * the formula (log2(size_bytes) - 2), where size_bytes cannot be675 * greater than 256.676 * @order_id: Specifies the ring's bus order ID.677 * @virtid: Ring virt ID value678 * @asel: Ring ASEL (address select) value to be set into the ASEL field of the679 * ring's RING_BA_HI register.680 */681struct ti_sci_msg_rm_ring_cfg_req {682 struct ti_sci_msg_hdr hdr;683 u32 valid_params;684 u16 nav_id;685 u16 index;686 u32 addr_lo;687 u32 addr_hi;688 u32 count;689 u8 mode;690 u8 size;691 u8 order_id;692 u16 virtid;693 u8 asel;694} __packed;695 696/**697 * struct ti_sci_msg_psil_pair - Pairs a PSI-L source thread to a destination698 * thread699 * @hdr: Generic Header700 * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is701 * used to pair the source and destination threads.702 * @src_thread: PSI-L source thread ID within the PSI-L System thread map.703 *704 * UDMAP transmit channels mapped to source threads will have their705 * TCHAN_THRD_ID register programmed with the destination thread if the pairing706 * is successful.707 708 * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map.709 * PSI-L destination threads start at index 0x8000. The request is NACK'd if710 * the destination thread is not greater than or equal to 0x8000.711 *712 * UDMAP receive channels mapped to destination threads will have their713 * RCHAN_THRD_ID register programmed with the source thread if the pairing714 * is successful.715 *716 * Request type is TI_SCI_MSG_RM_PSIL_PAIR, response is a generic ACK or NACK717 * message.718 */719struct ti_sci_msg_psil_pair {720 struct ti_sci_msg_hdr hdr;721 u32 nav_id;722 u32 src_thread;723 u32 dst_thread;724} __packed;725 726/**727 * struct ti_sci_msg_psil_unpair - Unpairs a PSI-L source thread from a728 * destination thread729 * @hdr: Generic Header730 * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is731 * used to unpair the source and destination threads.732 * @src_thread: PSI-L source thread ID within the PSI-L System thread map.733 *734 * UDMAP transmit channels mapped to source threads will have their735 * TCHAN_THRD_ID register cleared if the unpairing is successful.736 *737 * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map.738 * PSI-L destination threads start at index 0x8000. The request is NACK'd if739 * the destination thread is not greater than or equal to 0x8000.740 *741 * UDMAP receive channels mapped to destination threads will have their742 * RCHAN_THRD_ID register cleared if the unpairing is successful.743 *744 * Request type is TI_SCI_MSG_RM_PSIL_UNPAIR, response is a generic ACK or NACK745 * message.746 */747struct ti_sci_msg_psil_unpair {748 struct ti_sci_msg_hdr hdr;749 u32 nav_id;750 u32 src_thread;751 u32 dst_thread;752} __packed;753 754/**755 * struct ti_sci_msg_udmap_rx_flow_cfg - UDMAP receive flow configuration756 * message757 * @hdr: Generic Header758 * @nav_id: SoC Navigator Subsystem device ID from which the receive flow is759 * allocated760 * @flow_index: UDMAP receive flow index for non-optional configuration.761 * @rx_ch_index: Specifies the index of the receive channel using the flow_index762 * @rx_einfo_present: UDMAP receive flow extended packet info present.763 * @rx_psinfo_present: UDMAP receive flow PS words present.764 * @rx_error_handling: UDMAP receive flow error handling configuration. Valid765 * values are TI_SCI_RM_UDMAP_RX_FLOW_ERR_DROP/RETRY.766 * @rx_desc_type: UDMAP receive flow descriptor type. It can be one of767 * TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST/MONO.768 * @rx_sop_offset: UDMAP receive flow start of packet offset.769 * @rx_dest_qnum: UDMAP receive flow destination queue number.770 * @rx_ps_location: UDMAP receive flow PS words location.771 * 0 - end of packet descriptor772 * 1 - Beginning of the data buffer773 * @rx_src_tag_hi: UDMAP receive flow source tag high byte constant774 * @rx_src_tag_lo: UDMAP receive flow source tag low byte constant775 * @rx_dest_tag_hi: UDMAP receive flow destination tag high byte constant776 * @rx_dest_tag_lo: UDMAP receive flow destination tag low byte constant777 * @rx_src_tag_hi_sel: UDMAP receive flow source tag high byte selector778 * @rx_src_tag_lo_sel: UDMAP receive flow source tag low byte selector779 * @rx_dest_tag_hi_sel: UDMAP receive flow destination tag high byte selector780 * @rx_dest_tag_lo_sel: UDMAP receive flow destination tag low byte selector781 * @rx_size_thresh_en: UDMAP receive flow packet size based free buffer queue782 * enable. If enabled, the ti_sci_rm_udmap_rx_flow_opt_cfg also need to be783 * configured and sent.784 * @rx_fdq0_sz0_qnum: UDMAP receive flow free descriptor queue 0.785 * @rx_fdq1_qnum: UDMAP receive flow free descriptor queue 1.786 * @rx_fdq2_qnum: UDMAP receive flow free descriptor queue 2.787 * @rx_fdq3_qnum: UDMAP receive flow free descriptor queue 3.788 *789 * For detailed information on the settings, see the UDMAP section of the TRM.790 */791struct ti_sci_msg_udmap_rx_flow_cfg {792 struct ti_sci_msg_hdr hdr;793 u32 nav_id;794 u32 flow_index;795 u32 rx_ch_index;796 u8 rx_einfo_present;797 u8 rx_psinfo_present;798 u8 rx_error_handling;799 u8 rx_desc_type;800 u16 rx_sop_offset;801 u16 rx_dest_qnum;802 u8 rx_ps_location;803 u8 rx_src_tag_hi;804 u8 rx_src_tag_lo;805 u8 rx_dest_tag_hi;806 u8 rx_dest_tag_lo;807 u8 rx_src_tag_hi_sel;808 u8 rx_src_tag_lo_sel;809 u8 rx_dest_tag_hi_sel;810 u8 rx_dest_tag_lo_sel;811 u8 rx_size_thresh_en;812 u16 rx_fdq0_sz0_qnum;813 u16 rx_fdq1_qnum;814 u16 rx_fdq2_qnum;815 u16 rx_fdq3_qnum;816} __packed;817 818/**819 * struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg - parameters for UDMAP receive820 * flow optional configuration821 * @hdr: Generic Header822 * @nav_id: SoC Navigator Subsystem device ID from which the receive flow is823 * allocated824 * @flow_index: UDMAP receive flow index for optional configuration.825 * @rx_ch_index: Specifies the index of the receive channel using the flow_index826 * @rx_size_thresh0: UDMAP receive flow packet size threshold 0.827 * @rx_size_thresh1: UDMAP receive flow packet size threshold 1.828 * @rx_size_thresh2: UDMAP receive flow packet size threshold 2.829 * @rx_fdq0_sz1_qnum: UDMAP receive flow free descriptor queue for size830 * threshold 1.831 * @rx_fdq0_sz2_qnum: UDMAP receive flow free descriptor queue for size832 * threshold 2.833 * @rx_fdq0_sz3_qnum: UDMAP receive flow free descriptor queue for size834 * threshold 3.835 *836 * For detailed information on the settings, see the UDMAP section of the TRM.837 */838struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg {839 struct ti_sci_msg_hdr hdr;840 u32 nav_id;841 u32 flow_index;842 u32 rx_ch_index;843 u16 rx_size_thresh0;844 u16 rx_size_thresh1;845 u16 rx_size_thresh2;846 u16 rx_fdq0_sz1_qnum;847 u16 rx_fdq0_sz2_qnum;848 u16 rx_fdq0_sz3_qnum;849} __packed;850 851/**852 * Configures a Navigator Subsystem UDMAP transmit channel853 *854 * Configures the non-real-time registers of a Navigator Subsystem UDMAP855 * transmit channel. The channel index must be assigned to the host defined856 * in the TISCI header via the RM board configuration resource assignment857 * range list.858 *859 * @hdr: Generic Header860 *861 * @valid_params: Bitfield defining validity of tx channel configuration862 * parameters. The tx channel configuration fields are not valid, and will not863 * be used for ch configuration, if their corresponding valid bit is zero.864 * Valid bit usage:865 * 0 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_pause_on_err866 * 1 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_atype867 * 2 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_chan_type868 * 3 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_fetch_size869 * 4 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::txcq_qnum870 * 5 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_priority871 * 6 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_qos872 * 7 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_orderid873 * 8 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_sched_priority874 * 9 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_einfo875 * 10 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_pswords876 * 11 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_supr_tdpkt877 * 12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count878 * 13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth879 * 14 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_burst_size880 * 15 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_tdtype881 * 16 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::extended_ch_type882 *883 * @nav_id: SoC device ID of Navigator Subsystem where tx channel is located884 *885 * @index: UDMAP transmit channel index.886 *887 * @tx_pause_on_err: UDMAP transmit channel pause on error configuration to888 * be programmed into the tx_pause_on_err field of the channel's TCHAN_TCFG889 * register.890 *891 * @tx_filt_einfo: UDMAP transmit channel extended packet information passing892 * configuration to be programmed into the tx_filt_einfo field of the893 * channel's TCHAN_TCFG register.894 *895 * @tx_filt_pswords: UDMAP transmit channel protocol specific word passing896 * configuration to be programmed into the tx_filt_pswords field of the897 * channel's TCHAN_TCFG register.898 *899 * @tx_atype: UDMAP transmit channel non Ring Accelerator access pointer900 * interpretation configuration to be programmed into the tx_atype field of901 * the channel's TCHAN_TCFG register.902 *903 * @tx_chan_type: UDMAP transmit channel functional channel type and work904 * passing mechanism configuration to be programmed into the tx_chan_type905 * field of the channel's TCHAN_TCFG register.906 *907 * @tx_supr_tdpkt: UDMAP transmit channel teardown packet generation suppression908 * configuration to be programmed into the tx_supr_tdpkt field of the channel's909 * TCHAN_TCFG register.910 *911 * @tx_fetch_size: UDMAP transmit channel number of 32-bit descriptor words to912 * fetch configuration to be programmed into the tx_fetch_size field of the913 * channel's TCHAN_TCFG register. The user must make sure to set the maximum914 * word count that can pass through the channel for any allowed descriptor type.915 *916 * @tx_credit_count: UDMAP transmit channel transfer request credit count917 * configuration to be programmed into the count field of the TCHAN_TCREDIT918 * register. Specifies how many credits for complete TRs are available.919 *920 * @txcq_qnum: UDMAP transmit channel completion queue configuration to be921 * programmed into the txcq_qnum field of the TCHAN_TCQ register. The specified922 * completion queue must be assigned to the host, or a subordinate of the host,923 * requesting configuration of the transmit channel.924 *925 * @tx_priority: UDMAP transmit channel transmit priority value to be programmed926 * into the priority field of the channel's TCHAN_TPRI_CTRL register.927 *928 * @tx_qos: UDMAP transmit channel transmit qos value to be programmed into the929 * qos field of the channel's TCHAN_TPRI_CTRL register.930 *931 * @tx_orderid: UDMAP transmit channel bus order id value to be programmed into932 * the orderid field of the channel's TCHAN_TPRI_CTRL register.933 *934 * @fdepth: UDMAP transmit channel FIFO depth configuration to be programmed935 * into the fdepth field of the TCHAN_TFIFO_DEPTH register. Sets the number of936 * Tx FIFO bytes which are allowed to be stored for the channel. Check the UDMAP937 * section of the TRM for restrictions regarding this parameter.938 *939 * @tx_sched_priority: UDMAP transmit channel tx scheduling priority940 * configuration to be programmed into the priority field of the channel's941 * TCHAN_TST_SCHED register.942 *943 * @tx_burst_size: UDMAP transmit channel burst size configuration to be944 * programmed into the tx_burst_size field of the TCHAN_TCFG register.945 *946 * @tx_tdtype: UDMAP transmit channel teardown type configuration to be947 * programmed into the tdtype field of the TCHAN_TCFG register:948 * 0 - Return immediately949 * 1 - Wait for completion message from remote peer950 *951 * @extended_ch_type: Valid for BCDMA.952 * 0 - the channel is split tx channel (tchan)953 * 1 - the channel is block copy channel (bchan)954 */955struct ti_sci_msg_rm_udmap_tx_ch_cfg_req {956 struct ti_sci_msg_hdr hdr;957 u32 valid_params;958 u16 nav_id;959 u16 index;960 u8 tx_pause_on_err;961 u8 tx_filt_einfo;962 u8 tx_filt_pswords;963 u8 tx_atype;964 u8 tx_chan_type;965 u8 tx_supr_tdpkt;966 u16 tx_fetch_size;967 u8 tx_credit_count;968 u16 txcq_qnum;969 u8 tx_priority;970 u8 tx_qos;971 u8 tx_orderid;972 u16 fdepth;973 u8 tx_sched_priority;974 u8 tx_burst_size;975 u8 tx_tdtype;976 u8 extended_ch_type;977} __packed;978 979/**980 * Configures a Navigator Subsystem UDMAP receive channel981 *982 * Configures the non-real-time registers of a Navigator Subsystem UDMAP983 * receive channel. The channel index must be assigned to the host defined984 * in the TISCI header via the RM board configuration resource assignment985 * range list.986 *987 * @hdr: Generic Header988 *989 * @valid_params: Bitfield defining validity of rx channel configuration990 * parameters.991 * The rx channel configuration fields are not valid, and will not be used for992 * ch configuration, if their corresponding valid bit is zero.993 * Valid bit usage:994 * 0 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_pause_on_err995 * 1 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_atype996 * 2 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type997 * 3 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_fetch_size998 * 4 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rxcq_qnum999 * 5 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_priority1000 * 6 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_qos1001 * 7 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_orderid1002 * 8 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_sched_priority1003 * 9 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_start1004 * 10 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_cnt1005 * 11 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_short1006 * 12 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_long1007 * 14 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_burst_size1008 *1009 * @nav_id: SoC device ID of Navigator Subsystem where rx channel is located1010 *1011 * @index: UDMAP receive channel index.1012 *1013 * @rx_fetch_size: UDMAP receive channel number of 32-bit descriptor words to1014 * fetch configuration to be programmed into the rx_fetch_size field of the1015 * channel's RCHAN_RCFG register.1016 *1017 * @rxcq_qnum: UDMAP receive channel completion queue configuration to be1018 * programmed into the rxcq_qnum field of the RCHAN_RCQ register.1019 * The specified completion queue must be assigned to the host, or a subordinate1020 * of the host, requesting configuration of the receive channel.1021 *1022 * @rx_priority: UDMAP receive channel receive priority value to be programmed1023 * into the priority field of the channel's RCHAN_RPRI_CTRL register.1024 *1025 * @rx_qos: UDMAP receive channel receive qos value to be programmed into the1026 * qos field of the channel's RCHAN_RPRI_CTRL register.1027 *1028 * @rx_orderid: UDMAP receive channel bus order id value to be programmed into1029 * the orderid field of the channel's RCHAN_RPRI_CTRL register.1030 *1031 * @rx_sched_priority: UDMAP receive channel rx scheduling priority1032 * configuration to be programmed into the priority field of the channel's1033 * RCHAN_RST_SCHED register.1034 *1035 * @flowid_start: UDMAP receive channel additional flows starting index1036 * configuration to program into the flow_start field of the RCHAN_RFLOW_RNG1037 * register. Specifies the starting index for flow IDs the receive channel is to1038 * make use of beyond the default flow. flowid_start and @ref flowid_cnt must be1039 * set as valid and configured together. The starting flow ID set by1040 * @ref flowid_cnt must be a flow index within the Navigator Subsystem's subset1041 * of flows beyond the default flows statically mapped to receive channels.1042 * The additional flows must be assigned to the host, or a subordinate of the1043 * host, requesting configuration of the receive channel.1044 *1045 * @flowid_cnt: UDMAP receive channel additional flows count configuration to1046 * program into the flowid_cnt field of the RCHAN_RFLOW_RNG register.1047 * This field specifies how many flow IDs are in the additional contiguous range1048 * of legal flow IDs for the channel. @ref flowid_start and flowid_cnt must be1049 * set as valid and configured together. Disabling the valid_params field bit1050 * for flowid_cnt indicates no flow IDs other than the default are to be1051 * allocated and used by the receive channel. @ref flowid_start plus flowid_cnt1052 * cannot be greater than the number of receive flows in the receive channel's1053 * Navigator Subsystem. The additional flows must be assigned to the host, or a1054 * subordinate of the host, requesting configuration of the receive channel.1055 *1056 * @rx_pause_on_err: UDMAP receive channel pause on error configuration to be1057 * programmed into the rx_pause_on_err field of the channel's RCHAN_RCFG1058 * register.1059 *1060 * @rx_atype: UDMAP receive channel non Ring Accelerator access pointer1061 * interpretation configuration to be programmed into the rx_atype field of the1062 * channel's RCHAN_RCFG register.1063 *1064 * @rx_chan_type: UDMAP receive channel functional channel type and work passing1065 * mechanism configuration to be programmed into the rx_chan_type field of the1066 * channel's RCHAN_RCFG register.1067 *1068 * @rx_ignore_short: UDMAP receive channel short packet treatment configuration1069 * to be programmed into the rx_ignore_short field of the RCHAN_RCFG register.1070 *1071 * @rx_ignore_long: UDMAP receive channel long packet treatment configuration to1072 * be programmed into the rx_ignore_long field of the RCHAN_RCFG register.1073 *1074 * @rx_burst_size: UDMAP receive channel burst size configuration to be1075 * programmed into the rx_burst_size field of the RCHAN_RCFG register.1076 */1077struct ti_sci_msg_rm_udmap_rx_ch_cfg_req {1078 struct ti_sci_msg_hdr hdr;1079 u32 valid_params;1080 u16 nav_id;1081 u16 index;1082 u16 rx_fetch_size;1083 u16 rxcq_qnum;1084 u8 rx_priority;1085 u8 rx_qos;1086 u8 rx_orderid;1087 u8 rx_sched_priority;1088 u16 flowid_start;1089 u16 flowid_cnt;1090 u8 rx_pause_on_err;1091 u8 rx_atype;1092 u8 rx_chan_type;1093 u8 rx_ignore_short;1094 u8 rx_ignore_long;1095 u8 rx_burst_size;1096} __packed;1097 1098/**1099 * Configures a Navigator Subsystem UDMAP receive flow1100 *1101 * Configures a Navigator Subsystem UDMAP receive flow's registers.1102 * Configuration does not include the flow registers which handle size-based1103 * free descriptor queue routing.1104 *1105 * The flow index must be assigned to the host defined in the TISCI header via1106 * the RM board configuration resource assignment range list.1107 *1108 * @hdr: Standard TISCI header1109 *1110 * @valid_params1111 * Bitfield defining validity of rx flow configuration parameters. The1112 * rx flow configuration fields are not valid, and will not be used for flow1113 * configuration, if their corresponding valid bit is zero. Valid bit usage:1114 * 0 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_einfo_present1115 * 1 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_psinfo_present1116 * 2 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_error_handling1117 * 3 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_desc_type1118 * 4 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_sop_offset1119 * 5 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_qnum1120 * 6 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi1121 * 7 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo1122 * 8 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi1123 * 9 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo1124 * 10 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi_sel1125 * 11 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo_sel1126 * 12 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi_sel1127 * 13 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo_sel1128 * 14 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq0_sz0_qnum1129 * 15 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq1_sz0_qnum1130 * 16 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq2_sz0_qnum1131 * 17 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq3_sz0_qnum1132 * 18 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_ps_location1133 *1134 * @nav_id: SoC device ID of Navigator Subsystem from which the receive flow is1135 * allocated1136 *1137 * @flow_index: UDMAP receive flow index for non-optional configuration.1138 *1139 * @rx_einfo_present:1140 * UDMAP receive flow extended packet info present configuration to be1141 * programmed into the rx_einfo_present field of the flow's RFLOW_RFA register.1142 *1143 * @rx_psinfo_present:1144 * UDMAP receive flow PS words present configuration to be programmed into the1145 * rx_psinfo_present field of the flow's RFLOW_RFA register.1146 *1147 * @rx_error_handling:1148 * UDMAP receive flow error handling configuration to be programmed into the1149 * rx_error_handling field of the flow's RFLOW_RFA register.1150 *1151 * @rx_desc_type:1152 * UDMAP receive flow descriptor type configuration to be programmed into the1153 * rx_desc_type field field of the flow's RFLOW_RFA register.1154 *1155 * @rx_sop_offset:1156 * UDMAP receive flow start of packet offset configuration to be programmed1157 * into the rx_sop_offset field of the RFLOW_RFA register. See the UDMAP1158 * section of the TRM for more information on this setting. Valid values for1159 * this field are 0-255 bytes.1160 *1161 * @rx_dest_qnum:1162 * UDMAP receive flow destination queue configuration to be programmed into the1163 * rx_dest_qnum field of the flow's RFLOW_RFA register. The specified1164 * destination queue must be valid within the Navigator Subsystem and must be1165 * owned by the host, or a subordinate of the host, requesting allocation and1166 * configuration of the receive flow.1167 *1168 * @rx_src_tag_hi:1169 * UDMAP receive flow source tag high byte constant configuration to be1170 * programmed into the rx_src_tag_hi field of the flow's RFLOW_RFB register.1171 * See the UDMAP section of the TRM for more information on this setting.1172 *1173 * @rx_src_tag_lo:1174 * UDMAP receive flow source tag low byte constant configuration to be1175 * programmed into the rx_src_tag_lo field of the flow's RFLOW_RFB register.1176 * See the UDMAP section of the TRM for more information on this setting.1177 *1178 * @rx_dest_tag_hi:1179 * UDMAP receive flow destination tag high byte constant configuration to be1180 * programmed into the rx_dest_tag_hi field of the flow's RFLOW_RFB register.1181 * See the UDMAP section of the TRM for more information on this setting.1182 *1183 * @rx_dest_tag_lo:1184 * UDMAP receive flow destination tag low byte constant configuration to be1185 * programmed into the rx_dest_tag_lo field of the flow's RFLOW_RFB register.1186 * See the UDMAP section of the TRM for more information on this setting.1187 *1188 * @rx_src_tag_hi_sel:1189 * UDMAP receive flow source tag high byte selector configuration to be1190 * programmed into the rx_src_tag_hi_sel field of the RFLOW_RFC register. See1191 * the UDMAP section of the TRM for more information on this setting.1192 *1193 * @rx_src_tag_lo_sel:1194 * UDMAP receive flow source tag low byte selector configuration to be1195 * programmed into the rx_src_tag_lo_sel field of the RFLOW_RFC register. See1196 * the UDMAP section of the TRM for more information on this setting.1197 *1198 * @rx_dest_tag_hi_sel:1199 * UDMAP receive flow destination tag high byte selector configuration to be1200 * programmed into the rx_dest_tag_hi_sel field of the RFLOW_RFC register. See1201 * the UDMAP section of the TRM for more information on this setting.1202 *1203 * @rx_dest_tag_lo_sel:1204 * UDMAP receive flow destination tag low byte selector configuration to be1205 * programmed into the rx_dest_tag_lo_sel field of the RFLOW_RFC register. See1206 * the UDMAP section of the TRM for more information on this setting.1207 *1208 * @rx_fdq0_sz0_qnum:1209 * UDMAP receive flow free descriptor queue 0 configuration to be programmed1210 * into the rx_fdq0_sz0_qnum field of the flow's RFLOW_RFD register. See the1211 * UDMAP section of the TRM for more information on this setting. The specified1212 * free queue must be valid within the Navigator Subsystem and must be owned1213 * by the host, or a subordinate of the host, requesting allocation and1214 * configuration of the receive flow.1215 *1216 * @rx_fdq1_qnum:1217 * UDMAP receive flow free descriptor queue 1 configuration to be programmed1218 * into the rx_fdq1_qnum field of the flow's RFLOW_RFD register. See the1219 * UDMAP section of the TRM for more information on this setting. The specified1220 * free queue must be valid within the Navigator Subsystem and must be owned1221 * by the host, or a subordinate of the host, requesting allocation and1222 * configuration of the receive flow.1223 *1224 * @rx_fdq2_qnum:1225 * UDMAP receive flow free descriptor queue 2 configuration to be programmed1226 * into the rx_fdq2_qnum field of the flow's RFLOW_RFE register. See the1227 * UDMAP section of the TRM for more information on this setting. The specified1228 * free queue must be valid within the Navigator Subsystem and must be owned1229 * by the host, or a subordinate of the host, requesting allocation and1230 * configuration of the receive flow.1231 *1232 * @rx_fdq3_qnum:1233 * UDMAP receive flow free descriptor queue 3 configuration to be programmed1234 * into the rx_fdq3_qnum field of the flow's RFLOW_RFE register. See the1235 * UDMAP section of the TRM for more information on this setting. The specified1236 * free queue must be valid within the Navigator Subsystem and must be owned1237 * by the host, or a subordinate of the host, requesting allocation and1238 * configuration of the receive flow.1239 *1240 * @rx_ps_location:1241 * UDMAP receive flow PS words location configuration to be programmed into the1242 * rx_ps_location field of the flow's RFLOW_RFA register.1243 */1244struct ti_sci_msg_rm_udmap_flow_cfg_req {1245 struct ti_sci_msg_hdr hdr;1246 u32 valid_params;1247 u16 nav_id;1248 u16 flow_index;1249 u8 rx_einfo_present;1250 u8 rx_psinfo_present;1251 u8 rx_error_handling;1252 u8 rx_desc_type;1253 u16 rx_sop_offset;1254 u16 rx_dest_qnum;1255 u8 rx_src_tag_hi;1256 u8 rx_src_tag_lo;1257 u8 rx_dest_tag_hi;1258 u8 rx_dest_tag_lo;1259 u8 rx_src_tag_hi_sel;1260 u8 rx_src_tag_lo_sel;1261 u8 rx_dest_tag_hi_sel;1262 u8 rx_dest_tag_lo_sel;1263 u16 rx_fdq0_sz0_qnum;1264 u16 rx_fdq1_qnum;1265 u16 rx_fdq2_qnum;1266 u16 rx_fdq3_qnum;1267 u8 rx_ps_location;1268} __packed;1269 1270/**1271 * struct ti_sci_msg_req_proc_request - Request a processor1272 * @hdr: Generic Header1273 * @processor_id: ID of processor being requested1274 *1275 * Request type is TI_SCI_MSG_PROC_REQUEST, response is a generic ACK/NACK1276 * message.1277 */1278struct ti_sci_msg_req_proc_request {1279 struct ti_sci_msg_hdr hdr;1280 u8 processor_id;1281} __packed;1282 1283/**1284 * struct ti_sci_msg_req_proc_release - Release a processor1285 * @hdr: Generic Header1286 * @processor_id: ID of processor being released1287 *1288 * Request type is TI_SCI_MSG_PROC_RELEASE, response is a generic ACK/NACK1289 * message.1290 */1291struct ti_sci_msg_req_proc_release {1292 struct ti_sci_msg_hdr hdr;1293 u8 processor_id;1294} __packed;1295 1296/**1297 * struct ti_sci_msg_req_proc_handover - Handover a processor to a host1298 * @hdr: Generic Header1299 * @processor_id: ID of processor being handed over1300 * @host_id: Host ID the control needs to be transferred to1301 *1302 * Request type is TI_SCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK1303 * message.1304 */1305struct ti_sci_msg_req_proc_handover {1306 struct ti_sci_msg_hdr hdr;1307 u8 processor_id;1308 u8 host_id;1309} __packed;1310 1311/* Boot Vector masks */1312#define TI_SCI_ADDR_LOW_MASK GENMASK_ULL(31, 0)1313#define TI_SCI_ADDR_HIGH_MASK GENMASK_ULL(63, 32)1314#define TI_SCI_ADDR_HIGH_SHIFT 321315 1316/**1317 * struct ti_sci_msg_req_set_config - Set Processor boot configuration1318 * @hdr: Generic Header1319 * @processor_id: ID of processor being configured1320 * @bootvector_low: Lower 32 bit address (Little Endian) of boot vector1321 * @bootvector_high: Higher 32 bit address (Little Endian) of boot vector1322 * @config_flags_set: Optional Processor specific Config Flags to set.1323 * Setting a bit here implies the corresponding mode1324 * will be set1325 * @config_flags_clear: Optional Processor specific Config Flags to clear.1326 * Setting a bit here implies the corresponding mode1327 * will be cleared1328 *1329 * Request type is TI_SCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK1330 * message.1331 */1332struct ti_sci_msg_req_set_config {1333 struct ti_sci_msg_hdr hdr;1334 u8 processor_id;1335 u32 bootvector_low;1336 u32 bootvector_high;1337 u32 config_flags_set;1338 u32 config_flags_clear;1339} __packed;1340 1341/**1342 * struct ti_sci_msg_req_set_ctrl - Set Processor boot control flags1343 * @hdr: Generic Header1344 * @processor_id: ID of processor being configured1345 * @control_flags_set: Optional Processor specific Control Flags to set.1346 * Setting a bit here implies the corresponding mode1347 * will be set1348 * @control_flags_clear:Optional Processor specific Control Flags to clear.1349 * Setting a bit here implies the corresponding mode1350 * will be cleared1351 *1352 * Request type is TI_SCI_MSG_SET_CTRL, response is a generic ACK/NACK1353 * message.1354 */1355struct ti_sci_msg_req_set_ctrl {1356 struct ti_sci_msg_hdr hdr;1357 u8 processor_id;1358 u32 control_flags_set;1359 u32 control_flags_clear;1360} __packed;1361 1362/**1363 * struct ti_sci_msg_req_get_status - Processor boot status request1364 * @hdr: Generic Header1365 * @processor_id: ID of processor whose status is being requested1366 *1367 * Request type is TI_SCI_MSG_GET_STATUS, response is an appropriate1368 * message, or NACK in case of inability to satisfy request.1369 */1370struct ti_sci_msg_req_get_status {1371 struct ti_sci_msg_hdr hdr;1372 u8 processor_id;1373} __packed;1374 1375/**1376 * struct ti_sci_msg_resp_get_status - Processor boot status response1377 * @hdr: Generic Header1378 * @processor_id: ID of processor whose status is returned1379 * @bootvector_low: Lower 32 bit address (Little Endian) of boot vector1380 * @bootvector_high: Higher 32 bit address (Little Endian) of boot vector1381 * @config_flags: Optional Processor specific Config Flags set currently1382 * @control_flags: Optional Processor specific Control Flags set currently1383 * @status_flags: Optional Processor specific Status Flags set currently1384 *1385 * Response structure to a TI_SCI_MSG_GET_STATUS request.1386 */1387struct ti_sci_msg_resp_get_status {1388 struct ti_sci_msg_hdr hdr;1389 u8 processor_id;1390 u32 bootvector_low;1391 u32 bootvector_high;1392 u32 config_flags;1393 u32 control_flags;1394 u32 status_flags;1395} __packed;1396 1397#endif /* __TI_SCI_H */1398