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1# SPDX-License-Identifier: GPL-2.0-only2#3# FPGA framework configuration4#5 6menuconfig FPGA7 tristate "FPGA Configuration Framework"8 help9 Say Y here if you want support for configuring FPGAs from the10 kernel. The FPGA framework adds an FPGA manager class and FPGA11 manager drivers.12 13if FPGA14 15config FPGA_MGR_SOCFPGA16 tristate "Altera SOCFPGA FPGA Manager"17 depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST18 help19 FPGA manager driver support for Altera SOCFPGA.20 21config FPGA_MGR_SOCFPGA_A1022 tristate "Altera SoCFPGA Arria10"23 depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST24 select REGMAP_MMIO25 help26 FPGA manager driver support for Altera Arria10 SoCFPGA.27 28config ALTERA_PR_IP_CORE29 tristate "Altera Partial Reconfiguration IP Core"30 help31 Core driver support for Altera Partial Reconfiguration IP component32 33config ALTERA_PR_IP_CORE_PLAT34 tristate "Platform support of Altera Partial Reconfiguration IP Core"35 depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM36 help37 Platform driver support for Altera Partial Reconfiguration IP38 component39 40config FPGA_MGR_ALTERA_PS_SPI41 tristate "Altera FPGA Passive Serial over SPI"42 depends on SPI43 select BITREVERSE44 help45 FPGA manager driver support for Altera Arria/Cyclone/Stratix46 using the passive serial interface over SPI.47 48config FPGA_MGR_ALTERA_CVP49 tristate "Altera CvP FPGA Manager"50 depends on PCI51 help52 FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,53 Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe.54 55config FPGA_MGR_ZYNQ_FPGA56 tristate "Xilinx Zynq FPGA"57 depends on ARCH_ZYNQ || COMPILE_TEST58 help59 FPGA manager driver support for Xilinx Zynq FPGAs.60 61config FPGA_MGR_STRATIX10_SOC62 tristate "Intel Stratix10 SoC FPGA Manager"63 depends on (ARCH_INTEL_SOCFPGA && INTEL_STRATIX10_SERVICE)64 help65 FPGA manager driver support for the Intel Stratix10 SoC.66 67config FPGA_MGR_XILINX_CORE68 tristate69 70config FPGA_MGR_XILINX_SELECTMAP71 tristate "Xilinx Configuration over SelectMAP"72 depends on HAS_IOMEM73 select FPGA_MGR_XILINX_CORE74 help75 FPGA manager driver support for Xilinx FPGA configuration76 over SelectMAP interface.77 78config FPGA_MGR_XILINX_SPI79 tristate "Xilinx Configuration over Slave Serial (SPI)"80 depends on SPI81 select FPGA_MGR_XILINX_CORE82 help83 FPGA manager driver support for Xilinx FPGA configuration84 over slave serial interface.85 86config FPGA_MGR_ICE40_SPI87 tristate "Lattice iCE40 SPI"88 depends on OF && SPI89 help90 FPGA manager driver support for Lattice iCE40 FPGAs over SPI.91 92config FPGA_MGR_MACHXO2_SPI93 tristate "Lattice MachXO2 SPI"94 depends on SPI95 help96 FPGA manager driver support for Lattice MachXO2 configuration97 over slave SPI interface.98 99config FPGA_MGR_TS73XX100 tristate "Technologic Systems TS-73xx SBC FPGA Manager"101 depends on ARCH_EP93XX && MACH_TS72XX102 help103 FPGA manager driver support for the Altera Cyclone II FPGA104 present on the TS-73xx SBC boards.105 106config FPGA_BRIDGE107 tristate "FPGA Bridge Framework"108 help109 Say Y here if you want to support bridges connected between host110 processors and FPGAs or between FPGAs.111 112config SOCFPGA_FPGA_BRIDGE113 tristate "Altera SoCFPGA FPGA Bridges"114 depends on ARCH_INTEL_SOCFPGA && FPGA_BRIDGE115 help116 Say Y to enable drivers for FPGA bridges for Altera SOCFPGA117 devices.118 119config ALTERA_FREEZE_BRIDGE120 tristate "Altera FPGA Freeze Bridge"121 depends on FPGA_BRIDGE && HAS_IOMEM122 help123 Say Y to enable drivers for Altera FPGA Freeze bridges. A124 freeze bridge is a bridge that exists in the FPGA fabric to125 isolate one region of the FPGA from the busses while that126 region is being reprogrammed.127 128config XILINX_PR_DECOUPLER129 tristate "Xilinx LogiCORE PR Decoupler"130 depends on FPGA_BRIDGE131 depends on HAS_IOMEM132 help133 Say Y to enable drivers for Xilinx LogiCORE PR Decoupler134 or Xilinx Dynamic Function eXchange AIX Shutdown Manager.135 The PR Decoupler exists in the FPGA fabric to isolate one136 region of the FPGA from the busses while that region is137 being reprogrammed during partial reconfig.138 The Dynamic Function eXchange AXI shutdown manager prevents139 AXI traffic from passing through the bridge. The controller140 safely handles AXI4MM and AXI4-Lite interfaces on a141 Reconfigurable Partition when it is undergoing dynamic142 reconfiguration, preventing the system deadlock that can143 occur if AXI transactions are interrupted by DFX.144 145config FPGA_REGION146 tristate "FPGA Region"147 depends on FPGA_BRIDGE148 help149 FPGA Region common code. An FPGA Region controls an FPGA Manager150 and the FPGA Bridges associated with either a reconfigurable151 region of an FPGA or a whole FPGA.152 153config OF_FPGA_REGION154 tristate "FPGA Region Device Tree Overlay Support"155 depends on OF && FPGA_REGION156 help157 Support for loading FPGA images by applying a Device Tree158 overlay.159 160config FPGA_DFL161 tristate "FPGA Device Feature List (DFL) support"162 select FPGA_BRIDGE163 select FPGA_REGION164 depends on HAS_IOMEM165 help166 Device Feature List (DFL) defines a feature list structure that167 creates a linked list of feature headers within the MMIO space168 to provide an extensible way of adding features for FPGA.169 Driver can walk through the feature headers to enumerate feature170 devices (e.g. FPGA Management Engine, Port and Accelerator171 Function Unit) and their private features for target FPGA devices.172 173 Select this option to enable common support for Field-Programmable174 Gate Array (FPGA) solutions which implement Device Feature List.175 It provides enumeration APIs and feature device infrastructure.176 177config FPGA_DFL_FME178 tristate "FPGA DFL FME Driver"179 depends on FPGA_DFL && HWMON && PERF_EVENTS180 help181 The FPGA Management Engine (FME) is a feature device implemented182 under Device Feature List (DFL) framework. Select this option to183 enable the platform device driver for FME which implements all184 FPGA platform level management features. There shall be one FME185 per DFL based FPGA device.186 187config FPGA_DFL_FME_MGR188 tristate "FPGA DFL FME Manager Driver"189 depends on FPGA_DFL_FME && HAS_IOMEM190 help191 Say Y to enable FPGA Manager driver for FPGA Management Engine.192 193config FPGA_DFL_FME_BRIDGE194 tristate "FPGA DFL FME Bridge Driver"195 depends on FPGA_DFL_FME && HAS_IOMEM196 help197 Say Y to enable FPGA Bridge driver for FPGA Management Engine.198 199config FPGA_DFL_FME_REGION200 tristate "FPGA DFL FME Region Driver"201 depends on FPGA_DFL_FME && HAS_IOMEM202 help203 Say Y to enable FPGA Region driver for FPGA Management Engine.204 205config FPGA_DFL_AFU206 tristate "FPGA DFL AFU Driver"207 depends on FPGA_DFL208 help209 This is the driver for FPGA Accelerated Function Unit (AFU) which210 implements AFU and Port management features. A User AFU connects211 to the FPGA infrastructure via a Port. There may be more than one212 Port/AFU per DFL based FPGA device.213 214config FPGA_DFL_NIOS_INTEL_PAC_N3000215 tristate "FPGA DFL NIOS Driver for Intel PAC N3000"216 depends on FPGA_DFL217 select REGMAP218 help219 This is the driver for the N3000 Nios private feature on Intel220 PAC (Programmable Acceleration Card) N3000. It communicates221 with the embedded Nios processor to configure the retimers on222 the card. It also instantiates the SPI master (spi-altera) for223 the card's BMC (Board Management Controller).224 225config FPGA_DFL_PCI226 tristate "FPGA DFL PCIe Device Driver"227 depends on PCI && FPGA_DFL228 help229 Select this option to enable PCIe driver for PCIe-based230 Field-Programmable Gate Array (FPGA) solutions which implement231 the Device Feature List (DFL). This driver provides interfaces232 for userspace applications to configure, enumerate, open and access233 FPGA accelerators on the FPGA DFL devices, enables system level234 management functions such as FPGA partial reconfiguration, power235 management and virtualization with DFL framework and DFL feature236 device drivers.237 238 To compile this as a module, choose M here.239 240config FPGA_MGR_ZYNQMP_FPGA241 tristate "Xilinx ZynqMP FPGA"242 depends on ZYNQMP_FIRMWARE || (!ZYNQMP_FIRMWARE && COMPILE_TEST)243 help244 FPGA manager driver support for Xilinx ZynqMP FPGAs.245 This driver uses the processor configuration port(PCAP)246 to configure the programmable logic(PL) through PS247 on ZynqMP SoC.248 249config FPGA_MGR_VERSAL_FPGA250 tristate "Xilinx Versal FPGA"251 depends on ARCH_ZYNQMP || COMPILE_TEST252 help253 Select this option to enable FPGA manager driver support for254 Xilinx Versal SoC. This driver uses the firmware interface to255 configure the programmable logic(PL).256 257 To compile this as a module, choose M here.258 259config FPGA_M10_BMC_SEC_UPDATE260 tristate "Intel MAX10 BMC Secure Update driver"261 depends on MFD_INTEL_M10_BMC_CORE262 select FW_LOADER263 select FW_UPLOAD264 help265 Secure update support for the Intel MAX10 board management266 controller.267 268 This is a subdriver of the Intel MAX10 board management controller269 (BMC) and provides support for secure updates for the BMC image,270 the FPGA image, the Root Entry Hashes, etc.271 272config FPGA_MGR_MICROCHIP_SPI273 tristate "Microchip Polarfire SPI FPGA manager"274 depends on SPI275 help276 FPGA manager driver support for Microchip Polarfire FPGAs277 programming over slave SPI interface with .dat formatted278 bitstream image.279 280config FPGA_MGR_LATTICE_SYSCONFIG281 tristate282 283config FPGA_MGR_LATTICE_SYSCONFIG_SPI284 tristate "Lattice sysCONFIG SPI FPGA manager"285 depends on SPI286 select FPGA_MGR_LATTICE_SYSCONFIG287 help288 FPGA manager driver support for Lattice FPGAs programming over slave289 SPI sysCONFIG interface.290 291source "drivers/fpga/tests/Kconfig"292 293endif # FPGA294