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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Driver Header File for FPGA Device Feature List (DFL) Support4 *5 * Copyright (C) 2017-2018 Intel Corporation, Inc.6 *7 * Authors:8 * Kang Luwei <luwei.kang@intel.com>9 * Zhang Yi <yi.z.zhang@intel.com>10 * Wu Hao <hao.wu@intel.com>11 * Xiao Guangrong <guangrong.xiao@linux.intel.com>12 */13 14#ifndef __FPGA_DFL_H15#define __FPGA_DFL_H16 17#include <linux/bitfield.h>18#include <linux/cdev.h>19#include <linux/delay.h>20#include <linux/eventfd.h>21#include <linux/fs.h>22#include <linux/interrupt.h>23#include <linux/iopoll.h>24#include <linux/io-64-nonatomic-lo-hi.h>25#include <linux/mod_devicetable.h>26#include <linux/platform_device.h>27#include <linux/slab.h>28#include <linux/uuid.h>29#include <linux/fpga/fpga-region.h>30 31/* maximum supported number of ports */32#define MAX_DFL_FPGA_PORT_NUM 433/* plus one for fme device */34#define MAX_DFL_FEATURE_DEV_NUM (MAX_DFL_FPGA_PORT_NUM + 1)35 36/* Reserved 0xfe for Header Group Register and 0xff for AFU */37#define FEATURE_ID_FIU_HEADER 0xfe38#define FEATURE_ID_AFU 0xff39 40#define FME_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER41#define FME_FEATURE_ID_THERMAL_MGMT 0x142#define FME_FEATURE_ID_POWER_MGMT 0x243#define FME_FEATURE_ID_GLOBAL_IPERF 0x344#define FME_FEATURE_ID_GLOBAL_ERR 0x445#define FME_FEATURE_ID_PR_MGMT 0x546#define FME_FEATURE_ID_HSSI 0x647#define FME_FEATURE_ID_GLOBAL_DPERF 0x748 49#define PORT_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER50#define PORT_FEATURE_ID_AFU FEATURE_ID_AFU51#define PORT_FEATURE_ID_ERROR 0x1052#define PORT_FEATURE_ID_UMSG 0x1153#define PORT_FEATURE_ID_UINT 0x1254#define PORT_FEATURE_ID_STP 0x1355 56/*57 * Device Feature Header Register Set58 *59 * For FIUs, they all have DFH + GUID + NEXT_AFU as common header registers.60 * For AFUs, they have DFH + GUID as common header registers.61 * For private features, they only have DFH register as common header.62 */63#define DFH 0x064#define GUID_L 0x865#define GUID_H 0x1066#define NEXT_AFU 0x1867 68#define DFH_SIZE 0x869 70/* Device Feature Header Register Bitfield */71#define DFH_ID GENMASK_ULL(11, 0) /* Feature ID */72#define DFH_ID_FIU_FME 073#define DFH_ID_FIU_PORT 174#define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */75#define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */76#define DFH_EOL BIT_ULL(40) /* End of list */77#define DFH_VERSION GENMASK_ULL(59, 52) /* DFH version */78#define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */79#define DFH_TYPE_AFU 180#define DFH_TYPE_PRIVATE 381#define DFH_TYPE_FIU 482 83/*84 * DFHv1 Register Offset definitons85 * In DHFv1, DFH + GUID + CSR_START + CSR_SIZE_GROUP + PARAM_HDR + PARAM_DATA86 * as common header registers87 */88#define DFHv1_CSR_ADDR 0x18 /* CSR Register start address */89#define DFHv1_CSR_SIZE_GRP 0x20 /* Size of Reg Block and Group/tag */90#define DFHv1_PARAM_HDR 0x28 /* Optional First Param header */91 92/*93 * CSR Rel Bit, 1'b0 = relative (offset from feature DFH start),94 * 1'b1 = absolute (ARM or other non-PCIe use)95 */96#define DFHv1_CSR_ADDR_REL BIT_ULL(0)97 98/* CSR Header Register Bit Definitions */99#define DFHv1_CSR_ADDR_MASK GENMASK_ULL(63, 1) /* 63:1 of CSR address */100 101/* CSR SIZE Goup Register Bit Definitions */102#define DFHv1_CSR_SIZE_GRP_INSTANCE_ID GENMASK_ULL(15, 0) /* Enumeration instantiated IP */103#define DFHv1_CSR_SIZE_GRP_GROUPING_ID GENMASK_ULL(30, 16) /* Group Features/interfaces */104#define DFHv1_CSR_SIZE_GRP_HAS_PARAMS BIT_ULL(31) /* Presence of Parameters */105#define DFHv1_CSR_SIZE_GRP_SIZE GENMASK_ULL(63, 32) /* Size of CSR Block in bytes */106 107/* PARAM Header Register Bit Definitions */108#define DFHv1_PARAM_HDR_ID GENMASK_ULL(15, 0) /* Id of this Param */109#define DFHv1_PARAM_HDR_VER GENMASK_ULL(31, 16) /* Version Param */110#define DFHv1_PARAM_HDR_NEXT_OFFSET GENMASK_ULL(63, 35) /* Offset of next Param */111#define DFHv1_PARAM_HDR_NEXT_EOP BIT_ULL(32)112#define DFHv1_PARAM_DATA 0x08 /* Offset of Param data from Param header */113 114#define DFHv1_PARAM_ID_MSI_X 0x1115#define DFHv1_PARAM_MSI_X_NUMV GENMASK_ULL(63, 32)116#define DFHv1_PARAM_MSI_X_STARTV GENMASK_ULL(31, 0)117 118/* Next AFU Register Bitfield */119#define NEXT_AFU_NEXT_DFH_OFST GENMASK_ULL(23, 0) /* Offset to next AFU */120 121/* FME Header Register Set */122#define FME_HDR_DFH DFH123#define FME_HDR_GUID_L GUID_L124#define FME_HDR_GUID_H GUID_H125#define FME_HDR_NEXT_AFU NEXT_AFU126#define FME_HDR_CAP 0x30127#define FME_HDR_PORT_OFST(n) (0x38 + ((n) * 0x8))128#define FME_PORT_OFST_BAR_SKIP 7129#define FME_HDR_BITSTREAM_ID 0x60130#define FME_HDR_BITSTREAM_MD 0x68131 132/* FME Fab Capability Register Bitfield */133#define FME_CAP_FABRIC_VERID GENMASK_ULL(7, 0) /* Fabric version ID */134#define FME_CAP_SOCKET_ID BIT_ULL(8) /* Socket ID */135#define FME_CAP_PCIE0_LINK_AVL BIT_ULL(12) /* PCIE0 Link */136#define FME_CAP_PCIE1_LINK_AVL BIT_ULL(13) /* PCIE1 Link */137#define FME_CAP_COHR_LINK_AVL BIT_ULL(14) /* Coherent Link */138#define FME_CAP_IOMMU_AVL BIT_ULL(16) /* IOMMU available */139#define FME_CAP_NUM_PORTS GENMASK_ULL(19, 17) /* Number of ports */140#define FME_CAP_ADDR_WIDTH GENMASK_ULL(29, 24) /* Address bus width */141#define FME_CAP_CACHE_SIZE GENMASK_ULL(43, 32) /* cache size in KB */142#define FME_CAP_CACHE_ASSOC GENMASK_ULL(47, 44) /* Associativity */143 144/* FME Port Offset Register Bitfield */145/* Offset to port device feature header */146#define FME_PORT_OFST_DFH_OFST GENMASK_ULL(23, 0)147/* PCI Bar ID for this port */148#define FME_PORT_OFST_BAR_ID GENMASK_ULL(34, 32)149/* AFU MMIO access permission. 1 - VF, 0 - PF. */150#define FME_PORT_OFST_ACC_CTRL BIT_ULL(55)151#define FME_PORT_OFST_ACC_PF 0152#define FME_PORT_OFST_ACC_VF 1153#define FME_PORT_OFST_IMP BIT_ULL(60)154 155/* FME Error Capability Register */156#define FME_ERROR_CAP 0x70157 158/* FME Error Capability Register Bitfield */159#define FME_ERROR_CAP_SUPP_INT BIT_ULL(0) /* Interrupt Support */160#define FME_ERROR_CAP_INT_VECT GENMASK_ULL(12, 1) /* Interrupt vector */161 162/* PORT Header Register Set */163#define PORT_HDR_DFH DFH164#define PORT_HDR_GUID_L GUID_L165#define PORT_HDR_GUID_H GUID_H166#define PORT_HDR_NEXT_AFU NEXT_AFU167#define PORT_HDR_CAP 0x30168#define PORT_HDR_CTRL 0x38169#define PORT_HDR_STS 0x40170#define PORT_HDR_USRCLK_CMD0 0x50171#define PORT_HDR_USRCLK_CMD1 0x58172#define PORT_HDR_USRCLK_STS0 0x60173#define PORT_HDR_USRCLK_STS1 0x68174 175/* Port Capability Register Bitfield */176#define PORT_CAP_PORT_NUM GENMASK_ULL(1, 0) /* ID of this port */177#define PORT_CAP_MMIO_SIZE GENMASK_ULL(23, 8) /* MMIO size in KB */178#define PORT_CAP_SUPP_INT_NUM GENMASK_ULL(35, 32) /* Interrupts num */179 180/* Port Control Register Bitfield */181#define PORT_CTRL_SFTRST BIT_ULL(0) /* Port soft reset */182/* Latency tolerance reporting. '1' >= 40us, '0' < 40us.*/183#define PORT_CTRL_LATENCY BIT_ULL(2)184#define PORT_CTRL_SFTRST_ACK BIT_ULL(4) /* HW ack for reset */185 186/* Port Status Register Bitfield */187#define PORT_STS_AP2_EVT BIT_ULL(13) /* AP2 event detected */188#define PORT_STS_AP1_EVT BIT_ULL(12) /* AP1 event detected */189#define PORT_STS_PWR_STATE GENMASK_ULL(11, 8) /* AFU power states */190#define PORT_STS_PWR_STATE_NORM 0191#define PORT_STS_PWR_STATE_AP1 1 /* 50% throttling */192#define PORT_STS_PWR_STATE_AP2 2 /* 90% throttling */193#define PORT_STS_PWR_STATE_AP6 6 /* 100% throttling */194 195/* Port Error Capability Register */196#define PORT_ERROR_CAP 0x38197 198/* Port Error Capability Register Bitfield */199#define PORT_ERROR_CAP_SUPP_INT BIT_ULL(0) /* Interrupt Support */200#define PORT_ERROR_CAP_INT_VECT GENMASK_ULL(12, 1) /* Interrupt vector */201 202/* Port Uint Capability Register */203#define PORT_UINT_CAP 0x8204 205/* Port Uint Capability Register Bitfield */206#define PORT_UINT_CAP_INT_NUM GENMASK_ULL(11, 0) /* Interrupts num */207#define PORT_UINT_CAP_FST_VECT GENMASK_ULL(23, 12) /* First Vector */208 209/**210 * struct dfl_fpga_port_ops - port ops211 *212 * @name: name of this port ops, to match with port platform device.213 * @owner: pointer to the module which owns this port ops.214 * @node: node to link port ops to global list.215 * @get_id: get port id from hardware.216 * @enable_set: enable/disable the port.217 */218struct dfl_fpga_port_ops {219 const char *name;220 struct module *owner;221 struct list_head node;222 int (*get_id)(struct platform_device *pdev);223 int (*enable_set)(struct platform_device *pdev, bool enable);224};225 226void dfl_fpga_port_ops_add(struct dfl_fpga_port_ops *ops);227void dfl_fpga_port_ops_del(struct dfl_fpga_port_ops *ops);228struct dfl_fpga_port_ops *dfl_fpga_port_ops_get(struct platform_device *pdev);229void dfl_fpga_port_ops_put(struct dfl_fpga_port_ops *ops);230int dfl_fpga_check_port_id(struct platform_device *pdev, void *pport_id);231 232/**233 * struct dfl_feature_id - dfl private feature id234 *235 * @id: unique dfl private feature id.236 */237struct dfl_feature_id {238 u16 id;239};240 241/**242 * struct dfl_feature_driver - dfl private feature driver243 *244 * @id_table: id_table for dfl private features supported by this driver.245 * @ops: ops of this dfl private feature driver.246 */247struct dfl_feature_driver {248 const struct dfl_feature_id *id_table;249 const struct dfl_feature_ops *ops;250};251 252/**253 * struct dfl_feature_irq_ctx - dfl private feature interrupt context254 *255 * @irq: Linux IRQ number of this interrupt.256 * @trigger: eventfd context to signal when interrupt happens.257 * @name: irq name needed when requesting irq.258 */259struct dfl_feature_irq_ctx {260 int irq;261 struct eventfd_ctx *trigger;262 char *name;263};264 265/**266 * struct dfl_feature - sub feature of the feature devices267 *268 * @dev: ptr to pdev of the feature device which has the sub feature.269 * @id: sub feature id.270 * @revision: revision of this sub feature.271 * @resource_index: each sub feature has one mmio resource for its registers.272 * this index is used to find its mmio resource from the273 * feature dev (platform device)'s resources.274 * @ioaddr: mapped mmio resource address.275 * @irq_ctx: interrupt context list.276 * @nr_irqs: number of interrupt contexts.277 * @ops: ops of this sub feature.278 * @ddev: ptr to the dfl device of this sub feature.279 * @priv: priv data of this feature.280 * @dfh_version: version of the DFH281 * @param_size: size of dfh parameters282 * @params: point to memory copy of dfh parameters283 */284struct dfl_feature {285 struct platform_device *dev;286 u16 id;287 u8 revision;288 int resource_index;289 void __iomem *ioaddr;290 struct dfl_feature_irq_ctx *irq_ctx;291 unsigned int nr_irqs;292 const struct dfl_feature_ops *ops;293 struct dfl_device *ddev;294 void *priv;295 u8 dfh_version;296 unsigned int param_size;297 void *params;298};299 300#define FEATURE_DEV_ID_UNUSED (-1)301 302/**303 * struct dfl_feature_platform_data - platform data for feature devices304 *305 * @node: node to link feature devs to container device's port_dev_list.306 * @lock: mutex to protect platform data.307 * @cdev: cdev of feature dev.308 * @dev: ptr to platform device linked with this platform data.309 * @dfl_cdev: ptr to container device.310 * @id: id used for this feature device.311 * @disable_count: count for port disable.312 * @excl_open: set on feature device exclusive open.313 * @open_count: count for feature device open.314 * @num: number for sub features.315 * @private: ptr to feature dev private data.316 * @features: sub features of this feature dev.317 */318struct dfl_feature_platform_data {319 struct list_head node;320 struct mutex lock;321 struct cdev cdev;322 struct platform_device *dev;323 struct dfl_fpga_cdev *dfl_cdev;324 int id;325 unsigned int disable_count;326 bool excl_open;327 int open_count;328 void *private;329 int num;330 struct dfl_feature features[];331};332 333static inline334int dfl_feature_dev_use_begin(struct dfl_feature_platform_data *pdata,335 bool excl)336{337 if (pdata->excl_open)338 return -EBUSY;339 340 if (excl) {341 if (pdata->open_count)342 return -EBUSY;343 344 pdata->excl_open = true;345 }346 pdata->open_count++;347 348 return 0;349}350 351static inline352void dfl_feature_dev_use_end(struct dfl_feature_platform_data *pdata)353{354 pdata->excl_open = false;355 356 if (WARN_ON(pdata->open_count <= 0))357 return;358 359 pdata->open_count--;360}361 362static inline363int dfl_feature_dev_use_count(struct dfl_feature_platform_data *pdata)364{365 return pdata->open_count;366}367 368static inline369void dfl_fpga_pdata_set_private(struct dfl_feature_platform_data *pdata,370 void *private)371{372 pdata->private = private;373}374 375static inline376void *dfl_fpga_pdata_get_private(struct dfl_feature_platform_data *pdata)377{378 return pdata->private;379}380 381struct dfl_feature_ops {382 int (*init)(struct platform_device *pdev, struct dfl_feature *feature);383 void (*uinit)(struct platform_device *pdev,384 struct dfl_feature *feature);385 long (*ioctl)(struct platform_device *pdev, struct dfl_feature *feature,386 unsigned int cmd, unsigned long arg);387};388 389#define DFL_FPGA_FEATURE_DEV_FME "dfl-fme"390#define DFL_FPGA_FEATURE_DEV_PORT "dfl-port"391 392void dfl_fpga_dev_feature_uinit(struct platform_device *pdev);393int dfl_fpga_dev_feature_init(struct platform_device *pdev,394 struct dfl_feature_driver *feature_drvs);395 396int dfl_fpga_dev_ops_register(struct platform_device *pdev,397 const struct file_operations *fops,398 struct module *owner);399void dfl_fpga_dev_ops_unregister(struct platform_device *pdev);400 401static inline402struct platform_device *dfl_fpga_inode_to_feature_dev(struct inode *inode)403{404 struct dfl_feature_platform_data *pdata;405 406 pdata = container_of(inode->i_cdev, struct dfl_feature_platform_data,407 cdev);408 return pdata->dev;409}410 411#define dfl_fpga_dev_for_each_feature(pdata, feature) \412 for ((feature) = (pdata)->features; \413 (feature) < (pdata)->features + (pdata)->num; (feature)++)414 415static inline416struct dfl_feature *dfl_get_feature_by_id(struct device *dev, u16 id)417{418 struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);419 struct dfl_feature *feature;420 421 dfl_fpga_dev_for_each_feature(pdata, feature)422 if (feature->id == id)423 return feature;424 425 return NULL;426}427 428static inline429void __iomem *dfl_get_feature_ioaddr_by_id(struct device *dev, u16 id)430{431 struct dfl_feature *feature = dfl_get_feature_by_id(dev, id);432 433 if (feature && feature->ioaddr)434 return feature->ioaddr;435 436 WARN_ON(1);437 return NULL;438}439 440static inline441struct device *dfl_fpga_pdata_to_parent(struct dfl_feature_platform_data *pdata)442{443 return pdata->dev->dev.parent->parent;444}445 446static inline bool dfl_feature_is_fme(void __iomem *base)447{448 u64 v = readq(base + DFH);449 450 return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&451 (FIELD_GET(DFH_ID, v) == DFH_ID_FIU_FME);452}453 454static inline bool dfl_feature_is_port(void __iomem *base)455{456 u64 v = readq(base + DFH);457 458 return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&459 (FIELD_GET(DFH_ID, v) == DFH_ID_FIU_PORT);460}461 462static inline u8 dfl_feature_revision(void __iomem *base)463{464 return (u8)FIELD_GET(DFH_REVISION, readq(base + DFH));465}466 467/**468 * struct dfl_fpga_enum_info - DFL FPGA enumeration information469 *470 * @dev: parent device.471 * @dfls: list of device feature lists.472 * @nr_irqs: number of irqs for all feature devices.473 * @irq_table: Linux IRQ numbers for all irqs, indexed by hw irq numbers.474 */475struct dfl_fpga_enum_info {476 struct device *dev;477 struct list_head dfls;478 unsigned int nr_irqs;479 int *irq_table;480};481 482/**483 * struct dfl_fpga_enum_dfl - DFL FPGA enumeration device feature list info484 *485 * @start: base address of this device feature list.486 * @len: size of this device feature list.487 * @node: node in list of device feature lists.488 */489struct dfl_fpga_enum_dfl {490 resource_size_t start;491 resource_size_t len;492 struct list_head node;493};494 495struct dfl_fpga_enum_info *dfl_fpga_enum_info_alloc(struct device *dev);496int dfl_fpga_enum_info_add_dfl(struct dfl_fpga_enum_info *info,497 resource_size_t start, resource_size_t len);498int dfl_fpga_enum_info_add_irq(struct dfl_fpga_enum_info *info,499 unsigned int nr_irqs, int *irq_table);500void dfl_fpga_enum_info_free(struct dfl_fpga_enum_info *info);501 502/**503 * struct dfl_fpga_cdev - container device of DFL based FPGA504 *505 * @parent: parent device of this container device.506 * @region: base fpga region.507 * @fme_dev: FME feature device under this container device.508 * @lock: mutex lock to protect the port device list.509 * @port_dev_list: list of all port feature devices under this container device.510 * @released_port_num: released port number under this container device.511 */512struct dfl_fpga_cdev {513 struct device *parent;514 struct fpga_region *region;515 struct device *fme_dev;516 struct mutex lock;517 struct list_head port_dev_list;518 int released_port_num;519};520 521struct dfl_fpga_cdev *522dfl_fpga_feature_devs_enumerate(struct dfl_fpga_enum_info *info);523void dfl_fpga_feature_devs_remove(struct dfl_fpga_cdev *cdev);524 525/*526 * need to drop the device reference with put_device() after use port platform527 * device returned by __dfl_fpga_cdev_find_port and dfl_fpga_cdev_find_port528 * functions.529 */530struct platform_device *531__dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data,532 int (*match)(struct platform_device *, void *));533 534static inline struct platform_device *535dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data,536 int (*match)(struct platform_device *, void *))537{538 struct platform_device *pdev;539 540 mutex_lock(&cdev->lock);541 pdev = __dfl_fpga_cdev_find_port(cdev, data, match);542 mutex_unlock(&cdev->lock);543 544 return pdev;545}546 547int dfl_fpga_cdev_release_port(struct dfl_fpga_cdev *cdev, int port_id);548int dfl_fpga_cdev_assign_port(struct dfl_fpga_cdev *cdev, int port_id);549void dfl_fpga_cdev_config_ports_pf(struct dfl_fpga_cdev *cdev);550int dfl_fpga_cdev_config_ports_vf(struct dfl_fpga_cdev *cdev, int num_vf);551int dfl_fpga_set_irq_triggers(struct dfl_feature *feature, unsigned int start,552 unsigned int count, int32_t *fds);553long dfl_feature_ioctl_get_num_irqs(struct platform_device *pdev,554 struct dfl_feature *feature,555 unsigned long arg);556long dfl_feature_ioctl_set_irq(struct platform_device *pdev,557 struct dfl_feature *feature,558 unsigned long arg);559 560#endif /* __FPGA_DFL_H */561