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1// SPDX-License-Identifier: GPL-2.02/*3 * GPIO driver for AMD 8111 south bridges4 *5 * Copyright (c) 2012 Dmitry Eremin-Solenikov6 *7 * Based on the AMD RNG driver:8 * Copyright 2005 (c) MontaVista Software, Inc.9 * with the majority of the code coming from:10 *11 * Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)12 * (c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com>13 *14 * derived from15 *16 * Hardware driver for the AMD 768 Random Number Generator (RNG)17 * (c) Copyright 2001 Red Hat Inc18 *19 * derived from20 *21 * Hardware driver for Intel i810 Random Number Generator (RNG)22 * Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com>23 * Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com>24 */25#include <linux/ioport.h>26#include <linux/module.h>27#include <linux/kernel.h>28#include <linux/gpio/driver.h>29#include <linux/pci.h>30#include <linux/spinlock.h>31 32#define PMBASE_OFFSET 0xb033#define PMBASE_SIZE 0x3034 35#define AMD_REG_GPIO(i) (0x10 + (i))36 37#define AMD_GPIO_LTCH_STS 0x40 /* Latch status, w1 */38#define AMD_GPIO_RTIN 0x20 /* Real Time in, ro */39#define AMD_GPIO_DEBOUNCE 0x10 /* Debounce, rw */40#define AMD_GPIO_MODE_MASK 0x0c /* Pin Mode Select, rw */41#define AMD_GPIO_MODE_IN 0x0042#define AMD_GPIO_MODE_OUT 0x0443/* Enable alternative (e.g. clkout, IRQ, etc) function of the pin */44#define AMD_GPIO_MODE_ALTFN 0x08 /* Or 0x09 */45#define AMD_GPIO_X_MASK 0x03 /* In/Out specific, rw */46#define AMD_GPIO_X_IN_ACTIVEHI 0x01 /* Active High */47#define AMD_GPIO_X_IN_LATCH 0x02 /* Latched version is selected */48#define AMD_GPIO_X_OUT_LOW 0x0049#define AMD_GPIO_X_OUT_HI 0x0150#define AMD_GPIO_X_OUT_CLK0 0x0251#define AMD_GPIO_X_OUT_CLK1 0x0352 53/*54 * Data for PCI driver interface55 *56 * This data only exists for exporting the supported57 * PCI ids via MODULE_DEVICE_TABLE. We do not actually58 * register a pci_driver, because someone else might one day59 * want to register another driver on the same PCI id.60 */61static const struct pci_device_id pci_tbl[] = {62 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS), 0 },63 { 0, }, /* terminate list */64};65MODULE_DEVICE_TABLE(pci, pci_tbl);66 67struct amd_gpio {68 struct gpio_chip chip;69 u32 pmbase;70 void __iomem *pm;71 struct pci_dev *pdev;72 spinlock_t lock; /* guards hw registers and orig table */73 u8 orig[32];74};75 76static int amd_gpio_request(struct gpio_chip *chip, unsigned offset)77{78 struct amd_gpio *agp = gpiochip_get_data(chip);79 80 agp->orig[offset] = ioread8(agp->pm + AMD_REG_GPIO(offset)) &81 (AMD_GPIO_DEBOUNCE | AMD_GPIO_MODE_MASK | AMD_GPIO_X_MASK);82 83 dev_dbg(&agp->pdev->dev, "Requested gpio %d, data %x\n", offset, agp->orig[offset]);84 85 return 0;86}87 88static void amd_gpio_free(struct gpio_chip *chip, unsigned offset)89{90 struct amd_gpio *agp = gpiochip_get_data(chip);91 92 dev_dbg(&agp->pdev->dev, "Freed gpio %d, data %x\n", offset, agp->orig[offset]);93 94 iowrite8(agp->orig[offset], agp->pm + AMD_REG_GPIO(offset));95}96 97static void amd_gpio_set(struct gpio_chip *chip, unsigned offset, int value)98{99 struct amd_gpio *agp = gpiochip_get_data(chip);100 u8 temp;101 unsigned long flags;102 103 spin_lock_irqsave(&agp->lock, flags);104 temp = ioread8(agp->pm + AMD_REG_GPIO(offset));105 temp = (temp & AMD_GPIO_DEBOUNCE) | AMD_GPIO_MODE_OUT | (value ? AMD_GPIO_X_OUT_HI : AMD_GPIO_X_OUT_LOW);106 iowrite8(temp, agp->pm + AMD_REG_GPIO(offset));107 spin_unlock_irqrestore(&agp->lock, flags);108 109 dev_dbg(&agp->pdev->dev, "Setting gpio %d, value %d, reg=%02x\n", offset, !!value, temp);110}111 112static int amd_gpio_get(struct gpio_chip *chip, unsigned offset)113{114 struct amd_gpio *agp = gpiochip_get_data(chip);115 u8 temp;116 117 temp = ioread8(agp->pm + AMD_REG_GPIO(offset));118 119 dev_dbg(&agp->pdev->dev, "Getting gpio %d, reg=%02x\n", offset, temp);120 121 return (temp & AMD_GPIO_RTIN) ? 1 : 0;122}123 124static int amd_gpio_dirout(struct gpio_chip *chip, unsigned offset, int value)125{126 struct amd_gpio *agp = gpiochip_get_data(chip);127 u8 temp;128 unsigned long flags;129 130 spin_lock_irqsave(&agp->lock, flags);131 temp = ioread8(agp->pm + AMD_REG_GPIO(offset));132 temp = (temp & AMD_GPIO_DEBOUNCE) | AMD_GPIO_MODE_OUT | (value ? AMD_GPIO_X_OUT_HI : AMD_GPIO_X_OUT_LOW);133 iowrite8(temp, agp->pm + AMD_REG_GPIO(offset));134 spin_unlock_irqrestore(&agp->lock, flags);135 136 dev_dbg(&agp->pdev->dev, "Dirout gpio %d, value %d, reg=%02x\n", offset, !!value, temp);137 138 return 0;139}140 141static int amd_gpio_dirin(struct gpio_chip *chip, unsigned offset)142{143 struct amd_gpio *agp = gpiochip_get_data(chip);144 u8 temp;145 unsigned long flags;146 147 spin_lock_irqsave(&agp->lock, flags);148 temp = ioread8(agp->pm + AMD_REG_GPIO(offset));149 temp = (temp & AMD_GPIO_DEBOUNCE) | AMD_GPIO_MODE_IN;150 iowrite8(temp, agp->pm + AMD_REG_GPIO(offset));151 spin_unlock_irqrestore(&agp->lock, flags);152 153 dev_dbg(&agp->pdev->dev, "Dirin gpio %d, reg=%02x\n", offset, temp);154 155 return 0;156}157 158static struct amd_gpio gp = {159 .chip = {160 .label = "AMD GPIO",161 .owner = THIS_MODULE,162 .base = -1,163 .ngpio = 32,164 .request = amd_gpio_request,165 .free = amd_gpio_free,166 .set = amd_gpio_set,167 .get = amd_gpio_get,168 .direction_output = amd_gpio_dirout,169 .direction_input = amd_gpio_dirin,170 },171};172 173static int __init amd_gpio_init(void)174{175 int err = -ENODEV;176 struct pci_dev *pdev = NULL;177 const struct pci_device_id *ent;178 179 /* We look for our device - AMD South Bridge180 * I don't know about a system with two such bridges,181 * so we can assume that there is max. one device.182 *183 * We can't use plain pci_driver mechanism,184 * as the device is really a multiple function device,185 * main driver that binds to the pci_device is an smbus186 * driver and have to find & bind to the device this way.187 */188 for_each_pci_dev(pdev) {189 ent = pci_match_id(pci_tbl, pdev);190 if (ent)191 goto found;192 }193 /* Device not found. */194 goto out;195 196found:197 err = pci_read_config_dword(pdev, 0x58, &gp.pmbase);198 if (err) {199 err = pcibios_err_to_errno(err);200 goto out;201 }202 err = -EIO;203 gp.pmbase &= 0x0000FF00;204 if (gp.pmbase == 0)205 goto out;206 if (!devm_request_region(&pdev->dev, gp.pmbase + PMBASE_OFFSET,207 PMBASE_SIZE, "AMD GPIO")) {208 dev_err(&pdev->dev, "AMD GPIO region 0x%x already in use!\n",209 gp.pmbase + PMBASE_OFFSET);210 err = -EBUSY;211 goto out;212 }213 gp.pm = ioport_map(gp.pmbase + PMBASE_OFFSET, PMBASE_SIZE);214 if (!gp.pm) {215 dev_err(&pdev->dev, "Couldn't map io port into io memory\n");216 err = -ENOMEM;217 goto out;218 }219 gp.pdev = pdev;220 gp.chip.parent = &pdev->dev;221 222 spin_lock_init(&gp.lock);223 224 dev_info(&pdev->dev, "AMD-8111 GPIO detected\n");225 err = gpiochip_add_data(&gp.chip, &gp);226 if (err) {227 dev_err(&pdev->dev, "GPIO registering failed (%d)\n", err);228 ioport_unmap(gp.pm);229 goto out;230 }231 return 0;232 233out:234 pci_dev_put(pdev);235 return err;236}237 238static void __exit amd_gpio_exit(void)239{240 gpiochip_remove(&gp.chip);241 ioport_unmap(gp.pm);242 pci_dev_put(gp.pdev);243}244 245module_init(amd_gpio_init);246module_exit(amd_gpio_exit);247 248MODULE_AUTHOR("The Linux Kernel team");249MODULE_DESCRIPTION("GPIO driver for AMD chipsets");250MODULE_LICENSE("GPL");251