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1// SPDX-License-Identifier: GPL-2.02 3/*4 * Copyright 2017-2018 Cadence5 *6 * Authors:7 * Jan Kotas <jank@cadence.com>8 * Boris Brezillon <boris.brezillon@free-electrons.com>9 */10 11#include <linux/gpio/driver.h>12#include <linux/clk.h>13#include <linux/interrupt.h>14#include <linux/kernel.h>15#include <linux/module.h>16#include <linux/platform_device.h>17#include <linux/spinlock.h>18 19#define CDNS_GPIO_BYPASS_MODE 0x0020#define CDNS_GPIO_DIRECTION_MODE 0x0421#define CDNS_GPIO_OUTPUT_EN 0x0822#define CDNS_GPIO_OUTPUT_VALUE 0x0c23#define CDNS_GPIO_INPUT_VALUE 0x1024#define CDNS_GPIO_IRQ_MASK 0x1425#define CDNS_GPIO_IRQ_EN 0x1826#define CDNS_GPIO_IRQ_DIS 0x1c27#define CDNS_GPIO_IRQ_STATUS 0x2028#define CDNS_GPIO_IRQ_TYPE 0x2429#define CDNS_GPIO_IRQ_VALUE 0x2830#define CDNS_GPIO_IRQ_ANY_EDGE 0x2c31 32struct cdns_gpio_chip {33 struct gpio_chip gc;34 void __iomem *regs;35 u32 bypass_orig;36};37 38static int cdns_gpio_request(struct gpio_chip *chip, unsigned int offset)39{40 struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);41 unsigned long flags;42 43 raw_spin_lock_irqsave(&chip->bgpio_lock, flags);44 45 iowrite32(ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE) & ~BIT(offset),46 cgpio->regs + CDNS_GPIO_BYPASS_MODE);47 48 raw_spin_unlock_irqrestore(&chip->bgpio_lock, flags);49 return 0;50}51 52static void cdns_gpio_free(struct gpio_chip *chip, unsigned int offset)53{54 struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);55 unsigned long flags;56 57 raw_spin_lock_irqsave(&chip->bgpio_lock, flags);58 59 iowrite32(ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE) |60 (BIT(offset) & cgpio->bypass_orig),61 cgpio->regs + CDNS_GPIO_BYPASS_MODE);62 63 raw_spin_unlock_irqrestore(&chip->bgpio_lock, flags);64}65 66static void cdns_gpio_irq_mask(struct irq_data *d)67{68 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);69 struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);70 71 iowrite32(BIT(d->hwirq), cgpio->regs + CDNS_GPIO_IRQ_DIS);72 gpiochip_disable_irq(chip, irqd_to_hwirq(d));73}74 75static void cdns_gpio_irq_unmask(struct irq_data *d)76{77 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);78 struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);79 80 gpiochip_enable_irq(chip, irqd_to_hwirq(d));81 iowrite32(BIT(d->hwirq), cgpio->regs + CDNS_GPIO_IRQ_EN);82}83 84static int cdns_gpio_irq_set_type(struct irq_data *d, unsigned int type)85{86 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);87 struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);88 unsigned long flags;89 u32 int_value;90 u32 int_type;91 u32 mask = BIT(d->hwirq);92 int ret = 0;93 94 raw_spin_lock_irqsave(&chip->bgpio_lock, flags);95 96 int_value = ioread32(cgpio->regs + CDNS_GPIO_IRQ_VALUE) & ~mask;97 int_type = ioread32(cgpio->regs + CDNS_GPIO_IRQ_TYPE) & ~mask;98 99 /*100 * The GPIO controller doesn't have an ACK register.101 * All interrupt statuses are cleared on a status register read.102 * Don't support edge interrupts for now.103 */104 105 if (type == IRQ_TYPE_LEVEL_HIGH) {106 int_type |= mask;107 int_value |= mask;108 } else if (type == IRQ_TYPE_LEVEL_LOW) {109 int_type |= mask;110 } else {111 ret = -EINVAL;112 goto err_irq_type;113 }114 115 iowrite32(int_value, cgpio->regs + CDNS_GPIO_IRQ_VALUE);116 iowrite32(int_type, cgpio->regs + CDNS_GPIO_IRQ_TYPE);117 118err_irq_type:119 raw_spin_unlock_irqrestore(&chip->bgpio_lock, flags);120 return ret;121}122 123static void cdns_gpio_irq_handler(struct irq_desc *desc)124{125 struct gpio_chip *chip = irq_desc_get_handler_data(desc);126 struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);127 struct irq_chip *irqchip = irq_desc_get_chip(desc);128 unsigned long status;129 int hwirq;130 131 chained_irq_enter(irqchip, desc);132 133 status = ioread32(cgpio->regs + CDNS_GPIO_IRQ_STATUS) &134 ~ioread32(cgpio->regs + CDNS_GPIO_IRQ_MASK);135 136 for_each_set_bit(hwirq, &status, chip->ngpio)137 generic_handle_domain_irq(chip->irq.domain, hwirq);138 139 chained_irq_exit(irqchip, desc);140}141 142static const struct irq_chip cdns_gpio_irqchip = {143 .name = "cdns-gpio",144 .irq_mask = cdns_gpio_irq_mask,145 .irq_unmask = cdns_gpio_irq_unmask,146 .irq_set_type = cdns_gpio_irq_set_type,147 .flags = IRQCHIP_IMMUTABLE,148 GPIOCHIP_IRQ_RESOURCE_HELPERS,149};150 151static int cdns_gpio_probe(struct platform_device *pdev)152{153 struct cdns_gpio_chip *cgpio;154 int ret, irq;155 u32 dir_prev;156 u32 num_gpios = 32;157 struct clk *clk;158 159 cgpio = devm_kzalloc(&pdev->dev, sizeof(*cgpio), GFP_KERNEL);160 if (!cgpio)161 return -ENOMEM;162 163 cgpio->regs = devm_platform_ioremap_resource(pdev, 0);164 if (IS_ERR(cgpio->regs))165 return PTR_ERR(cgpio->regs);166 167 of_property_read_u32(pdev->dev.of_node, "ngpios", &num_gpios);168 169 if (num_gpios > 32) {170 dev_err(&pdev->dev, "ngpios must be less or equal 32\n");171 return -EINVAL;172 }173 174 /*175 * Set all pins as inputs by default, otherwise:176 * gpiochip_lock_as_irq:177 * tried to flag a GPIO set as output for IRQ178 * Generic GPIO driver stores the direction value internally,179 * so it needs to be changed before bgpio_init() is called.180 */181 dir_prev = ioread32(cgpio->regs + CDNS_GPIO_DIRECTION_MODE);182 iowrite32(GENMASK(num_gpios - 1, 0),183 cgpio->regs + CDNS_GPIO_DIRECTION_MODE);184 185 ret = bgpio_init(&cgpio->gc, &pdev->dev, 4,186 cgpio->regs + CDNS_GPIO_INPUT_VALUE,187 cgpio->regs + CDNS_GPIO_OUTPUT_VALUE,188 NULL,189 NULL,190 cgpio->regs + CDNS_GPIO_DIRECTION_MODE,191 BGPIOF_READ_OUTPUT_REG_SET);192 if (ret) {193 dev_err(&pdev->dev, "Failed to register generic gpio, %d\n",194 ret);195 goto err_revert_dir;196 }197 198 cgpio->gc.label = dev_name(&pdev->dev);199 cgpio->gc.ngpio = num_gpios;200 cgpio->gc.parent = &pdev->dev;201 cgpio->gc.base = -1;202 cgpio->gc.owner = THIS_MODULE;203 cgpio->gc.request = cdns_gpio_request;204 cgpio->gc.free = cdns_gpio_free;205 206 clk = devm_clk_get_enabled(&pdev->dev, NULL);207 if (IS_ERR(clk)) {208 ret = PTR_ERR(clk);209 dev_err(&pdev->dev,210 "Failed to retrieve peripheral clock, %d\n", ret);211 goto err_revert_dir;212 }213 214 /*215 * Optional irq_chip support216 */217 irq = platform_get_irq(pdev, 0);218 if (irq >= 0) {219 struct gpio_irq_chip *girq;220 221 girq = &cgpio->gc.irq;222 gpio_irq_chip_set_chip(girq, &cdns_gpio_irqchip);223 girq->parent_handler = cdns_gpio_irq_handler;224 girq->num_parents = 1;225 girq->parents = devm_kcalloc(&pdev->dev, 1,226 sizeof(*girq->parents),227 GFP_KERNEL);228 if (!girq->parents) {229 ret = -ENOMEM;230 goto err_revert_dir;231 }232 girq->parents[0] = irq;233 girq->default_type = IRQ_TYPE_NONE;234 girq->handler = handle_level_irq;235 }236 237 ret = devm_gpiochip_add_data(&pdev->dev, &cgpio->gc, cgpio);238 if (ret < 0) {239 dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret);240 goto err_revert_dir;241 }242 243 cgpio->bypass_orig = ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE);244 245 /*246 * Enable gpio outputs, ignored for input direction247 */248 iowrite32(GENMASK(num_gpios - 1, 0),249 cgpio->regs + CDNS_GPIO_OUTPUT_EN);250 iowrite32(0, cgpio->regs + CDNS_GPIO_BYPASS_MODE);251 252 platform_set_drvdata(pdev, cgpio);253 return 0;254 255err_revert_dir:256 iowrite32(dir_prev, cgpio->regs + CDNS_GPIO_DIRECTION_MODE);257 258 return ret;259}260 261static void cdns_gpio_remove(struct platform_device *pdev)262{263 struct cdns_gpio_chip *cgpio = platform_get_drvdata(pdev);264 265 iowrite32(cgpio->bypass_orig, cgpio->regs + CDNS_GPIO_BYPASS_MODE);266}267 268static const struct of_device_id cdns_of_ids[] = {269 { .compatible = "cdns,gpio-r1p02" },270 { /* sentinel */ },271};272MODULE_DEVICE_TABLE(of, cdns_of_ids);273 274static struct platform_driver cdns_gpio_driver = {275 .driver = {276 .name = "cdns-gpio",277 .of_match_table = cdns_of_ids,278 },279 .probe = cdns_gpio_probe,280 .remove_new = cdns_gpio_remove,281};282module_platform_driver(cdns_gpio_driver);283 284MODULE_AUTHOR("Jan Kotas <jank@cadence.com>");285MODULE_DESCRIPTION("Cadence GPIO driver");286MODULE_LICENSE("GPL v2");287MODULE_ALIAS("platform:cdns-gpio");288