857 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2011 Jamie Iles4 *5 * All enquiries to support@picochip.com6 */7#include <linux/acpi.h>8#include <linux/clk.h>9#include <linux/err.h>10#include <linux/gpio/driver.h>11#include <linux/init.h>12#include <linux/interrupt.h>13#include <linux/io.h>14#include <linux/ioport.h>15#include <linux/irq.h>16#include <linux/mod_devicetable.h>17#include <linux/module.h>18#include <linux/platform_device.h>19#include <linux/property.h>20#include <linux/reset.h>21#include <linux/slab.h>22#include <linux/spinlock.h>23 24#include "gpiolib-acpi.h"25 26#define GPIO_SWPORTA_DR 0x0027#define GPIO_SWPORTA_DDR 0x0428#define GPIO_SWPORTB_DR 0x0c29#define GPIO_SWPORTB_DDR 0x1030#define GPIO_SWPORTC_DR 0x1831#define GPIO_SWPORTC_DDR 0x1c32#define GPIO_SWPORTD_DR 0x2433#define GPIO_SWPORTD_DDR 0x2834#define GPIO_INTEN 0x3035#define GPIO_INTMASK 0x3436#define GPIO_INTTYPE_LEVEL 0x3837#define GPIO_INT_POLARITY 0x3c38#define GPIO_INTSTATUS 0x4039#define GPIO_PORTA_DEBOUNCE 0x4840#define GPIO_PORTA_EOI 0x4c41#define GPIO_EXT_PORTA 0x5042#define GPIO_EXT_PORTB 0x5443#define GPIO_EXT_PORTC 0x5844#define GPIO_EXT_PORTD 0x5c45 46#define DWAPB_DRIVER_NAME "gpio-dwapb"47#define DWAPB_MAX_PORTS 448#define DWAPB_MAX_GPIOS 3249 50#define GPIO_EXT_PORT_STRIDE 0x04 /* register stride 32 bits */51#define GPIO_SWPORT_DR_STRIDE 0x0c /* register stride 3*32 bits */52#define GPIO_SWPORT_DDR_STRIDE 0x0c /* register stride 3*32 bits */53 54#define GPIO_REG_OFFSET_V1 055#define GPIO_REG_OFFSET_V2 156#define GPIO_REG_OFFSET_MASK BIT(0)57 58#define GPIO_INTMASK_V2 0x4459#define GPIO_INTTYPE_LEVEL_V2 0x3460#define GPIO_INT_POLARITY_V2 0x3861#define GPIO_INTSTATUS_V2 0x3c62#define GPIO_PORTA_EOI_V2 0x4063 64#define DWAPB_NR_CLOCKS 265 66struct dwapb_gpio;67 68struct dwapb_port_property {69 struct fwnode_handle *fwnode;70 unsigned int idx;71 unsigned int ngpio;72 unsigned int gpio_base;73 int irq[DWAPB_MAX_GPIOS];74};75 76struct dwapb_platform_data {77 struct dwapb_port_property *properties;78 unsigned int nports;79};80 81#ifdef CONFIG_PM_SLEEP82/* Store GPIO context across system-wide suspend/resume transitions */83struct dwapb_context {84 u32 data;85 u32 dir;86 u32 ext;87 u32 int_en;88 u32 int_mask;89 u32 int_type;90 u32 int_pol;91 u32 int_deb;92 u32 wake_en;93};94#endif95 96struct dwapb_gpio_port_irqchip {97 unsigned int nr_irqs;98 unsigned int irq[DWAPB_MAX_GPIOS];99};100 101struct dwapb_gpio_port {102 struct gpio_chip gc;103 struct dwapb_gpio_port_irqchip *pirq;104 struct dwapb_gpio *gpio;105#ifdef CONFIG_PM_SLEEP106 struct dwapb_context *ctx;107#endif108 unsigned int idx;109};110#define to_dwapb_gpio(_gc) \111 (container_of(_gc, struct dwapb_gpio_port, gc)->gpio)112 113struct dwapb_gpio {114 struct device *dev;115 void __iomem *regs;116 struct dwapb_gpio_port *ports;117 unsigned int nr_ports;118 unsigned int flags;119 struct reset_control *rst;120 struct clk_bulk_data clks[DWAPB_NR_CLOCKS];121};122 123static inline u32 gpio_reg_v2_convert(unsigned int offset)124{125 switch (offset) {126 case GPIO_INTMASK:127 return GPIO_INTMASK_V2;128 case GPIO_INTTYPE_LEVEL:129 return GPIO_INTTYPE_LEVEL_V2;130 case GPIO_INT_POLARITY:131 return GPIO_INT_POLARITY_V2;132 case GPIO_INTSTATUS:133 return GPIO_INTSTATUS_V2;134 case GPIO_PORTA_EOI:135 return GPIO_PORTA_EOI_V2;136 }137 138 return offset;139}140 141static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)142{143 if ((gpio->flags & GPIO_REG_OFFSET_MASK) == GPIO_REG_OFFSET_V2)144 return gpio_reg_v2_convert(offset);145 146 return offset;147}148 149static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)150{151 struct gpio_chip *gc = &gpio->ports[0].gc;152 void __iomem *reg_base = gpio->regs;153 154 return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset));155}156 157static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,158 u32 val)159{160 struct gpio_chip *gc = &gpio->ports[0].gc;161 void __iomem *reg_base = gpio->regs;162 163 gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val);164}165 166static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs)167{168 struct dwapb_gpio_port *port;169 int i;170 171 for (i = 0; i < gpio->nr_ports; i++) {172 port = &gpio->ports[i];173 if (port->idx == offs / DWAPB_MAX_GPIOS)174 return port;175 }176 177 return NULL;178}179 180static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)181{182 struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs);183 struct gpio_chip *gc;184 u32 pol;185 int val;186 187 if (!port)188 return;189 gc = &port->gc;190 191 pol = dwapb_read(gpio, GPIO_INT_POLARITY);192 /* Just read the current value right out of the data register */193 val = gc->get(gc, offs % DWAPB_MAX_GPIOS);194 if (val)195 pol &= ~BIT(offs);196 else197 pol |= BIT(offs);198 199 dwapb_write(gpio, GPIO_INT_POLARITY, pol);200}201 202static u32 dwapb_do_irq(struct dwapb_gpio *gpio)203{204 struct gpio_chip *gc = &gpio->ports[0].gc;205 unsigned long irq_status;206 irq_hw_number_t hwirq;207 208 irq_status = dwapb_read(gpio, GPIO_INTSTATUS);209 for_each_set_bit(hwirq, &irq_status, DWAPB_MAX_GPIOS) {210 int gpio_irq = irq_find_mapping(gc->irq.domain, hwirq);211 u32 irq_type = irq_get_trigger_type(gpio_irq);212 213 generic_handle_irq(gpio_irq);214 215 if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)216 dwapb_toggle_trigger(gpio, hwirq);217 }218 219 return irq_status;220}221 222static void dwapb_irq_handler(struct irq_desc *desc)223{224 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);225 struct irq_chip *chip = irq_desc_get_chip(desc);226 227 chained_irq_enter(chip, desc);228 dwapb_do_irq(gpio);229 chained_irq_exit(chip, desc);230}231 232static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)233{234 return IRQ_RETVAL(dwapb_do_irq(dev_id));235}236 237static void dwapb_irq_ack(struct irq_data *d)238{239 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);240 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);241 u32 val = BIT(irqd_to_hwirq(d));242 unsigned long flags;243 244 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);245 dwapb_write(gpio, GPIO_PORTA_EOI, val);246 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);247}248 249static void dwapb_irq_mask(struct irq_data *d)250{251 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);252 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);253 irq_hw_number_t hwirq = irqd_to_hwirq(d);254 unsigned long flags;255 u32 val;256 257 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);258 val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq);259 dwapb_write(gpio, GPIO_INTMASK, val);260 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);261 262 gpiochip_disable_irq(gc, hwirq);263}264 265static void dwapb_irq_unmask(struct irq_data *d)266{267 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);268 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);269 irq_hw_number_t hwirq = irqd_to_hwirq(d);270 unsigned long flags;271 u32 val;272 273 gpiochip_enable_irq(gc, hwirq);274 275 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);276 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq);277 dwapb_write(gpio, GPIO_INTMASK, val);278 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);279}280 281static void dwapb_irq_enable(struct irq_data *d)282{283 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);284 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);285 irq_hw_number_t hwirq = irqd_to_hwirq(d);286 unsigned long flags;287 u32 val;288 289 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);290 val = dwapb_read(gpio, GPIO_INTEN) | BIT(hwirq);291 dwapb_write(gpio, GPIO_INTEN, val);292 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq);293 dwapb_write(gpio, GPIO_INTMASK, val);294 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);295}296 297static void dwapb_irq_disable(struct irq_data *d)298{299 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);300 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);301 irq_hw_number_t hwirq = irqd_to_hwirq(d);302 unsigned long flags;303 u32 val;304 305 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);306 val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq);307 dwapb_write(gpio, GPIO_INTMASK, val);308 val = dwapb_read(gpio, GPIO_INTEN) & ~BIT(hwirq);309 dwapb_write(gpio, GPIO_INTEN, val);310 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);311}312 313static int dwapb_irq_set_type(struct irq_data *d, u32 type)314{315 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);316 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);317 irq_hw_number_t bit = irqd_to_hwirq(d);318 unsigned long level, polarity, flags;319 320 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);321 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);322 polarity = dwapb_read(gpio, GPIO_INT_POLARITY);323 324 switch (type) {325 case IRQ_TYPE_EDGE_BOTH:326 level |= BIT(bit);327 dwapb_toggle_trigger(gpio, bit);328 break;329 case IRQ_TYPE_EDGE_RISING:330 level |= BIT(bit);331 polarity |= BIT(bit);332 break;333 case IRQ_TYPE_EDGE_FALLING:334 level |= BIT(bit);335 polarity &= ~BIT(bit);336 break;337 case IRQ_TYPE_LEVEL_HIGH:338 level &= ~BIT(bit);339 polarity |= BIT(bit);340 break;341 case IRQ_TYPE_LEVEL_LOW:342 level &= ~BIT(bit);343 polarity &= ~BIT(bit);344 break;345 }346 347 if (type & IRQ_TYPE_LEVEL_MASK)348 irq_set_handler_locked(d, handle_level_irq);349 else if (type & IRQ_TYPE_EDGE_BOTH)350 irq_set_handler_locked(d, handle_edge_irq);351 352 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);353 if (type != IRQ_TYPE_EDGE_BOTH)354 dwapb_write(gpio, GPIO_INT_POLARITY, polarity);355 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);356 357 return 0;358}359 360#ifdef CONFIG_PM_SLEEP361static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable)362{363 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);364 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);365 struct dwapb_context *ctx = gpio->ports[0].ctx;366 irq_hw_number_t bit = irqd_to_hwirq(d);367 368 if (enable)369 ctx->wake_en |= BIT(bit);370 else371 ctx->wake_en &= ~BIT(bit);372 373 return 0;374}375#else376#define dwapb_irq_set_wake NULL377#endif378 379static const struct irq_chip dwapb_irq_chip = {380 .name = DWAPB_DRIVER_NAME,381 .irq_ack = dwapb_irq_ack,382 .irq_mask = dwapb_irq_mask,383 .irq_unmask = dwapb_irq_unmask,384 .irq_set_type = dwapb_irq_set_type,385 .irq_enable = dwapb_irq_enable,386 .irq_disable = dwapb_irq_disable,387 .irq_set_wake = dwapb_irq_set_wake,388 .flags = IRQCHIP_IMMUTABLE,389 GPIOCHIP_IRQ_RESOURCE_HELPERS,390};391 392static int dwapb_gpio_set_debounce(struct gpio_chip *gc,393 unsigned offset, unsigned debounce)394{395 struct dwapb_gpio_port *port = gpiochip_get_data(gc);396 struct dwapb_gpio *gpio = port->gpio;397 unsigned long flags, val_deb;398 unsigned long mask = BIT(offset);399 400 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);401 402 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);403 if (debounce)404 val_deb |= mask;405 else406 val_deb &= ~mask;407 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb);408 409 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);410 411 return 0;412}413 414static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset,415 unsigned long config)416{417 u32 debounce;418 419 if (pinconf_to_config_param(config) == PIN_CONFIG_INPUT_DEBOUNCE) {420 debounce = pinconf_to_config_argument(config);421 return dwapb_gpio_set_debounce(gc, offset, debounce);422 }423 424 return gpiochip_generic_config(gc, offset, config);425}426 427static int dwapb_convert_irqs(struct dwapb_gpio_port_irqchip *pirq,428 struct dwapb_port_property *pp)429{430 int i;431 432 /* Group all available IRQs into an array of parental IRQs. */433 for (i = 0; i < pp->ngpio; ++i) {434 if (!pp->irq[i])435 continue;436 437 pirq->irq[pirq->nr_irqs++] = pp->irq[i];438 }439 440 return pirq->nr_irqs ? 0 : -ENOENT;441}442 443static void dwapb_configure_irqs(struct dwapb_gpio *gpio,444 struct dwapb_gpio_port *port,445 struct dwapb_port_property *pp)446{447 struct dwapb_gpio_port_irqchip *pirq;448 struct gpio_chip *gc = &port->gc;449 struct gpio_irq_chip *girq;450 int err;451 452 pirq = devm_kzalloc(gpio->dev, sizeof(*pirq), GFP_KERNEL);453 if (!pirq)454 return;455 456 if (dwapb_convert_irqs(pirq, pp)) {457 dev_warn(gpio->dev, "no IRQ for port%d\n", pp->idx);458 goto err_kfree_pirq;459 }460 461 girq = &gc->irq;462 girq->handler = handle_bad_irq;463 girq->default_type = IRQ_TYPE_NONE;464 465 port->pirq = pirq;466 467 /*468 * Intel ACPI-based platforms mostly have the DesignWare APB GPIO469 * IRQ lane shared between several devices. In that case the parental470 * IRQ has to be handled in the shared way so to be properly delivered471 * to all the connected devices.472 */473 if (has_acpi_companion(gpio->dev)) {474 girq->num_parents = 0;475 girq->parents = NULL;476 girq->parent_handler = NULL;477 478 err = devm_request_irq(gpio->dev, pp->irq[0],479 dwapb_irq_handler_mfd,480 IRQF_SHARED, DWAPB_DRIVER_NAME, gpio);481 if (err) {482 dev_err(gpio->dev, "error requesting IRQ\n");483 goto err_kfree_pirq;484 }485 } else {486 girq->num_parents = pirq->nr_irqs;487 girq->parents = pirq->irq;488 girq->parent_handler_data = gpio;489 girq->parent_handler = dwapb_irq_handler;490 }491 492 gpio_irq_chip_set_chip(girq, &dwapb_irq_chip);493 494 return;495 496err_kfree_pirq:497 devm_kfree(gpio->dev, pirq);498}499 500static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,501 struct dwapb_port_property *pp,502 unsigned int offs)503{504 struct dwapb_gpio_port *port;505 void __iomem *dat, *set, *dirout;506 int err;507 508 port = &gpio->ports[offs];509 port->gpio = gpio;510 port->idx = pp->idx;511 512#ifdef CONFIG_PM_SLEEP513 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);514 if (!port->ctx)515 return -ENOMEM;516#endif517 518 dat = gpio->regs + GPIO_EXT_PORTA + pp->idx * GPIO_EXT_PORT_STRIDE;519 set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE;520 dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE;521 522 /* This registers 32 GPIO lines per port */523 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,524 NULL, 0);525 if (err) {526 dev_err(gpio->dev, "failed to init gpio chip for port%d\n",527 port->idx);528 return err;529 }530 531 port->gc.fwnode = pp->fwnode;532 port->gc.ngpio = pp->ngpio;533 port->gc.base = pp->gpio_base;534 port->gc.request = gpiochip_generic_request;535 port->gc.free = gpiochip_generic_free;536 537 /* Only port A support debounce */538 if (pp->idx == 0)539 port->gc.set_config = dwapb_gpio_set_config;540 else541 port->gc.set_config = gpiochip_generic_config;542 543 /* Only port A can provide interrupts in all configurations of the IP */544 if (pp->idx == 0)545 dwapb_configure_irqs(gpio, port, pp);546 547 err = devm_gpiochip_add_data(gpio->dev, &port->gc, port);548 if (err) {549 dev_err(gpio->dev, "failed to register gpiochip for port%d\n",550 port->idx);551 return err;552 }553 554 return 0;555}556 557static void dwapb_get_irq(struct device *dev, struct fwnode_handle *fwnode,558 struct dwapb_port_property *pp)559{560 int irq, j;561 562 for (j = 0; j < pp->ngpio; j++) {563 if (has_acpi_companion(dev))564 irq = platform_get_irq_optional(to_platform_device(dev), j);565 else566 irq = fwnode_irq_get(fwnode, j);567 if (irq > 0)568 pp->irq[j] = irq;569 }570}571 572static struct dwapb_platform_data *dwapb_gpio_get_pdata(struct device *dev)573{574 struct fwnode_handle *fwnode;575 struct dwapb_platform_data *pdata;576 struct dwapb_port_property *pp;577 int nports;578 int i;579 580 nports = device_get_child_node_count(dev);581 if (nports == 0)582 return ERR_PTR(-ENODEV);583 584 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);585 if (!pdata)586 return ERR_PTR(-ENOMEM);587 588 pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);589 if (!pdata->properties)590 return ERR_PTR(-ENOMEM);591 592 pdata->nports = nports;593 594 i = 0;595 device_for_each_child_node(dev, fwnode) {596 pp = &pdata->properties[i++];597 pp->fwnode = fwnode;598 599 if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) ||600 pp->idx >= DWAPB_MAX_PORTS) {601 dev_err(dev,602 "missing/invalid port index for port%d\n", i);603 fwnode_handle_put(fwnode);604 return ERR_PTR(-EINVAL);605 }606 607 if (fwnode_property_read_u32(fwnode, "ngpios", &pp->ngpio) &&608 fwnode_property_read_u32(fwnode, "snps,nr-gpios", &pp->ngpio)) {609 dev_info(dev,610 "failed to get number of gpios for port%d\n",611 i);612 pp->ngpio = DWAPB_MAX_GPIOS;613 }614 615 pp->gpio_base = -1;616 617 /* For internal use only, new platforms mustn't exercise this */618 if (is_software_node(fwnode))619 fwnode_property_read_u32(fwnode, "gpio-base", &pp->gpio_base);620 621 /*622 * Only port A can provide interrupts in all configurations of623 * the IP.624 */625 if (pp->idx == 0)626 dwapb_get_irq(dev, fwnode, pp);627 }628 629 return pdata;630}631 632static void dwapb_assert_reset(void *data)633{634 struct dwapb_gpio *gpio = data;635 636 reset_control_assert(gpio->rst);637}638 639static int dwapb_get_reset(struct dwapb_gpio *gpio)640{641 int err;642 643 gpio->rst = devm_reset_control_get_optional_shared(gpio->dev, NULL);644 if (IS_ERR(gpio->rst))645 return dev_err_probe(gpio->dev, PTR_ERR(gpio->rst),646 "Cannot get reset descriptor\n");647 648 err = reset_control_deassert(gpio->rst);649 if (err) {650 dev_err(gpio->dev, "Cannot deassert reset lane\n");651 return err;652 }653 654 return devm_add_action_or_reset(gpio->dev, dwapb_assert_reset, gpio);655}656 657static void dwapb_disable_clks(void *data)658{659 struct dwapb_gpio *gpio = data;660 661 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);662}663 664static int dwapb_get_clks(struct dwapb_gpio *gpio)665{666 int err;667 668 /* Optional bus and debounce clocks */669 gpio->clks[0].id = "bus";670 gpio->clks[1].id = "db";671 err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS,672 gpio->clks);673 if (err)674 return dev_err_probe(gpio->dev, err,675 "Cannot get APB/Debounce clocks\n");676 677 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);678 if (err) {679 dev_err(gpio->dev, "Cannot enable APB/Debounce clocks\n");680 return err;681 }682 683 return devm_add_action_or_reset(gpio->dev, dwapb_disable_clks, gpio);684}685 686static const struct of_device_id dwapb_of_match[] = {687 { .compatible = "snps,dw-apb-gpio", .data = (void *)GPIO_REG_OFFSET_V1},688 { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},689 { /* Sentinel */ }690};691MODULE_DEVICE_TABLE(of, dwapb_of_match);692 693static const struct acpi_device_id dwapb_acpi_match[] = {694 {"HISI0181", GPIO_REG_OFFSET_V1},695 {"APMC0D07", GPIO_REG_OFFSET_V1},696 {"APMC0D81", GPIO_REG_OFFSET_V2},697 { }698};699MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match);700 701static int dwapb_gpio_probe(struct platform_device *pdev)702{703 unsigned int i;704 struct dwapb_gpio *gpio;705 int err;706 struct dwapb_platform_data *pdata;707 struct device *dev = &pdev->dev;708 709 pdata = dwapb_gpio_get_pdata(dev);710 if (IS_ERR(pdata))711 return PTR_ERR(pdata);712 713 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);714 if (!gpio)715 return -ENOMEM;716 717 gpio->dev = &pdev->dev;718 gpio->nr_ports = pdata->nports;719 720 err = dwapb_get_reset(gpio);721 if (err)722 return err;723 724 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,725 sizeof(*gpio->ports), GFP_KERNEL);726 if (!gpio->ports)727 return -ENOMEM;728 729 gpio->regs = devm_platform_ioremap_resource(pdev, 0);730 if (IS_ERR(gpio->regs))731 return PTR_ERR(gpio->regs);732 733 err = dwapb_get_clks(gpio);734 if (err)735 return err;736 737 gpio->flags = (uintptr_t)device_get_match_data(dev);738 739 for (i = 0; i < gpio->nr_ports; i++) {740 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);741 if (err)742 return err;743 }744 745 platform_set_drvdata(pdev, gpio);746 747 return 0;748}749 750#ifdef CONFIG_PM_SLEEP751static int dwapb_gpio_suspend(struct device *dev)752{753 struct dwapb_gpio *gpio = dev_get_drvdata(dev);754 struct gpio_chip *gc = &gpio->ports[0].gc;755 unsigned long flags;756 int i;757 758 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);759 for (i = 0; i < gpio->nr_ports; i++) {760 unsigned int offset;761 unsigned int idx = gpio->ports[i].idx;762 struct dwapb_context *ctx = gpio->ports[i].ctx;763 764 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;765 ctx->dir = dwapb_read(gpio, offset);766 767 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;768 ctx->data = dwapb_read(gpio, offset);769 770 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;771 ctx->ext = dwapb_read(gpio, offset);772 773 /* Only port A can provide interrupts */774 if (idx == 0) {775 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);776 ctx->int_en = dwapb_read(gpio, GPIO_INTEN);777 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);778 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);779 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);780 781 /* Mask out interrupts */782 dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en);783 }784 }785 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);786 787 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);788 789 return 0;790}791 792static int dwapb_gpio_resume(struct device *dev)793{794 struct dwapb_gpio *gpio = dev_get_drvdata(dev);795 struct gpio_chip *gc = &gpio->ports[0].gc;796 unsigned long flags;797 int i, err;798 799 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);800 if (err) {801 dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n");802 return err;803 }804 805 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);806 for (i = 0; i < gpio->nr_ports; i++) {807 unsigned int offset;808 unsigned int idx = gpio->ports[i].idx;809 struct dwapb_context *ctx = gpio->ports[i].ctx;810 811 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;812 dwapb_write(gpio, offset, ctx->data);813 814 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;815 dwapb_write(gpio, offset, ctx->dir);816 817 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;818 dwapb_write(gpio, offset, ctx->ext);819 820 /* Only port A can provide interrupts */821 if (idx == 0) {822 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);823 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);824 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);825 dwapb_write(gpio, GPIO_INTEN, ctx->int_en);826 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);827 828 /* Clear out spurious interrupts */829 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);830 }831 }832 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);833 834 return 0;835}836#endif837 838static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,839 dwapb_gpio_resume);840 841static struct platform_driver dwapb_gpio_driver = {842 .driver = {843 .name = DWAPB_DRIVER_NAME,844 .pm = &dwapb_gpio_pm_ops,845 .of_match_table = dwapb_of_match,846 .acpi_match_table = dwapb_acpi_match,847 },848 .probe = dwapb_gpio_probe,849};850 851module_platform_driver(dwapb_gpio_driver);852 853MODULE_LICENSE("GPL");854MODULE_AUTHOR("Jamie Iles");855MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");856MODULE_ALIAS("platform:" DWAPB_DRIVER_NAME);857