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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * PCA953x 4/8/16/24/40 bit I/O ports4 *5 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>6 * Copyright (C) 2007 Marvell International Ltd.7 *8 * Derived from drivers/i2c/chips/pca9539.c9 */10 11#include <linux/atomic.h>12#include <linux/bitmap.h>13#include <linux/cleanup.h>14#include <linux/device.h>15#include <linux/errno.h>16#include <linux/i2c.h>17#include <linux/init.h>18#include <linux/interrupt.h>19#include <linux/irq.h>20#include <linux/mod_devicetable.h>21#include <linux/module.h>22#include <linux/mutex.h>23#include <linux/pm.h>24#include <linux/regmap.h>25#include <linux/regulator/consumer.h>26#include <linux/seq_file.h>27#include <linux/slab.h>28 29#include <linux/gpio/consumer.h>30#include <linux/gpio/driver.h>31 32#include <linux/pinctrl/pinconf-generic.h>33 34#include <linux/platform_data/pca953x.h>35 36#define PCA953X_INPUT 0x0037#define PCA953X_OUTPUT 0x0138#define PCA953X_INVERT 0x0239#define PCA953X_DIRECTION 0x0340 41#define REG_ADDR_MASK GENMASK(5, 0)42#define REG_ADDR_EXT BIT(6)43#define REG_ADDR_AI BIT(7)44 45#define PCA957X_IN 0x0046#define PCA957X_INVRT 0x0147#define PCA957X_BKEN 0x0248#define PCA957X_PUPD 0x0349#define PCA957X_CFG 0x0450#define PCA957X_OUT 0x0551#define PCA957X_MSK 0x0652#define PCA957X_INTS 0x0753 54#define PCAL953X_OUT_STRENGTH 0x2055#define PCAL953X_IN_LATCH 0x2256#define PCAL953X_PULL_EN 0x2357#define PCAL953X_PULL_SEL 0x2458#define PCAL953X_INT_MASK 0x2559#define PCAL953X_INT_STAT 0x2660#define PCAL953X_OUT_CONF 0x2761 62#define PCAL6524_INT_EDGE 0x2863#define PCAL6524_INT_CLR 0x2a64#define PCAL6524_IN_STATUS 0x2b65#define PCAL6524_OUT_INDCONF 0x2c66#define PCAL6524_DEBOUNCE 0x2d67 68#define PCA_GPIO_MASK GENMASK(7, 0)69 70#define PCAL_GPIO_MASK GENMASK(4, 0)71#define PCAL_PINCTRL_MASK GENMASK(6, 5)72 73#define PCA_INT BIT(8)74#define PCA_PCAL BIT(9)75#define PCA_LATCH_INT (PCA_PCAL | PCA_INT)76#define PCA953X_TYPE BIT(12)77#define PCA957X_TYPE BIT(13)78#define PCAL653X_TYPE BIT(14)79#define PCA_TYPE_MASK GENMASK(15, 12)80 81#define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)82 83static const struct i2c_device_id pca953x_id[] = {84 { "pca6408", 8 | PCA953X_TYPE | PCA_INT, },85 { "pca6416", 16 | PCA953X_TYPE | PCA_INT, },86 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },87 { "pca9506", 40 | PCA953X_TYPE | PCA_INT, },88 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },89 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },90 { "pca9536", 4 | PCA953X_TYPE, },91 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },92 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },93 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },94 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },95 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },96 { "pca9556", 8 | PCA953X_TYPE, },97 { "pca9557", 8 | PCA953X_TYPE, },98 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },99 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },100 { "pca9698", 40 | PCA953X_TYPE, },101 102 { "pcal6408", 8 | PCA953X_TYPE | PCA_LATCH_INT, },103 { "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, },104 { "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, },105 { "pcal6534", 34 | PCAL653X_TYPE | PCA_LATCH_INT, },106 { "pcal9535", 16 | PCA953X_TYPE | PCA_LATCH_INT, },107 { "pcal9554b", 8 | PCA953X_TYPE | PCA_LATCH_INT, },108 { "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, },109 110 { "max7310", 8 | PCA953X_TYPE, },111 { "max7312", 16 | PCA953X_TYPE | PCA_INT, },112 { "max7313", 16 | PCA953X_TYPE | PCA_INT, },113 { "max7315", 8 | PCA953X_TYPE | PCA_INT, },114 { "max7318", 16 | PCA953X_TYPE | PCA_INT, },115 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },116 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },117 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },118 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },119 { "tca9538", 8 | PCA953X_TYPE | PCA_INT, },120 { "tca9539", 16 | PCA953X_TYPE | PCA_INT, },121 { "tca9554", 8 | PCA953X_TYPE | PCA_INT, },122 { "xra1202", 8 | PCA953X_TYPE },123 { }124};125MODULE_DEVICE_TABLE(i2c, pca953x_id);126 127#ifdef CONFIG_GPIO_PCA953X_IRQ128 129#include <linux/acpi.h>130#include <linux/dmi.h>131 132static const struct acpi_gpio_params pca953x_irq_gpios = { 0, 0, true };133 134static const struct acpi_gpio_mapping pca953x_acpi_irq_gpios[] = {135 { "irq-gpios", &pca953x_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER },136 { }137};138 139static int pca953x_acpi_get_irq(struct device *dev)140{141 int ret;142 143 ret = devm_acpi_dev_add_driver_gpios(dev, pca953x_acpi_irq_gpios);144 if (ret)145 dev_warn(dev, "can't add GPIO ACPI mapping\n");146 147 ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq", 0);148 if (ret < 0)149 return ret;150 151 dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret);152 return ret;153}154 155static const struct dmi_system_id pca953x_dmi_acpi_irq_info[] = {156 {157 /*158 * On Intel Galileo Gen 2 board the IRQ pin of one of159 * the I²C GPIO expanders, which has GpioInt() resource,160 * is provided as an absolute number instead of being161 * relative. Since first controller (gpio-sch.c) and162 * second (gpio-dwapb.c) are at the fixed bases, we may163 * safely refer to the number in the global space to get164 * an IRQ out of it.165 */166 .matches = {167 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),168 },169 },170 {}171};172#endif173 174static const struct acpi_device_id pca953x_acpi_ids[] = {175 { "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, },176 { }177};178MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);179 180#define MAX_BANK 5181#define BANK_SZ 8182#define MAX_LINE (MAX_BANK * BANK_SZ)183 184#define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)185 186struct pca953x_reg_config {187 int direction;188 int output;189 int input;190 int invert;191};192 193static const struct pca953x_reg_config pca953x_regs = {194 .direction = PCA953X_DIRECTION,195 .output = PCA953X_OUTPUT,196 .input = PCA953X_INPUT,197 .invert = PCA953X_INVERT,198};199 200static const struct pca953x_reg_config pca957x_regs = {201 .direction = PCA957X_CFG,202 .output = PCA957X_OUT,203 .input = PCA957X_IN,204 .invert = PCA957X_INVRT,205};206 207struct pca953x_chip {208 unsigned gpio_start;209 struct mutex i2c_lock;210 struct regmap *regmap;211 212#ifdef CONFIG_GPIO_PCA953X_IRQ213 struct mutex irq_lock;214 DECLARE_BITMAP(irq_mask, MAX_LINE);215 DECLARE_BITMAP(irq_stat, MAX_LINE);216 DECLARE_BITMAP(irq_trig_raise, MAX_LINE);217 DECLARE_BITMAP(irq_trig_fall, MAX_LINE);218#endif219 atomic_t wakeup_path;220 221 struct i2c_client *client;222 struct gpio_chip gpio_chip;223 unsigned long driver_data;224 struct regulator *regulator;225 226 const struct pca953x_reg_config *regs;227 228 u8 (*recalc_addr)(struct pca953x_chip *chip, int reg, int off);229 bool (*check_reg)(struct pca953x_chip *chip, unsigned int reg,230 u32 checkbank);231};232 233static int pca953x_bank_shift(struct pca953x_chip *chip)234{235 return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);236}237 238#define PCA953x_BANK_INPUT BIT(0)239#define PCA953x_BANK_OUTPUT BIT(1)240#define PCA953x_BANK_POLARITY BIT(2)241#define PCA953x_BANK_CONFIG BIT(3)242 243#define PCA957x_BANK_INPUT BIT(0)244#define PCA957x_BANK_POLARITY BIT(1)245#define PCA957x_BANK_BUSHOLD BIT(2)246#define PCA957x_BANK_CONFIG BIT(4)247#define PCA957x_BANK_OUTPUT BIT(5)248 249#define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2)250#define PCAL9xxx_BANK_PULL_EN BIT(8 + 3)251#define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4)252#define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5)253#define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6)254 255/*256 * We care about the following registers:257 * - Standard set, below 0x40, each port can be replicated up to 8 times258 * - PCA953x standard259 * Input port 0x00 + 0 * bank_size R260 * Output port 0x00 + 1 * bank_size RW261 * Polarity Inversion port 0x00 + 2 * bank_size RW262 * Configuration port 0x00 + 3 * bank_size RW263 * - PCA957x with mixed up registers264 * Input port 0x00 + 0 * bank_size R265 * Polarity Inversion port 0x00 + 1 * bank_size RW266 * Bus hold port 0x00 + 2 * bank_size RW267 * Configuration port 0x00 + 4 * bank_size RW268 * Output port 0x00 + 5 * bank_size RW269 *270 * - Extended set, above 0x40, often chip specific.271 * - PCAL6524/PCAL9555A with custom PCAL IRQ handling:272 * Input latch register 0x40 + 2 * bank_size RW273 * Pull-up/pull-down enable reg 0x40 + 3 * bank_size RW274 * Pull-up/pull-down select reg 0x40 + 4 * bank_size RW275 * Interrupt mask register 0x40 + 5 * bank_size RW276 * Interrupt status register 0x40 + 6 * bank_size R277 *278 * - Registers with bit 0x80 set, the AI bit279 * The bit is cleared and the registers fall into one of the280 * categories above.281 */282 283static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg,284 u32 checkbank)285{286 int bank_shift = pca953x_bank_shift(chip);287 int bank = (reg & REG_ADDR_MASK) >> bank_shift;288 int offset = reg & (BIT(bank_shift) - 1);289 290 /* Special PCAL extended register check. */291 if (reg & REG_ADDR_EXT) {292 if (!(chip->driver_data & PCA_PCAL))293 return false;294 bank += 8;295 }296 297 /* Register is not in the matching bank. */298 if (!(BIT(bank) & checkbank))299 return false;300 301 /* Register is not within allowed range of bank. */302 if (offset >= NBANK(chip))303 return false;304 305 return true;306}307 308/*309 * Unfortunately, whilst the PCAL6534 chip (and compatibles) broadly follow the310 * same register layout as the PCAL6524, the spacing of the registers has been311 * fundamentally altered by compacting them and thus does not obey the same312 * rules, including being able to use bit shifting to determine bank. These313 * chips hence need special handling here.314 */315static bool pcal6534_check_register(struct pca953x_chip *chip, unsigned int reg,316 u32 checkbank)317{318 int bank_shift;319 int bank;320 int offset;321 322 if (reg >= 0x54) {323 /*324 * Handle lack of reserved registers after output port325 * configuration register to form a bank.326 */327 reg -= 0x54;328 bank_shift = 16;329 } else if (reg >= 0x30) {330 /*331 * Reserved block between 14h and 2Fh does not align on332 * expected bank boundaries like other devices.333 */334 reg -= 0x30;335 bank_shift = 8;336 } else {337 bank_shift = 0;338 }339 340 bank = bank_shift + reg / NBANK(chip);341 offset = reg % NBANK(chip);342 343 /* Register is not in the matching bank. */344 if (!(BIT(bank) & checkbank))345 return false;346 347 /* Register is not within allowed range of bank. */348 if (offset >= NBANK(chip))349 return false;350 351 return true;352}353 354static bool pca953x_readable_register(struct device *dev, unsigned int reg)355{356 struct pca953x_chip *chip = dev_get_drvdata(dev);357 u32 bank;358 359 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {360 bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT |361 PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG |362 PCA957x_BANK_BUSHOLD;363 } else {364 bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT |365 PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG;366 }367 368 if (chip->driver_data & PCA_PCAL) {369 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |370 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK |371 PCAL9xxx_BANK_IRQ_STAT;372 }373 374 return chip->check_reg(chip, reg, bank);375}376 377static bool pca953x_writeable_register(struct device *dev, unsigned int reg)378{379 struct pca953x_chip *chip = dev_get_drvdata(dev);380 u32 bank;381 382 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {383 bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY |384 PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD;385 } else {386 bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY |387 PCA953x_BANK_CONFIG;388 }389 390 if (chip->driver_data & PCA_PCAL)391 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |392 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK;393 394 return chip->check_reg(chip, reg, bank);395}396 397static bool pca953x_volatile_register(struct device *dev, unsigned int reg)398{399 struct pca953x_chip *chip = dev_get_drvdata(dev);400 u32 bank;401 402 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE)403 bank = PCA957x_BANK_INPUT;404 else405 bank = PCA953x_BANK_INPUT;406 407 if (chip->driver_data & PCA_PCAL)408 bank |= PCAL9xxx_BANK_IRQ_STAT;409 410 return chip->check_reg(chip, reg, bank);411}412 413static const struct regmap_config pca953x_i2c_regmap = {414 .reg_bits = 8,415 .val_bits = 8,416 417 .use_single_read = true,418 .use_single_write = true,419 420 .readable_reg = pca953x_readable_register,421 .writeable_reg = pca953x_writeable_register,422 .volatile_reg = pca953x_volatile_register,423 424 .disable_locking = true,425 .cache_type = REGCACHE_MAPLE,426 .max_register = 0x7f,427};428 429static const struct regmap_config pca953x_ai_i2c_regmap = {430 .reg_bits = 8,431 .val_bits = 8,432 433 .read_flag_mask = REG_ADDR_AI,434 .write_flag_mask = REG_ADDR_AI,435 436 .readable_reg = pca953x_readable_register,437 .writeable_reg = pca953x_writeable_register,438 .volatile_reg = pca953x_volatile_register,439 440 .disable_locking = true,441 .cache_type = REGCACHE_MAPLE,442 .max_register = 0x7f,443};444 445static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off)446{447 int bank_shift = pca953x_bank_shift(chip);448 int addr = (reg & PCAL_GPIO_MASK) << bank_shift;449 int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1;450 u8 regaddr = pinctrl | addr | (off / BANK_SZ);451 452 return regaddr;453}454 455/*456 * The PCAL6534 and compatible chips have altered bank alignment that doesn't457 * fit within the bit shifting scheme used for other devices.458 */459static u8 pcal6534_recalc_addr(struct pca953x_chip *chip, int reg, int off)460{461 int addr;462 int pinctrl;463 464 addr = (reg & PCAL_GPIO_MASK) * NBANK(chip);465 466 switch (reg) {467 case PCAL953X_OUT_STRENGTH:468 case PCAL953X_IN_LATCH:469 case PCAL953X_PULL_EN:470 case PCAL953X_PULL_SEL:471 case PCAL953X_INT_MASK:472 case PCAL953X_INT_STAT:473 pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x20;474 break;475 case PCAL6524_INT_EDGE:476 case PCAL6524_INT_CLR:477 case PCAL6524_IN_STATUS:478 case PCAL6524_OUT_INDCONF:479 case PCAL6524_DEBOUNCE:480 pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x1c;481 break;482 default:483 pinctrl = 0;484 break;485 }486 487 return pinctrl + addr + (off / BANK_SZ);488}489 490static int pca953x_write_regs(struct pca953x_chip *chip, int reg, unsigned long *val)491{492 u8 regaddr = chip->recalc_addr(chip, reg, 0);493 u8 value[MAX_BANK];494 int i, ret;495 496 for (i = 0; i < NBANK(chip); i++)497 value[i] = bitmap_get_value8(val, i * BANK_SZ);498 499 ret = regmap_bulk_write(chip->regmap, regaddr, value, NBANK(chip));500 if (ret < 0) {501 dev_err(&chip->client->dev, "failed writing register: %d\n", ret);502 return ret;503 }504 505 return 0;506}507 508static int pca953x_read_regs(struct pca953x_chip *chip, int reg, unsigned long *val)509{510 u8 regaddr = chip->recalc_addr(chip, reg, 0);511 u8 value[MAX_BANK];512 int i, ret;513 514 ret = regmap_bulk_read(chip->regmap, regaddr, value, NBANK(chip));515 if (ret < 0) {516 dev_err(&chip->client->dev, "failed reading register: %d\n", ret);517 return ret;518 }519 520 for (i = 0; i < NBANK(chip); i++)521 bitmap_set_value8(val, value[i], i * BANK_SZ);522 523 return 0;524}525 526static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)527{528 struct pca953x_chip *chip = gpiochip_get_data(gc);529 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off);530 u8 bit = BIT(off % BANK_SZ);531 532 guard(mutex)(&chip->i2c_lock);533 534 return regmap_write_bits(chip->regmap, dirreg, bit, bit);535}536 537static int pca953x_gpio_direction_output(struct gpio_chip *gc,538 unsigned off, int val)539{540 struct pca953x_chip *chip = gpiochip_get_data(gc);541 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off);542 u8 outreg = chip->recalc_addr(chip, chip->regs->output, off);543 u8 bit = BIT(off % BANK_SZ);544 int ret;545 546 guard(mutex)(&chip->i2c_lock);547 548 /* set output level */549 ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);550 if (ret)551 return ret;552 553 /* then direction */554 return regmap_write_bits(chip->regmap, dirreg, bit, 0);555}556 557static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)558{559 struct pca953x_chip *chip = gpiochip_get_data(gc);560 u8 inreg = chip->recalc_addr(chip, chip->regs->input, off);561 u8 bit = BIT(off % BANK_SZ);562 u32 reg_val;563 int ret;564 565 scoped_guard(mutex, &chip->i2c_lock)566 ret = regmap_read(chip->regmap, inreg, ®_val);567 if (ret < 0)568 return ret;569 570 return !!(reg_val & bit);571}572 573static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)574{575 struct pca953x_chip *chip = gpiochip_get_data(gc);576 u8 outreg = chip->recalc_addr(chip, chip->regs->output, off);577 u8 bit = BIT(off % BANK_SZ);578 579 guard(mutex)(&chip->i2c_lock);580 581 regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);582}583 584static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off)585{586 struct pca953x_chip *chip = gpiochip_get_data(gc);587 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off);588 u8 bit = BIT(off % BANK_SZ);589 u32 reg_val;590 int ret;591 592 scoped_guard(mutex, &chip->i2c_lock)593 ret = regmap_read(chip->regmap, dirreg, ®_val);594 if (ret < 0)595 return ret;596 597 if (reg_val & bit)598 return GPIO_LINE_DIRECTION_IN;599 600 return GPIO_LINE_DIRECTION_OUT;601}602 603static int pca953x_gpio_get_multiple(struct gpio_chip *gc,604 unsigned long *mask, unsigned long *bits)605{606 struct pca953x_chip *chip = gpiochip_get_data(gc);607 DECLARE_BITMAP(reg_val, MAX_LINE);608 int ret;609 610 scoped_guard(mutex, &chip->i2c_lock)611 ret = pca953x_read_regs(chip, chip->regs->input, reg_val);612 if (ret)613 return ret;614 615 bitmap_replace(bits, bits, reg_val, mask, gc->ngpio);616 return 0;617}618 619static void pca953x_gpio_set_multiple(struct gpio_chip *gc,620 unsigned long *mask, unsigned long *bits)621{622 struct pca953x_chip *chip = gpiochip_get_data(gc);623 DECLARE_BITMAP(reg_val, MAX_LINE);624 int ret;625 626 guard(mutex)(&chip->i2c_lock);627 628 ret = pca953x_read_regs(chip, chip->regs->output, reg_val);629 if (ret)630 return;631 632 bitmap_replace(reg_val, reg_val, bits, mask, gc->ngpio);633 634 pca953x_write_regs(chip, chip->regs->output, reg_val);635}636 637static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip,638 unsigned int offset,639 unsigned long config)640{641 enum pin_config_param param = pinconf_to_config_param(config);642 u8 pull_en_reg = chip->recalc_addr(chip, PCAL953X_PULL_EN, offset);643 u8 pull_sel_reg = chip->recalc_addr(chip, PCAL953X_PULL_SEL, offset);644 u8 bit = BIT(offset % BANK_SZ);645 int ret;646 647 /*648 * pull-up/pull-down configuration requires PCAL extended649 * registers650 */651 if (!(chip->driver_data & PCA_PCAL))652 return -ENOTSUPP;653 654 guard(mutex)(&chip->i2c_lock);655 656 /* Configure pull-up/pull-down */657 if (param == PIN_CONFIG_BIAS_PULL_UP)658 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, bit);659 else if (param == PIN_CONFIG_BIAS_PULL_DOWN)660 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, 0);661 else662 ret = 0;663 if (ret)664 return ret;665 666 /* Disable/Enable pull-up/pull-down */667 if (param == PIN_CONFIG_BIAS_DISABLE)668 return regmap_write_bits(chip->regmap, pull_en_reg, bit, 0);669 else670 return regmap_write_bits(chip->regmap, pull_en_reg, bit, bit);671}672 673static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset,674 unsigned long config)675{676 struct pca953x_chip *chip = gpiochip_get_data(gc);677 678 switch (pinconf_to_config_param(config)) {679 case PIN_CONFIG_BIAS_PULL_UP:680 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:681 case PIN_CONFIG_BIAS_PULL_DOWN:682 case PIN_CONFIG_BIAS_DISABLE:683 return pca953x_gpio_set_pull_up_down(chip, offset, config);684 default:685 return -ENOTSUPP;686 }687}688 689static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)690{691 struct gpio_chip *gc = &chip->gpio_chip;692 693 gc->direction_input = pca953x_gpio_direction_input;694 gc->direction_output = pca953x_gpio_direction_output;695 gc->get = pca953x_gpio_get_value;696 gc->set = pca953x_gpio_set_value;697 gc->get_direction = pca953x_gpio_get_direction;698 gc->get_multiple = pca953x_gpio_get_multiple;699 gc->set_multiple = pca953x_gpio_set_multiple;700 gc->set_config = pca953x_gpio_set_config;701 gc->can_sleep = true;702 703 gc->base = chip->gpio_start;704 gc->ngpio = gpios;705 gc->label = dev_name(&chip->client->dev);706 gc->parent = &chip->client->dev;707 gc->owner = THIS_MODULE;708}709 710#ifdef CONFIG_GPIO_PCA953X_IRQ711static void pca953x_irq_mask(struct irq_data *d)712{713 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);714 struct pca953x_chip *chip = gpiochip_get_data(gc);715 irq_hw_number_t hwirq = irqd_to_hwirq(d);716 717 clear_bit(hwirq, chip->irq_mask);718 gpiochip_disable_irq(gc, hwirq);719}720 721static void pca953x_irq_unmask(struct irq_data *d)722{723 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);724 struct pca953x_chip *chip = gpiochip_get_data(gc);725 irq_hw_number_t hwirq = irqd_to_hwirq(d);726 727 gpiochip_enable_irq(gc, hwirq);728 set_bit(hwirq, chip->irq_mask);729}730 731static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on)732{733 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);734 struct pca953x_chip *chip = gpiochip_get_data(gc);735 736 if (on)737 atomic_inc(&chip->wakeup_path);738 else739 atomic_dec(&chip->wakeup_path);740 741 return irq_set_irq_wake(chip->client->irq, on);742}743 744static void pca953x_irq_bus_lock(struct irq_data *d)745{746 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);747 struct pca953x_chip *chip = gpiochip_get_data(gc);748 749 mutex_lock(&chip->irq_lock);750}751 752static void pca953x_irq_bus_sync_unlock(struct irq_data *d)753{754 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);755 struct pca953x_chip *chip = gpiochip_get_data(gc);756 DECLARE_BITMAP(irq_mask, MAX_LINE);757 DECLARE_BITMAP(reg_direction, MAX_LINE);758 int level;759 760 if (chip->driver_data & PCA_PCAL) {761 guard(mutex)(&chip->i2c_lock);762 763 /* Enable latch on interrupt-enabled inputs */764 pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask);765 766 bitmap_complement(irq_mask, chip->irq_mask, gc->ngpio);767 768 /* Unmask enabled interrupts */769 pca953x_write_regs(chip, PCAL953X_INT_MASK, irq_mask);770 }771 772 /* Switch direction to input if needed */773 pca953x_read_regs(chip, chip->regs->direction, reg_direction);774 775 bitmap_or(irq_mask, chip->irq_trig_fall, chip->irq_trig_raise, gc->ngpio);776 bitmap_complement(reg_direction, reg_direction, gc->ngpio);777 bitmap_and(irq_mask, irq_mask, reg_direction, gc->ngpio);778 779 /* Look for any newly setup interrupt */780 for_each_set_bit(level, irq_mask, gc->ngpio)781 pca953x_gpio_direction_input(&chip->gpio_chip, level);782 783 mutex_unlock(&chip->irq_lock);784}785 786static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)787{788 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);789 struct pca953x_chip *chip = gpiochip_get_data(gc);790 struct device *dev = &chip->client->dev;791 irq_hw_number_t hwirq = irqd_to_hwirq(d);792 793 if (!(type & IRQ_TYPE_EDGE_BOTH)) {794 dev_err(dev, "irq %d: unsupported type %d\n", d->irq, type);795 return -EINVAL;796 }797 798 assign_bit(hwirq, chip->irq_trig_fall, type & IRQ_TYPE_EDGE_FALLING);799 assign_bit(hwirq, chip->irq_trig_raise, type & IRQ_TYPE_EDGE_RISING);800 801 return 0;802}803 804static void pca953x_irq_shutdown(struct irq_data *d)805{806 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);807 struct pca953x_chip *chip = gpiochip_get_data(gc);808 irq_hw_number_t hwirq = irqd_to_hwirq(d);809 810 clear_bit(hwirq, chip->irq_trig_raise);811 clear_bit(hwirq, chip->irq_trig_fall);812}813 814static void pca953x_irq_print_chip(struct irq_data *data, struct seq_file *p)815{816 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);817 818 seq_printf(p, dev_name(gc->parent));819}820 821static const struct irq_chip pca953x_irq_chip = {822 .irq_mask = pca953x_irq_mask,823 .irq_unmask = pca953x_irq_unmask,824 .irq_set_wake = pca953x_irq_set_wake,825 .irq_bus_lock = pca953x_irq_bus_lock,826 .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,827 .irq_set_type = pca953x_irq_set_type,828 .irq_shutdown = pca953x_irq_shutdown,829 .irq_print_chip = pca953x_irq_print_chip,830 .flags = IRQCHIP_IMMUTABLE,831 GPIOCHIP_IRQ_RESOURCE_HELPERS,832};833 834static bool pca953x_irq_pending(struct pca953x_chip *chip, unsigned long *pending)835{836 struct gpio_chip *gc = &chip->gpio_chip;837 DECLARE_BITMAP(reg_direction, MAX_LINE);838 DECLARE_BITMAP(old_stat, MAX_LINE);839 DECLARE_BITMAP(cur_stat, MAX_LINE);840 DECLARE_BITMAP(new_stat, MAX_LINE);841 DECLARE_BITMAP(trigger, MAX_LINE);842 int ret;843 844 if (chip->driver_data & PCA_PCAL) {845 /* Read the current interrupt status from the device */846 ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger);847 if (ret)848 return false;849 850 /* Check latched inputs and clear interrupt status */851 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);852 if (ret)853 return false;854 855 /* Apply filter for rising/falling edge selection */856 bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise, cur_stat, gc->ngpio);857 858 bitmap_and(pending, new_stat, trigger, gc->ngpio);859 860 return !bitmap_empty(pending, gc->ngpio);861 }862 863 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);864 if (ret)865 return false;866 867 /* Remove output pins from the equation */868 pca953x_read_regs(chip, chip->regs->direction, reg_direction);869 870 bitmap_copy(old_stat, chip->irq_stat, gc->ngpio);871 872 bitmap_and(new_stat, cur_stat, reg_direction, gc->ngpio);873 bitmap_xor(cur_stat, new_stat, old_stat, gc->ngpio);874 bitmap_and(trigger, cur_stat, chip->irq_mask, gc->ngpio);875 876 bitmap_copy(chip->irq_stat, new_stat, gc->ngpio);877 878 if (bitmap_empty(trigger, gc->ngpio))879 return false;880 881 bitmap_and(cur_stat, chip->irq_trig_fall, old_stat, gc->ngpio);882 bitmap_and(old_stat, chip->irq_trig_raise, new_stat, gc->ngpio);883 bitmap_or(new_stat, old_stat, cur_stat, gc->ngpio);884 bitmap_and(pending, new_stat, trigger, gc->ngpio);885 886 return !bitmap_empty(pending, gc->ngpio);887}888 889static irqreturn_t pca953x_irq_handler(int irq, void *devid)890{891 struct pca953x_chip *chip = devid;892 struct gpio_chip *gc = &chip->gpio_chip;893 DECLARE_BITMAP(pending, MAX_LINE);894 int level;895 bool ret;896 897 bitmap_zero(pending, MAX_LINE);898 899 scoped_guard(mutex, &chip->i2c_lock)900 ret = pca953x_irq_pending(chip, pending);901 if (ret) {902 ret = 0;903 904 for_each_set_bit(level, pending, gc->ngpio) {905 int nested_irq = irq_find_mapping(gc->irq.domain, level);906 907 if (unlikely(nested_irq <= 0)) {908 dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level);909 continue;910 }911 912 handle_nested_irq(nested_irq);913 ret = 1;914 }915 }916 917 return IRQ_RETVAL(ret);918}919 920static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base)921{922 struct i2c_client *client = chip->client;923 struct device *dev = &client->dev;924 DECLARE_BITMAP(reg_direction, MAX_LINE);925 DECLARE_BITMAP(irq_stat, MAX_LINE);926 struct gpio_chip *gc = &chip->gpio_chip;927 struct gpio_irq_chip *girq;928 int ret;929 930 if (dmi_first_match(pca953x_dmi_acpi_irq_info)) {931 ret = pca953x_acpi_get_irq(dev);932 if (ret > 0)933 client->irq = ret;934 }935 936 if (!client->irq)937 return 0;938 939 if (irq_base == -1)940 return 0;941 942 if (!(chip->driver_data & PCA_INT))943 return 0;944 945 ret = pca953x_read_regs(chip, chip->regs->input, irq_stat);946 if (ret)947 return ret;948 949 /*950 * There is no way to know which GPIO line generated the951 * interrupt. We have to rely on the previous read for952 * this purpose.953 */954 pca953x_read_regs(chip, chip->regs->direction, reg_direction);955 bitmap_and(chip->irq_stat, irq_stat, reg_direction, gc->ngpio);956 mutex_init(&chip->irq_lock);957 958 girq = &chip->gpio_chip.irq;959 gpio_irq_chip_set_chip(girq, &pca953x_irq_chip);960 /* This will let us handle the parent IRQ in the driver */961 girq->parent_handler = NULL;962 girq->num_parents = 0;963 girq->parents = NULL;964 girq->default_type = IRQ_TYPE_NONE;965 girq->handler = handle_simple_irq;966 girq->threaded = true;967 girq->first = irq_base; /* FIXME: get rid of this */968 969 ret = devm_request_threaded_irq(dev, client->irq, NULL, pca953x_irq_handler,970 IRQF_ONESHOT | IRQF_SHARED, dev_name(dev),971 chip);972 if (ret)973 return dev_err_probe(dev, client->irq, "failed to request irq\n");974 975 return 0;976}977 978#else /* CONFIG_GPIO_PCA953X_IRQ */979static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base)980{981 struct i2c_client *client = chip->client;982 struct device *dev = &client->dev;983 984 if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT))985 dev_warn(dev, "interrupt support not compiled in\n");986 987 return 0;988}989#endif990 991static int device_pca95xx_init(struct pca953x_chip *chip)992{993 DECLARE_BITMAP(val, MAX_LINE);994 u8 regaddr;995 int ret;996 997 regaddr = chip->recalc_addr(chip, chip->regs->output, 0);998 ret = regcache_sync_region(chip->regmap, regaddr,999 regaddr + NBANK(chip) - 1);1000 if (ret)1001 return ret;1002 1003 regaddr = chip->recalc_addr(chip, chip->regs->direction, 0);1004 ret = regcache_sync_region(chip->regmap, regaddr,1005 regaddr + NBANK(chip) - 1);1006 if (ret)1007 return ret;1008 1009 /* clear polarity inversion */1010 bitmap_zero(val, MAX_LINE);1011 1012 return pca953x_write_regs(chip, chip->regs->invert, val);1013}1014 1015static int device_pca957x_init(struct pca953x_chip *chip)1016{1017 DECLARE_BITMAP(val, MAX_LINE);1018 unsigned int i;1019 int ret;1020 1021 ret = device_pca95xx_init(chip);1022 if (ret)1023 return ret;1024 1025 /* To enable register 6, 7 to control pull up and pull down */1026 for (i = 0; i < NBANK(chip); i++)1027 bitmap_set_value8(val, 0x02, i * BANK_SZ);1028 1029 return pca953x_write_regs(chip, PCA957X_BKEN, val);1030}1031 1032static void pca953x_disable_regulator(void *reg)1033{1034 regulator_disable(reg);1035}1036 1037static int pca953x_get_and_enable_regulator(struct pca953x_chip *chip)1038{1039 struct device *dev = &chip->client->dev;1040 struct regulator *reg = chip->regulator;1041 int ret;1042 1043 reg = devm_regulator_get(dev, "vcc");1044 if (IS_ERR(reg))1045 return dev_err_probe(dev, PTR_ERR(reg), "reg get err\n");1046 1047 ret = regulator_enable(reg);1048 if (ret)1049 return dev_err_probe(dev, ret, "reg en err\n");1050 1051 ret = devm_add_action_or_reset(dev, pca953x_disable_regulator, reg);1052 if (ret)1053 return ret;1054 1055 chip->regulator = reg;1056 return 0;1057}1058 1059static int pca953x_probe(struct i2c_client *client)1060{1061 struct device *dev = &client->dev;1062 struct pca953x_platform_data *pdata;1063 struct pca953x_chip *chip;1064 int irq_base;1065 int ret;1066 const struct regmap_config *regmap_config;1067 1068 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);1069 if (chip == NULL)1070 return -ENOMEM;1071 1072 pdata = dev_get_platdata(dev);1073 if (pdata) {1074 irq_base = pdata->irq_base;1075 chip->gpio_start = pdata->gpio_base;1076 } else {1077 struct gpio_desc *reset_gpio;1078 1079 chip->gpio_start = -1;1080 irq_base = 0;1081 1082 /*1083 * See if we need to de-assert a reset pin.1084 *1085 * There is no known ACPI-enabled platforms that are1086 * using "reset" GPIO. Otherwise any of those platform1087 * must use _DSD method with corresponding property.1088 */1089 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);1090 if (IS_ERR(reset_gpio))1091 return PTR_ERR(reset_gpio);1092 }1093 1094 chip->client = client;1095 chip->driver_data = (uintptr_t)i2c_get_match_data(client);1096 if (!chip->driver_data)1097 return -ENODEV;1098 1099 ret = pca953x_get_and_enable_regulator(chip);1100 if (ret)1101 return ret;1102 1103 i2c_set_clientdata(client, chip);1104 1105 pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);1106 1107 if (NBANK(chip) > 2 || PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {1108 dev_info(dev, "using AI\n");1109 regmap_config = &pca953x_ai_i2c_regmap;1110 } else {1111 dev_info(dev, "using no AI\n");1112 regmap_config = &pca953x_i2c_regmap;1113 }1114 1115 if (PCA_CHIP_TYPE(chip->driver_data) == PCAL653X_TYPE) {1116 chip->recalc_addr = pcal6534_recalc_addr;1117 chip->check_reg = pcal6534_check_register;1118 } else {1119 chip->recalc_addr = pca953x_recalc_addr;1120 chip->check_reg = pca953x_check_register;1121 }1122 1123 chip->regmap = devm_regmap_init_i2c(client, regmap_config);1124 if (IS_ERR(chip->regmap))1125 return PTR_ERR(chip->regmap);1126 1127 regcache_mark_dirty(chip->regmap);1128 1129 mutex_init(&chip->i2c_lock);1130 /*1131 * In case we have an i2c-mux controlled by a GPIO provided by an1132 * expander using the same driver higher on the device tree, read the1133 * i2c adapter nesting depth and use the retrieved value as lockdep1134 * subclass for chip->i2c_lock.1135 *1136 * REVISIT: This solution is not complete. It protects us from lockdep1137 * false positives when the expander controlling the i2c-mux is on1138 * a different level on the device tree, but not when it's on the same1139 * level on a different branch (in which case the subclass number1140 * would be the same).1141 *1142 * TODO: Once a correct solution is developed, a similar fix should be1143 * applied to all other i2c-controlled GPIO expanders (and potentially1144 * regmap-i2c).1145 */1146 lockdep_set_subclass(&chip->i2c_lock,1147 i2c_adapter_depth(client->adapter));1148 1149 /* initialize cached registers from their original values.1150 * we can't share this chip with another i2c master.1151 */1152 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {1153 chip->regs = &pca957x_regs;1154 ret = device_pca957x_init(chip);1155 } else {1156 chip->regs = &pca953x_regs;1157 ret = device_pca95xx_init(chip);1158 }1159 if (ret)1160 return ret;1161 1162 ret = pca953x_irq_setup(chip, irq_base);1163 if (ret)1164 return ret;1165 1166 return devm_gpiochip_add_data(dev, &chip->gpio_chip, chip);1167}1168 1169static int pca953x_regcache_sync(struct pca953x_chip *chip)1170{1171 struct device *dev = &chip->client->dev;1172 int ret;1173 u8 regaddr;1174 1175 /*1176 * The ordering between direction and output is important,1177 * sync these registers first and only then sync the rest.1178 */1179 regaddr = chip->recalc_addr(chip, chip->regs->direction, 0);1180 ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1);1181 if (ret) {1182 dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret);1183 return ret;1184 }1185 1186 regaddr = chip->recalc_addr(chip, chip->regs->output, 0);1187 ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1);1188 if (ret) {1189 dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret);1190 return ret;1191 }1192 1193#ifdef CONFIG_GPIO_PCA953X_IRQ1194 if (chip->driver_data & PCA_PCAL) {1195 regaddr = chip->recalc_addr(chip, PCAL953X_IN_LATCH, 0);1196 ret = regcache_sync_region(chip->regmap, regaddr,1197 regaddr + NBANK(chip) - 1);1198 if (ret) {1199 dev_err(dev, "Failed to sync INT latch registers: %d\n",1200 ret);1201 return ret;1202 }1203 1204 regaddr = chip->recalc_addr(chip, PCAL953X_INT_MASK, 0);1205 ret = regcache_sync_region(chip->regmap, regaddr,1206 regaddr + NBANK(chip) - 1);1207 if (ret) {1208 dev_err(dev, "Failed to sync INT mask registers: %d\n",1209 ret);1210 return ret;1211 }1212 }1213#endif1214 1215 return 0;1216}1217 1218static int pca953x_restore_context(struct pca953x_chip *chip)1219{1220 int ret;1221 1222 guard(mutex)(&chip->i2c_lock);1223 1224 regcache_cache_only(chip->regmap, false);1225 regcache_mark_dirty(chip->regmap);1226 ret = pca953x_regcache_sync(chip);1227 if (ret)1228 return ret;1229 1230 return regcache_sync(chip->regmap);1231}1232 1233static void pca953x_save_context(struct pca953x_chip *chip)1234{1235 guard(mutex)(&chip->i2c_lock);1236 regcache_cache_only(chip->regmap, true);1237}1238 1239static int pca953x_suspend(struct device *dev)1240{1241 struct pca953x_chip *chip = dev_get_drvdata(dev);1242 1243 pca953x_save_context(chip);1244 1245 if (atomic_read(&chip->wakeup_path))1246 device_set_wakeup_path(dev);1247 else1248 regulator_disable(chip->regulator);1249 1250 return 0;1251}1252 1253static int pca953x_resume(struct device *dev)1254{1255 struct pca953x_chip *chip = dev_get_drvdata(dev);1256 int ret;1257 1258 if (!atomic_read(&chip->wakeup_path)) {1259 ret = regulator_enable(chip->regulator);1260 if (ret) {1261 dev_err(dev, "Failed to enable regulator: %d\n", ret);1262 return 0;1263 }1264 }1265 1266 ret = pca953x_restore_context(chip);1267 if (ret)1268 dev_err(dev, "Failed to restore register map: %d\n", ret);1269 1270 return ret;1271}1272 1273static DEFINE_SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume);1274 1275/* convenience to stop overlong match-table lines */1276#define OF_653X(__nrgpio, __int) ((void *)(__nrgpio | PCAL653X_TYPE | __int))1277#define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int)1278#define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int)1279 1280static const struct of_device_id pca953x_dt_ids[] = {1281 { .compatible = "nxp,pca6408", .data = OF_953X(8, PCA_INT), },1282 { .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), },1283 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },1284 { .compatible = "nxp,pca9506", .data = OF_953X(40, PCA_INT), },1285 { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },1286 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },1287 { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },1288 { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },1289 { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },1290 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },1291 { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), },1292 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },1293 { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), },1294 { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), },1295 { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), },1296 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },1297 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },1298 1299 { .compatible = "nxp,pcal6408", .data = OF_953X(8, PCA_LATCH_INT), },1300 { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), },1301 { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), },1302 { .compatible = "nxp,pcal6534", .data = OF_653X(34, PCA_LATCH_INT), },1303 { .compatible = "nxp,pcal9535", .data = OF_953X(16, PCA_LATCH_INT), },1304 { .compatible = "nxp,pcal9554b", .data = OF_953X( 8, PCA_LATCH_INT), },1305 { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), },1306 1307 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },1308 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },1309 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },1310 { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), },1311 { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), },1312 1313 { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), },1314 { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), },1315 { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },1316 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },1317 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },1318 { .compatible = "ti,tca9535", .data = OF_953X(16, PCA_INT), },1319 { .compatible = "ti,tca9538", .data = OF_953X( 8, PCA_INT), },1320 { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), },1321 1322 { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), },1323 { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), },1324 { .compatible = "onnn,pca9655", .data = OF_953X(16, PCA_INT), },1325 1326 { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },1327 { }1328};1329 1330MODULE_DEVICE_TABLE(of, pca953x_dt_ids);1331 1332static struct i2c_driver pca953x_driver = {1333 .driver = {1334 .name = "pca953x",1335 .pm = pm_sleep_ptr(&pca953x_pm_ops),1336 .of_match_table = pca953x_dt_ids,1337 .acpi_match_table = pca953x_acpi_ids,1338 },1339 .probe = pca953x_probe,1340 .id_table = pca953x_id,1341};1342 1343static int __init pca953x_init(void)1344{1345 return i2c_add_driver(&pca953x_driver);1346}1347/* register after i2c postcore initcall and before1348 * subsys initcalls that may rely on these GPIOs1349 */1350subsys_initcall(pca953x_init);1351 1352static void __exit pca953x_exit(void)1353{1354 i2c_del_driver(&pca953x_driver);1355}1356module_exit(pca953x_exit);1357 1358MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");1359MODULE_DESCRIPTION("GPIO expander driver for PCA953x");1360MODULE_LICENSE("GPL");1361