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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (C) ST-Ericsson SA 20104 *5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson6 */7 8#include <linux/bitops.h>9#include <linux/cleanup.h>10#include <linux/gpio/driver.h>11#include <linux/init.h>12#include <linux/interrupt.h>13#include <linux/mfd/stmpe.h>14#include <linux/property.h>15#include <linux/platform_device.h>16#include <linux/seq_file.h>17#include <linux/slab.h>18 19/*20 * These registers are modified under the irq bus lock and cached to avoid21 * unnecessary writes in bus_sync_unlock.22 */23enum { REG_RE, REG_FE, REG_IE };24 25enum { LSB, CSB, MSB };26 27#define CACHE_NR_REGS 328/* No variant has more than 24 GPIOs */29#define CACHE_NR_BANKS (24 / 8)30 31struct stmpe_gpio {32 struct gpio_chip chip;33 struct stmpe *stmpe;34 struct mutex irq_lock;35 u32 norequest_mask;36 /* Caches of interrupt control registers for bus_lock */37 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];38 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];39};40 41static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)42{43 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);44 struct stmpe *stmpe = stmpe_gpio->stmpe;45 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)];46 u8 mask = BIT(offset % 8);47 int ret;48 49 ret = stmpe_reg_read(stmpe, reg);50 if (ret < 0)51 return ret;52 53 return !!(ret & mask);54}55 56static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)57{58 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);59 struct stmpe *stmpe = stmpe_gpio->stmpe;60 int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;61 u8 reg = stmpe->regs[which + (offset / 8)];62 u8 mask = BIT(offset % 8);63 64 /*65 * Some variants have single register for gpio set/clear functionality.66 * For them we need to write 0 to clear and 1 to set.67 */68 if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])69 stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);70 else71 stmpe_reg_write(stmpe, reg, mask);72}73 74static int stmpe_gpio_get_direction(struct gpio_chip *chip,75 unsigned offset)76{77 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);78 struct stmpe *stmpe = stmpe_gpio->stmpe;79 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);80 u8 mask = BIT(offset % 8);81 int ret;82 83 ret = stmpe_reg_read(stmpe, reg);84 if (ret < 0)85 return ret;86 87 if (ret & mask)88 return GPIO_LINE_DIRECTION_OUT;89 90 return GPIO_LINE_DIRECTION_IN;91}92 93static int stmpe_gpio_direction_output(struct gpio_chip *chip,94 unsigned offset, int val)95{96 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);97 struct stmpe *stmpe = stmpe_gpio->stmpe;98 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];99 u8 mask = BIT(offset % 8);100 101 stmpe_gpio_set(chip, offset, val);102 103 return stmpe_set_bits(stmpe, reg, mask, mask);104}105 106static int stmpe_gpio_direction_input(struct gpio_chip *chip,107 unsigned offset)108{109 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);110 struct stmpe *stmpe = stmpe_gpio->stmpe;111 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];112 u8 mask = BIT(offset % 8);113 114 return stmpe_set_bits(stmpe, reg, mask, 0);115}116 117static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)118{119 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);120 struct stmpe *stmpe = stmpe_gpio->stmpe;121 122 if (stmpe_gpio->norequest_mask & BIT(offset))123 return -EINVAL;124 125 return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO);126}127 128static const struct gpio_chip template_chip = {129 .label = "stmpe",130 .owner = THIS_MODULE,131 .get_direction = stmpe_gpio_get_direction,132 .direction_input = stmpe_gpio_direction_input,133 .get = stmpe_gpio_get,134 .direction_output = stmpe_gpio_direction_output,135 .set = stmpe_gpio_set,136 .request = stmpe_gpio_request,137 .can_sleep = true,138};139 140static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)141{142 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);143 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);144 int offset = d->hwirq;145 int regoffset = offset / 8;146 int mask = BIT(offset % 8);147 148 if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH)149 return -EINVAL;150 151 /* STMPE801 and STMPE 1600 don't have RE and FE registers */152 if (stmpe_gpio->stmpe->partnum == STMPE801 ||153 stmpe_gpio->stmpe->partnum == STMPE1600)154 return 0;155 156 if (type & IRQ_TYPE_EDGE_RISING)157 stmpe_gpio->regs[REG_RE][regoffset] |= mask;158 else159 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;160 161 if (type & IRQ_TYPE_EDGE_FALLING)162 stmpe_gpio->regs[REG_FE][regoffset] |= mask;163 else164 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;165 166 return 0;167}168 169static void stmpe_gpio_irq_lock(struct irq_data *d)170{171 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);172 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);173 174 mutex_lock(&stmpe_gpio->irq_lock);175}176 177static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)178{179 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);180 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);181 struct stmpe *stmpe = stmpe_gpio->stmpe;182 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);183 static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = {184 [REG_RE][LSB] = STMPE_IDX_GPRER_LSB,185 [REG_RE][CSB] = STMPE_IDX_GPRER_CSB,186 [REG_RE][MSB] = STMPE_IDX_GPRER_MSB,187 [REG_FE][LSB] = STMPE_IDX_GPFER_LSB,188 [REG_FE][CSB] = STMPE_IDX_GPFER_CSB,189 [REG_FE][MSB] = STMPE_IDX_GPFER_MSB,190 [REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB,191 [REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB,192 [REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB,193 };194 int i, j;195 196 /*197 * STMPE1600: to be able to get IRQ from pins,198 * a read must be done on GPMR register, or a write in199 * GPSR or GPCR registers200 */201 if (stmpe->partnum == STMPE1600) {202 stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]);203 stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]);204 }205 206 for (i = 0; i < CACHE_NR_REGS; i++) {207 /* STMPE801 and STMPE1600 don't have RE and FE registers */208 if ((stmpe->partnum == STMPE801 ||209 stmpe->partnum == STMPE1600) &&210 (i != REG_IE))211 continue;212 213 for (j = 0; j < num_banks; j++) {214 u8 old = stmpe_gpio->oldregs[i][j];215 u8 new = stmpe_gpio->regs[i][j];216 217 if (new == old)218 continue;219 220 stmpe_gpio->oldregs[i][j] = new;221 stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new);222 }223 }224 225 mutex_unlock(&stmpe_gpio->irq_lock);226}227 228static void stmpe_gpio_irq_mask(struct irq_data *d)229{230 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);231 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);232 int offset = d->hwirq;233 int regoffset = offset / 8;234 int mask = BIT(offset % 8);235 236 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;237 gpiochip_disable_irq(gc, offset);238}239 240static void stmpe_gpio_irq_unmask(struct irq_data *d)241{242 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);243 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);244 int offset = d->hwirq;245 int regoffset = offset / 8;246 int mask = BIT(offset % 8);247 248 gpiochip_enable_irq(gc, offset);249 stmpe_gpio->regs[REG_IE][regoffset] |= mask;250}251 252static void stmpe_dbg_show_one(struct seq_file *s,253 struct gpio_chip *gc,254 unsigned offset, unsigned gpio)255{256 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);257 struct stmpe *stmpe = stmpe_gpio->stmpe;258 bool val = !!stmpe_gpio_get(gc, offset);259 u8 bank = offset / 8;260 u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];261 u8 mask = BIT(offset % 8);262 int ret;263 u8 dir;264 265 char *label __free(kfree) = gpiochip_dup_line_label(gc, offset);266 if (IS_ERR(label))267 return;268 269 ret = stmpe_reg_read(stmpe, dir_reg);270 if (ret < 0)271 return;272 dir = !!(ret & mask);273 274 if (dir) {275 seq_printf(s, " gpio-%-3d (%-20.20s) out %s",276 gpio, label ?: "(none)",277 val ? "hi" : "lo");278 } else {279 u8 edge_det_reg;280 u8 rise_reg;281 u8 fall_reg;282 u8 irqen_reg;283 284 static const char * const edge_det_values[] = {285 "edge-inactive",286 "edge-asserted",287 "not-supported"288 };289 static const char * const rise_values[] = {290 "no-rising-edge-detection",291 "rising-edge-detection",292 "not-supported"293 };294 static const char * const fall_values[] = {295 "no-falling-edge-detection",296 "falling-edge-detection",297 "not-supported"298 };299 #define NOT_SUPPORTED_IDX 2300 u8 edge_det = NOT_SUPPORTED_IDX;301 u8 rise = NOT_SUPPORTED_IDX;302 u8 fall = NOT_SUPPORTED_IDX;303 bool irqen;304 305 switch (stmpe->partnum) {306 case STMPE610:307 case STMPE811:308 case STMPE1601:309 case STMPE2401:310 case STMPE2403:311 edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];312 ret = stmpe_reg_read(stmpe, edge_det_reg);313 if (ret < 0)314 return;315 edge_det = !!(ret & mask);316 fallthrough;317 case STMPE1801:318 rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];319 fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];320 321 ret = stmpe_reg_read(stmpe, rise_reg);322 if (ret < 0)323 return;324 rise = !!(ret & mask);325 ret = stmpe_reg_read(stmpe, fall_reg);326 if (ret < 0)327 return;328 fall = !!(ret & mask);329 fallthrough;330 case STMPE801:331 case STMPE1600:332 irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];333 break;334 335 default:336 return;337 }338 339 ret = stmpe_reg_read(stmpe, irqen_reg);340 if (ret < 0)341 return;342 irqen = !!(ret & mask);343 344 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s",345 gpio, label ?: "(none)",346 val ? "hi" : "lo",347 edge_det_values[edge_det],348 irqen ? "IRQ-enabled" : "IRQ-disabled",349 rise_values[rise],350 fall_values[fall]);351 }352}353 354static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc)355{356 unsigned i;357 unsigned gpio = gc->base;358 359 for (i = 0; i < gc->ngpio; i++, gpio++) {360 stmpe_dbg_show_one(s, gc, i, gpio);361 seq_putc(s, '\n');362 }363}364 365static const struct irq_chip stmpe_gpio_irq_chip = {366 .name = "stmpe-gpio",367 .irq_bus_lock = stmpe_gpio_irq_lock,368 .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,369 .irq_mask = stmpe_gpio_irq_mask,370 .irq_unmask = stmpe_gpio_irq_unmask,371 .irq_set_type = stmpe_gpio_irq_set_type,372 .flags = IRQCHIP_IMMUTABLE,373 GPIOCHIP_IRQ_RESOURCE_HELPERS,374};375 376#define MAX_GPIOS 24377 378static irqreturn_t stmpe_gpio_irq(int irq, void *dev)379{380 struct stmpe_gpio *stmpe_gpio = dev;381 struct stmpe *stmpe = stmpe_gpio->stmpe;382 u8 statmsbreg;383 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);384 u8 status[DIV_ROUND_UP(MAX_GPIOS, 8)];385 int ret;386 int i;387 388 /*389 * the stmpe_block_read() call below, imposes to set statmsbreg390 * with the register located at the lowest address. As STMPE1600391 * variant is the only one which respect registers address's order392 * (LSB regs located at lowest address than MSB ones) whereas all393 * the others have a registers layout with MSB located before the394 * LSB regs.395 */396 if (stmpe->partnum == STMPE1600)397 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB];398 else399 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];400 401 ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);402 if (ret < 0)403 return IRQ_NONE;404 405 for (i = 0; i < num_banks; i++) {406 int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :407 num_banks - i - 1;408 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];409 unsigned int stat = status[i];410 411 stat &= enabled;412 if (!stat)413 continue;414 415 while (stat) {416 int bit = __ffs(stat);417 int line = bank * 8 + bit;418 int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain,419 line);420 421 handle_nested_irq(child_irq);422 stat &= ~BIT(bit);423 }424 425 /*426 * interrupt status register write has no effect on427 * 801/1801/1600, bits are cleared when read.428 * Edge detect register is not present on 801/1600/1801429 */430 if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 &&431 stmpe->partnum != STMPE1801) {432 stmpe_reg_write(stmpe, statmsbreg + i, status[i]);433 stmpe_reg_write(stmpe,434 stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,435 status[i]);436 }437 }438 439 return IRQ_HANDLED;440}441 442static void stmpe_init_irq_valid_mask(struct gpio_chip *gc,443 unsigned long *valid_mask,444 unsigned int ngpios)445{446 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);447 int i;448 449 if (!stmpe_gpio->norequest_mask)450 return;451 452 /* Forbid unused lines to be mapped as IRQs */453 for (i = 0; i < sizeof(u32); i++) {454 if (stmpe_gpio->norequest_mask & BIT(i))455 clear_bit(i, valid_mask);456 }457}458 459static void stmpe_gpio_disable(void *stmpe)460{461 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);462}463 464static int stmpe_gpio_probe(struct platform_device *pdev)465{466 struct device *dev = &pdev->dev;467 struct stmpe *stmpe = dev_get_drvdata(dev->parent);468 struct stmpe_gpio *stmpe_gpio;469 int ret, irq;470 471 if (stmpe->num_gpios > MAX_GPIOS) {472 dev_err(dev, "Need to increase maximum GPIO number\n");473 return -EINVAL;474 }475 476 stmpe_gpio = devm_kzalloc(dev, sizeof(*stmpe_gpio), GFP_KERNEL);477 if (!stmpe_gpio)478 return -ENOMEM;479 480 mutex_init(&stmpe_gpio->irq_lock);481 482 stmpe_gpio->stmpe = stmpe;483 stmpe_gpio->chip = template_chip;484 stmpe_gpio->chip.ngpio = stmpe->num_gpios;485 stmpe_gpio->chip.parent = dev;486 stmpe_gpio->chip.base = -1;487 488 if (IS_ENABLED(CONFIG_DEBUG_FS))489 stmpe_gpio->chip.dbg_show = stmpe_dbg_show;490 491 device_property_read_u32(dev, "st,norequest-mask", &stmpe_gpio->norequest_mask);492 493 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);494 if (ret)495 return ret;496 497 ret = devm_add_action_or_reset(dev, stmpe_gpio_disable, stmpe);498 if (ret)499 return ret;500 501 irq = platform_get_irq(pdev, 0);502 if (irq > 0) {503 struct gpio_irq_chip *girq;504 505 ret = devm_request_threaded_irq(dev, irq, NULL, stmpe_gpio_irq,506 IRQF_ONESHOT, "stmpe-gpio", stmpe_gpio);507 if (ret)508 return dev_err_probe(dev, ret, "unable to register IRQ handler\n");509 510 girq = &stmpe_gpio->chip.irq;511 gpio_irq_chip_set_chip(girq, &stmpe_gpio_irq_chip);512 /* This will let us handle the parent IRQ in the driver */513 girq->parent_handler = NULL;514 girq->num_parents = 0;515 girq->parents = NULL;516 girq->default_type = IRQ_TYPE_NONE;517 girq->handler = handle_simple_irq;518 girq->threaded = true;519 girq->init_valid_mask = stmpe_init_irq_valid_mask;520 }521 522 return devm_gpiochip_add_data(dev, &stmpe_gpio->chip, stmpe_gpio);523}524 525static struct platform_driver stmpe_gpio_driver = {526 .driver = {527 .suppress_bind_attrs = true,528 .name = "stmpe-gpio",529 },530 .probe = stmpe_gpio_probe,531};532 533static int __init stmpe_gpio_init(void)534{535 return platform_driver_register(&stmpe_gpio_driver);536}537subsys_initcall(stmpe_gpio_init);538