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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2016-2022 NVIDIA Corporation4 *5 * Author: Thierry Reding <treding@nvidia.com>6 * Dipen Patel <dpatel@nvidia.com>7 */8 9#include <linux/gpio/driver.h>10#include <linux/hte.h>11#include <linux/interrupt.h>12#include <linux/irq.h>13#include <linux/module.h>14#include <linux/of.h>15#include <linux/platform_device.h>16#include <linux/property.h>17#include <linux/seq_file.h>18 19#include <dt-bindings/gpio/tegra186-gpio.h>20#include <dt-bindings/gpio/tegra194-gpio.h>21#include <dt-bindings/gpio/tegra234-gpio.h>22#include <dt-bindings/gpio/tegra241-gpio.h>23 24/* security registers */25#define TEGRA186_GPIO_CTL_SCR 0x0c26#define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28)27#define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27)28 29#define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4)30 31#define TEGRA186_GPIO_VM 0x0032#define TEGRA186_GPIO_VM_RW_MASK 0x0333#define TEGRA186_GPIO_SCR 0x0434#define TEGRA186_GPIO_SCR_PIN_SIZE 0x0835#define TEGRA186_GPIO_SCR_PORT_SIZE 0x4036#define TEGRA186_GPIO_SCR_SEC_WEN BIT(28)37#define TEGRA186_GPIO_SCR_SEC_REN BIT(27)38#define TEGRA186_GPIO_SCR_SEC_G1W BIT(9)39#define TEGRA186_GPIO_SCR_SEC_G1R BIT(1)40 41/* control registers */42#define TEGRA186_GPIO_ENABLE_CONFIG 0x0043#define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)44#define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)45#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2)46#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2)47#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2)48#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2)49#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2)50#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4)51#define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5)52#define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6)53#define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC BIT(7)54 55#define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x0456#define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff)57 58#define TEGRA186_GPIO_INPUT 0x0859#define TEGRA186_GPIO_INPUT_HIGH BIT(0)60 61#define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c62#define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)63 64#define TEGRA186_GPIO_OUTPUT_VALUE 0x1065#define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0)66 67#define TEGRA186_GPIO_INTERRUPT_CLEAR 0x1468 69#define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)70 71struct tegra_gpio_port {72 const char *name;73 unsigned int bank;74 unsigned int port;75 unsigned int pins;76};77 78struct tegra186_pin_range {79 unsigned int offset;80 const char *group;81};82 83struct tegra_gpio_soc {84 const struct tegra_gpio_port *ports;85 unsigned int num_ports;86 const char *name;87 unsigned int instance;88 89 unsigned int num_irqs_per_bank;90 91 const struct tegra186_pin_range *pin_ranges;92 unsigned int num_pin_ranges;93 const char *pinmux;94 bool has_gte;95 bool has_vm_support;96};97 98struct tegra_gpio {99 struct gpio_chip gpio;100 unsigned int num_irq;101 unsigned int *irq;102 103 const struct tegra_gpio_soc *soc;104 unsigned int num_irqs_per_bank;105 unsigned int num_banks;106 107 void __iomem *secure;108 void __iomem *base;109};110 111static const struct tegra_gpio_port *112tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin)113{114 unsigned int start = 0, i;115 116 for (i = 0; i < gpio->soc->num_ports; i++) {117 const struct tegra_gpio_port *port = &gpio->soc->ports[i];118 119 if (*pin >= start && *pin < start + port->pins) {120 *pin -= start;121 return port;122 }123 124 start += port->pins;125 }126 127 return NULL;128}129 130static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio,131 unsigned int pin)132{133 const struct tegra_gpio_port *port;134 unsigned int offset;135 136 port = tegra186_gpio_get_port(gpio, &pin);137 if (!port)138 return NULL;139 140 offset = port->bank * 0x1000 + port->port * 0x200;141 142 return gpio->base + offset + pin * 0x20;143}144 145static void __iomem *tegra186_gpio_get_secure_base(struct tegra_gpio *gpio,146 unsigned int pin)147{148 const struct tegra_gpio_port *port;149 unsigned int offset;150 151 port = tegra186_gpio_get_port(gpio, &pin);152 if (!port)153 return NULL;154 155 offset = port->bank * 0x1000 + port->port * TEGRA186_GPIO_SCR_PORT_SIZE;156 157 return gpio->secure + offset + pin * TEGRA186_GPIO_SCR_PIN_SIZE;158}159 160static inline bool tegra186_gpio_is_accessible(struct tegra_gpio *gpio, unsigned int pin)161{162 void __iomem *secure;163 u32 value;164 165 secure = tegra186_gpio_get_secure_base(gpio, pin);166 167 if (gpio->soc->has_vm_support) {168 value = readl(secure + TEGRA186_GPIO_VM);169 if ((value & TEGRA186_GPIO_VM_RW_MASK) != TEGRA186_GPIO_VM_RW_MASK)170 return false;171 }172 173 value = __raw_readl(secure + TEGRA186_GPIO_SCR);174 175 /*176 * When SCR_SEC_[R|W]EN is unset, then we have full read/write access to all the177 * registers for given GPIO pin.178 * When SCR_SEC[R|W]EN is set, then there is need to further check the accompanying179 * SCR_SEC_G1[R|W] bit to determine read/write access to all the registers for given180 * GPIO pin.181 */182 183 if (((value & TEGRA186_GPIO_SCR_SEC_REN) == 0 ||184 ((value & TEGRA186_GPIO_SCR_SEC_REN) && (value & TEGRA186_GPIO_SCR_SEC_G1R))) &&185 ((value & TEGRA186_GPIO_SCR_SEC_WEN) == 0 ||186 ((value & TEGRA186_GPIO_SCR_SEC_WEN) && (value & TEGRA186_GPIO_SCR_SEC_G1W))))187 return true;188 189 return false;190}191 192static int tegra186_init_valid_mask(struct gpio_chip *chip,193 unsigned long *valid_mask, unsigned int ngpios)194{195 struct tegra_gpio *gpio = gpiochip_get_data(chip);196 unsigned int j;197 198 for (j = 0; j < ngpios; j++) {199 if (!tegra186_gpio_is_accessible(gpio, j))200 clear_bit(j, valid_mask);201 }202 return 0;203}204 205static int tegra186_gpio_get_direction(struct gpio_chip *chip,206 unsigned int offset)207{208 struct tegra_gpio *gpio = gpiochip_get_data(chip);209 void __iomem *base;210 u32 value;211 212 base = tegra186_gpio_get_base(gpio, offset);213 if (WARN_ON(base == NULL))214 return -ENODEV;215 216 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);217 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)218 return GPIO_LINE_DIRECTION_OUT;219 220 return GPIO_LINE_DIRECTION_IN;221}222 223static int tegra186_gpio_direction_input(struct gpio_chip *chip,224 unsigned int offset)225{226 struct tegra_gpio *gpio = gpiochip_get_data(chip);227 void __iomem *base;228 u32 value;229 230 base = tegra186_gpio_get_base(gpio, offset);231 if (WARN_ON(base == NULL))232 return -ENODEV;233 234 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);235 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;236 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);237 238 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);239 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;240 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;241 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);242 243 return 0;244}245 246static int tegra186_gpio_direction_output(struct gpio_chip *chip,247 unsigned int offset, int level)248{249 struct tegra_gpio *gpio = gpiochip_get_data(chip);250 void __iomem *base;251 u32 value;252 253 /* configure output level first */254 chip->set(chip, offset, level);255 256 base = tegra186_gpio_get_base(gpio, offset);257 if (WARN_ON(base == NULL))258 return -EINVAL;259 260 /* set the direction */261 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);262 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;263 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);264 265 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);266 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;267 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;268 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);269 270 return 0;271}272 273#define HTE_BOTH_EDGES (HTE_RISING_EDGE_TS | HTE_FALLING_EDGE_TS)274 275static int tegra186_gpio_en_hw_ts(struct gpio_chip *gc, u32 offset,276 unsigned long flags)277{278 struct tegra_gpio *gpio;279 void __iomem *base;280 int value;281 282 if (!gc)283 return -EINVAL;284 285 gpio = gpiochip_get_data(gc);286 if (!gpio)287 return -ENODEV;288 289 base = tegra186_gpio_get_base(gpio, offset);290 if (WARN_ON(base == NULL))291 return -EINVAL;292 293 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);294 value |= TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC;295 296 if (flags == HTE_BOTH_EDGES) {297 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;298 } else if (flags == HTE_RISING_EDGE_TS) {299 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;300 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;301 } else if (flags == HTE_FALLING_EDGE_TS) {302 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;303 }304 305 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);306 307 return 0;308}309 310static int tegra186_gpio_dis_hw_ts(struct gpio_chip *gc, u32 offset,311 unsigned long flags)312{313 struct tegra_gpio *gpio;314 void __iomem *base;315 int value;316 317 if (!gc)318 return -EINVAL;319 320 gpio = gpiochip_get_data(gc);321 if (!gpio)322 return -ENODEV;323 324 base = tegra186_gpio_get_base(gpio, offset);325 if (WARN_ON(base == NULL))326 return -EINVAL;327 328 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);329 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC;330 if (flags == HTE_BOTH_EDGES) {331 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;332 } else if (flags == HTE_RISING_EDGE_TS) {333 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;334 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;335 } else if (flags == HTE_FALLING_EDGE_TS) {336 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;337 }338 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);339 340 return 0;341}342 343static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset)344{345 struct tegra_gpio *gpio = gpiochip_get_data(chip);346 void __iomem *base;347 u32 value;348 349 base = tegra186_gpio_get_base(gpio, offset);350 if (WARN_ON(base == NULL))351 return -ENODEV;352 353 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);354 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)355 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);356 else357 value = readl(base + TEGRA186_GPIO_INPUT);358 359 return value & BIT(0);360}361 362static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset,363 int level)364{365 struct tegra_gpio *gpio = gpiochip_get_data(chip);366 void __iomem *base;367 u32 value;368 369 base = tegra186_gpio_get_base(gpio, offset);370 if (WARN_ON(base == NULL))371 return;372 373 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);374 if (level == 0)375 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;376 else377 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;378 379 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);380}381 382static int tegra186_gpio_set_config(struct gpio_chip *chip,383 unsigned int offset,384 unsigned long config)385{386 struct tegra_gpio *gpio = gpiochip_get_data(chip);387 u32 debounce, value;388 void __iomem *base;389 390 base = tegra186_gpio_get_base(gpio, offset);391 if (base == NULL)392 return -ENXIO;393 394 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)395 return -ENOTSUPP;396 397 debounce = pinconf_to_config_argument(config);398 399 /*400 * The Tegra186 GPIO controller supports a maximum of 255 ms debounce401 * time.402 */403 if (debounce > 255000)404 return -EINVAL;405 406 debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC);407 408 value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce);409 writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL);410 411 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);412 value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE;413 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);414 415 return 0;416}417 418static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip)419{420 struct tegra_gpio *gpio = gpiochip_get_data(chip);421 struct pinctrl_dev *pctldev;422 struct device_node *np;423 unsigned int i, j;424 int err;425 426 if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0)427 return 0;428 429 np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux);430 if (!np)431 return -ENODEV;432 433 pctldev = of_pinctrl_get(np);434 of_node_put(np);435 if (!pctldev)436 return -EPROBE_DEFER;437 438 for (i = 0; i < gpio->soc->num_pin_ranges; i++) {439 unsigned int pin = gpio->soc->pin_ranges[i].offset, port;440 const char *group = gpio->soc->pin_ranges[i].group;441 442 port = pin / 8;443 pin = pin % 8;444 445 if (port >= gpio->soc->num_ports) {446 dev_warn(chip->parent, "invalid port %u for %s\n",447 port, group);448 continue;449 }450 451 for (j = 0; j < port; j++)452 pin += gpio->soc->ports[j].pins;453 454 err = gpiochip_add_pingroup_range(chip, pctldev, pin, group);455 if (err < 0)456 return err;457 }458 459 return 0;460}461 462static int tegra186_gpio_of_xlate(struct gpio_chip *chip,463 const struct of_phandle_args *spec,464 u32 *flags)465{466 struct tegra_gpio *gpio = gpiochip_get_data(chip);467 unsigned int port, pin, i, offset = 0;468 469 if (WARN_ON(chip->of_gpio_n_cells < 2))470 return -EINVAL;471 472 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells))473 return -EINVAL;474 475 port = spec->args[0] / 8;476 pin = spec->args[0] % 8;477 478 if (port >= gpio->soc->num_ports) {479 dev_err(chip->parent, "invalid port number: %u\n", port);480 return -EINVAL;481 }482 483 for (i = 0; i < port; i++)484 offset += gpio->soc->ports[i].pins;485 486 if (flags)487 *flags = spec->args[1];488 489 return offset + pin;490}491 492#define to_tegra_gpio(x) container_of((x), struct tegra_gpio, gpio)493 494static void tegra186_irq_ack(struct irq_data *data)495{496 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);497 struct tegra_gpio *gpio = to_tegra_gpio(gc);498 void __iomem *base;499 500 base = tegra186_gpio_get_base(gpio, data->hwirq);501 if (WARN_ON(base == NULL))502 return;503 504 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR);505}506 507static void tegra186_irq_mask(struct irq_data *data)508{509 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);510 struct tegra_gpio *gpio = to_tegra_gpio(gc);511 void __iomem *base;512 u32 value;513 514 base = tegra186_gpio_get_base(gpio, data->hwirq);515 if (WARN_ON(base == NULL))516 return;517 518 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);519 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;520 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);521 522 gpiochip_disable_irq(&gpio->gpio, data->hwirq);523}524 525static void tegra186_irq_unmask(struct irq_data *data)526{527 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);528 struct tegra_gpio *gpio = to_tegra_gpio(gc);529 void __iomem *base;530 u32 value;531 532 base = tegra186_gpio_get_base(gpio, data->hwirq);533 if (WARN_ON(base == NULL))534 return;535 536 gpiochip_enable_irq(&gpio->gpio, data->hwirq);537 538 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);539 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;540 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);541}542 543static int tegra186_irq_set_type(struct irq_data *data, unsigned int type)544{545 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);546 struct tegra_gpio *gpio = to_tegra_gpio(gc);547 void __iomem *base;548 u32 value;549 550 base = tegra186_gpio_get_base(gpio, data->hwirq);551 if (WARN_ON(base == NULL))552 return -ENODEV;553 554 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);555 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK;556 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;557 558 switch (type & IRQ_TYPE_SENSE_MASK) {559 case IRQ_TYPE_NONE:560 break;561 562 case IRQ_TYPE_EDGE_RISING:563 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;564 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;565 break;566 567 case IRQ_TYPE_EDGE_FALLING:568 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;569 break;570 571 case IRQ_TYPE_EDGE_BOTH:572 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;573 break;574 575 case IRQ_TYPE_LEVEL_HIGH:576 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;577 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;578 break;579 580 case IRQ_TYPE_LEVEL_LOW:581 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;582 break;583 584 default:585 return -EINVAL;586 }587 588 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);589 590 if ((type & IRQ_TYPE_EDGE_BOTH) == 0)591 irq_set_handler_locked(data, handle_level_irq);592 else593 irq_set_handler_locked(data, handle_edge_irq);594 595 if (data->parent_data)596 return irq_chip_set_type_parent(data, type);597 598 return 0;599}600 601static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on)602{603 if (data->parent_data)604 return irq_chip_set_wake_parent(data, on);605 606 return 0;607}608 609static void tegra186_irq_print_chip(struct irq_data *data, struct seq_file *p)610{611 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);612 613 seq_printf(p, dev_name(gc->parent));614}615 616static const struct irq_chip tegra186_gpio_irq_chip = {617 .irq_ack = tegra186_irq_ack,618 .irq_mask = tegra186_irq_mask,619 .irq_unmask = tegra186_irq_unmask,620 .irq_set_type = tegra186_irq_set_type,621 .irq_set_wake = tegra186_irq_set_wake,622 .irq_print_chip = tegra186_irq_print_chip,623 .flags = IRQCHIP_IMMUTABLE,624 GPIOCHIP_IRQ_RESOURCE_HELPERS,625};626 627static void tegra186_gpio_irq(struct irq_desc *desc)628{629 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc);630 struct irq_domain *domain = gpio->gpio.irq.domain;631 struct irq_chip *chip = irq_desc_get_chip(desc);632 unsigned int parent = irq_desc_get_irq(desc);633 unsigned int i, j, offset = 0;634 635 chained_irq_enter(chip, desc);636 637 for (i = 0; i < gpio->soc->num_ports; i++) {638 const struct tegra_gpio_port *port = &gpio->soc->ports[i];639 unsigned int pin;640 unsigned long value;641 void __iomem *base;642 643 base = gpio->base + port->bank * 0x1000 + port->port * 0x200;644 645 /* skip ports that are not associated with this bank */646 for (j = 0; j < gpio->num_irqs_per_bank; j++) {647 if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j])648 break;649 }650 651 if (j == gpio->num_irqs_per_bank)652 goto skip;653 654 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));655 656 for_each_set_bit(pin, &value, port->pins) {657 int ret = generic_handle_domain_irq(domain, offset + pin);658 WARN_RATELIMIT(ret, "hwirq = %d", offset + pin);659 }660 661skip:662 offset += port->pins;663 }664 665 chained_irq_exit(chip, desc);666}667 668static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain,669 struct irq_fwspec *fwspec,670 unsigned long *hwirq,671 unsigned int *type)672{673 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data);674 unsigned int port, pin, i, offset = 0;675 676 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2))677 return -EINVAL;678 679 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells))680 return -EINVAL;681 682 port = fwspec->param[0] / 8;683 pin = fwspec->param[0] % 8;684 685 if (port >= gpio->soc->num_ports)686 return -EINVAL;687 688 for (i = 0; i < port; i++)689 offset += gpio->soc->ports[i].pins;690 691 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;692 *hwirq = offset + pin;693 694 return 0;695}696 697static int tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip,698 union gpio_irq_fwspec *gfwspec,699 unsigned int parent_hwirq,700 unsigned int parent_type)701{702 struct tegra_gpio *gpio = gpiochip_get_data(chip);703 struct irq_fwspec *fwspec = &gfwspec->fwspec;704 705 fwspec->fwnode = chip->irq.parent_domain->fwnode;706 fwspec->param_count = 3;707 fwspec->param[0] = gpio->soc->instance;708 fwspec->param[1] = parent_hwirq;709 fwspec->param[2] = parent_type;710 711 return 0;712}713 714static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip,715 unsigned int hwirq,716 unsigned int type,717 unsigned int *parent_hwirq,718 unsigned int *parent_type)719{720 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);721 *parent_type = type;722 723 return 0;724}725 726static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip,727 unsigned int offset)728{729 struct tegra_gpio *gpio = gpiochip_get_data(chip);730 unsigned int i;731 732 for (i = 0; i < gpio->soc->num_ports; i++) {733 if (offset < gpio->soc->ports[i].pins)734 break;735 736 offset -= gpio->soc->ports[i].pins;737 }738 739 return offset + i * 8;740}741 742static const struct of_device_id tegra186_pmc_of_match[] = {743 { .compatible = "nvidia,tegra186-pmc" },744 { .compatible = "nvidia,tegra194-pmc" },745 { .compatible = "nvidia,tegra234-pmc" },746 { /* sentinel */ }747};748 749static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio)750{751 struct device *dev = gpio->gpio.parent;752 unsigned int i;753 u32 value;754 755 for (i = 0; i < gpio->soc->num_ports; i++) {756 const struct tegra_gpio_port *port = &gpio->soc->ports[i];757 unsigned int offset, p = port->port;758 void __iomem *base;759 760 base = gpio->secure + port->bank * 0x1000 + 0x800;761 762 value = readl(base + TEGRA186_GPIO_CTL_SCR);763 764 /*765 * For controllers that haven't been locked down yet, make766 * sure to program the default interrupt route mapping.767 */768 if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 &&769 (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) {770 /*771 * On Tegra194 and later, each pin can be routed to one or more772 * interrupts.773 */774 dev_dbg(dev, "programming default interrupt routing for port %s\n",775 port->name);776 777 offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, 0);778 779 /*780 * By default we only want to route GPIO pins to IRQ 0. This works781 * only under the assumption that we're running as the host kernel782 * and hence all GPIO pins are owned by Linux.783 *784 * For cases where Linux is the guest OS, the hypervisor will have785 * to configure the interrupt routing and pass only the valid786 * interrupts via device tree.787 */788 value = readl(base + offset);789 value = BIT(port->pins) - 1;790 writel(value, base + offset);791 }792 }793}794 795static unsigned int tegra186_gpio_irqs_per_bank(struct tegra_gpio *gpio)796{797 struct device *dev = gpio->gpio.parent;798 799 if (gpio->num_irq > gpio->num_banks) {800 if (gpio->num_irq % gpio->num_banks != 0)801 goto error;802 }803 804 if (gpio->num_irq < gpio->num_banks)805 goto error;806 807 gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks;808 809 if (gpio->num_irqs_per_bank > gpio->soc->num_irqs_per_bank)810 goto error;811 812 return 0;813 814error:815 dev_err(dev, "invalid number of interrupts (%u) for %u banks\n",816 gpio->num_irq, gpio->num_banks);817 return -EINVAL;818}819 820static int tegra186_gpio_probe(struct platform_device *pdev)821{822 unsigned int i, j, offset;823 struct gpio_irq_chip *irq;824 struct tegra_gpio *gpio;825 struct device_node *np;826 char **names;827 int err;828 829 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);830 if (!gpio)831 return -ENOMEM;832 833 gpio->soc = device_get_match_data(&pdev->dev);834 gpio->gpio.label = gpio->soc->name;835 gpio->gpio.parent = &pdev->dev;836 837 /* count the number of banks in the controller */838 for (i = 0; i < gpio->soc->num_ports; i++)839 if (gpio->soc->ports[i].bank > gpio->num_banks)840 gpio->num_banks = gpio->soc->ports[i].bank;841 842 gpio->num_banks++;843 844 /* get register apertures */845 gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security");846 if (IS_ERR(gpio->secure)) {847 gpio->secure = devm_platform_ioremap_resource(pdev, 0);848 if (IS_ERR(gpio->secure))849 return PTR_ERR(gpio->secure);850 }851 852 gpio->base = devm_platform_ioremap_resource_byname(pdev, "gpio");853 if (IS_ERR(gpio->base)) {854 gpio->base = devm_platform_ioremap_resource(pdev, 1);855 if (IS_ERR(gpio->base))856 return PTR_ERR(gpio->base);857 }858 859 err = platform_irq_count(pdev);860 if (err < 0)861 return err;862 863 gpio->num_irq = err;864 865 err = tegra186_gpio_irqs_per_bank(gpio);866 if (err < 0)867 return err;868 869 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq),870 GFP_KERNEL);871 if (!gpio->irq)872 return -ENOMEM;873 874 for (i = 0; i < gpio->num_irq; i++) {875 err = platform_get_irq(pdev, i);876 if (err < 0)877 return err;878 879 gpio->irq[i] = err;880 }881 882 gpio->gpio.request = gpiochip_generic_request;883 gpio->gpio.free = gpiochip_generic_free;884 gpio->gpio.get_direction = tegra186_gpio_get_direction;885 gpio->gpio.direction_input = tegra186_gpio_direction_input;886 gpio->gpio.direction_output = tegra186_gpio_direction_output;887 gpio->gpio.get = tegra186_gpio_get;888 gpio->gpio.set = tegra186_gpio_set;889 gpio->gpio.set_config = tegra186_gpio_set_config;890 gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges;891 gpio->gpio.init_valid_mask = tegra186_init_valid_mask;892 if (gpio->soc->has_gte) {893 gpio->gpio.en_hw_timestamp = tegra186_gpio_en_hw_ts;894 gpio->gpio.dis_hw_timestamp = tegra186_gpio_dis_hw_ts;895 }896 897 gpio->gpio.base = -1;898 899 for (i = 0; i < gpio->soc->num_ports; i++)900 gpio->gpio.ngpio += gpio->soc->ports[i].pins;901 902 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio,903 sizeof(*names), GFP_KERNEL);904 if (!names)905 return -ENOMEM;906 907 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {908 const struct tegra_gpio_port *port = &gpio->soc->ports[i];909 char *name;910 911 for (j = 0; j < port->pins; j++) {912 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL,913 "P%s.%02x", port->name, j);914 if (!name)915 return -ENOMEM;916 917 names[offset + j] = name;918 }919 920 offset += port->pins;921 }922 923 gpio->gpio.names = (const char * const *)names;924 925#if defined(CONFIG_OF_GPIO)926 gpio->gpio.of_gpio_n_cells = 2;927 gpio->gpio.of_xlate = tegra186_gpio_of_xlate;928#endif /* CONFIG_OF_GPIO */929 930 irq = &gpio->gpio.irq;931 gpio_irq_chip_set_chip(irq, &tegra186_gpio_irq_chip);932 irq->fwnode = dev_fwnode(&pdev->dev);933 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq;934 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec;935 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq;936 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate;937 irq->handler = handle_simple_irq;938 irq->default_type = IRQ_TYPE_NONE;939 irq->parent_handler = tegra186_gpio_irq;940 irq->parent_handler_data = gpio;941 irq->num_parents = gpio->num_irq;942 943 /*944 * To simplify things, use a single interrupt per bank for now. Some945 * chips support up to 8 interrupts per bank, which can be useful to946 * distribute the load and decrease the processing latency for GPIOs947 * but it also requires a more complicated interrupt routing than we948 * currently program.949 */950 if (gpio->num_irqs_per_bank > 1) {951 irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks,952 sizeof(*irq->parents), GFP_KERNEL);953 if (!irq->parents)954 return -ENOMEM;955 956 for (i = 0; i < gpio->num_banks; i++)957 irq->parents[i] = gpio->irq[i * gpio->num_irqs_per_bank];958 959 irq->num_parents = gpio->num_banks;960 } else {961 irq->num_parents = gpio->num_irq;962 irq->parents = gpio->irq;963 }964 965 if (gpio->soc->num_irqs_per_bank > 1)966 tegra186_gpio_init_route_mapping(gpio);967 968 np = of_find_matching_node(NULL, tegra186_pmc_of_match);969 if (np) {970 if (of_device_is_available(np)) {971 irq->parent_domain = irq_find_host(np);972 of_node_put(np);973 974 if (!irq->parent_domain)975 return -EPROBE_DEFER;976 } else {977 of_node_put(np);978 }979 }980 981 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio,982 sizeof(*irq->map), GFP_KERNEL);983 if (!irq->map)984 return -ENOMEM;985 986 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {987 const struct tegra_gpio_port *port = &gpio->soc->ports[i];988 989 for (j = 0; j < port->pins; j++)990 irq->map[offset + j] = irq->parents[port->bank];991 992 offset += port->pins;993 }994 995 return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio);996}997 998#define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \999 [TEGRA186_MAIN_GPIO_PORT_##_name] = { \1000 .name = #_name, \1001 .bank = _bank, \1002 .port = _port, \1003 .pins = _pins, \1004 }1005 1006static const struct tegra_gpio_port tegra186_main_ports[] = {1007 TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7),1008 TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7),1009 TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7),1010 TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6),1011 TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8),1012 TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6),1013 TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6),1014 TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7),1015 TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8),1016 TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8),1017 TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1),1018 TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8),1019 TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6),1020 TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7),1021 TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4),1022 TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7),1023 TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6),1024 TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6),1025 TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4),1026 TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8),1027 TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7),1028 TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2),1029 TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4),1030};1031 1032static const struct tegra_gpio_soc tegra186_main_soc = {1033 .num_ports = ARRAY_SIZE(tegra186_main_ports),1034 .ports = tegra186_main_ports,1035 .name = "tegra186-gpio",1036 .instance = 0,1037 .num_irqs_per_bank = 1,1038 .has_vm_support = false,1039};1040 1041#define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \1042 [TEGRA186_AON_GPIO_PORT_##_name] = { \1043 .name = #_name, \1044 .bank = _bank, \1045 .port = _port, \1046 .pins = _pins, \1047 }1048 1049static const struct tegra_gpio_port tegra186_aon_ports[] = {1050 TEGRA186_AON_GPIO_PORT( S, 0, 1, 5),1051 TEGRA186_AON_GPIO_PORT( U, 0, 2, 6),1052 TEGRA186_AON_GPIO_PORT( V, 0, 4, 8),1053 TEGRA186_AON_GPIO_PORT( W, 0, 5, 8),1054 TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4),1055 TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8),1056 TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3),1057 TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5),1058};1059 1060static const struct tegra_gpio_soc tegra186_aon_soc = {1061 .num_ports = ARRAY_SIZE(tegra186_aon_ports),1062 .ports = tegra186_aon_ports,1063 .name = "tegra186-gpio-aon",1064 .instance = 1,1065 .num_irqs_per_bank = 1,1066 .has_vm_support = false,1067};1068 1069#define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \1070 [TEGRA194_MAIN_GPIO_PORT_##_name] = { \1071 .name = #_name, \1072 .bank = _bank, \1073 .port = _port, \1074 .pins = _pins, \1075 }1076 1077static const struct tegra_gpio_port tegra194_main_ports[] = {1078 TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8),1079 TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2),1080 TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8),1081 TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4),1082 TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8),1083 TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6),1084 TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8),1085 TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8),1086 TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5),1087 TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6),1088 TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8),1089 TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4),1090 TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8),1091 TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3),1092 TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6),1093 TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8),1094 TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8),1095 TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6),1096 TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8),1097 TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8),1098 TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1),1099 TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8),1100 TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2),1101 TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8),1102 TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8),1103 TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8),1104 TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2),1105 TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2)1106};1107 1108static const struct tegra186_pin_range tegra194_main_pin_ranges[] = {1109 { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" },1110 { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" },1111};1112 1113static const struct tegra_gpio_soc tegra194_main_soc = {1114 .num_ports = ARRAY_SIZE(tegra194_main_ports),1115 .ports = tegra194_main_ports,1116 .name = "tegra194-gpio",1117 .instance = 0,1118 .num_irqs_per_bank = 8,1119 .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges),1120 .pin_ranges = tegra194_main_pin_ranges,1121 .pinmux = "nvidia,tegra194-pinmux",1122 .has_vm_support = true,1123};1124 1125#define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \1126 [TEGRA194_AON_GPIO_PORT_##_name] = { \1127 .name = #_name, \1128 .bank = _bank, \1129 .port = _port, \1130 .pins = _pins, \1131 }1132 1133static const struct tegra_gpio_port tegra194_aon_ports[] = {1134 TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8),1135 TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4),1136 TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8),1137 TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3),1138 TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7)1139};1140 1141static const struct tegra_gpio_soc tegra194_aon_soc = {1142 .num_ports = ARRAY_SIZE(tegra194_aon_ports),1143 .ports = tegra194_aon_ports,1144 .name = "tegra194-gpio-aon",1145 .instance = 1,1146 .num_irqs_per_bank = 8,1147 .has_gte = true,1148 .has_vm_support = false,1149};1150 1151#define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \1152 [TEGRA234_MAIN_GPIO_PORT_##_name] = { \1153 .name = #_name, \1154 .bank = _bank, \1155 .port = _port, \1156 .pins = _pins, \1157 }1158 1159static const struct tegra_gpio_port tegra234_main_ports[] = {1160 TEGRA234_MAIN_GPIO_PORT( A, 0, 0, 8),1161 TEGRA234_MAIN_GPIO_PORT( B, 0, 3, 1),1162 TEGRA234_MAIN_GPIO_PORT( C, 5, 1, 8),1163 TEGRA234_MAIN_GPIO_PORT( D, 5, 2, 4),1164 TEGRA234_MAIN_GPIO_PORT( E, 5, 3, 8),1165 TEGRA234_MAIN_GPIO_PORT( F, 5, 4, 6),1166 TEGRA234_MAIN_GPIO_PORT( G, 4, 0, 8),1167 TEGRA234_MAIN_GPIO_PORT( H, 4, 1, 8),1168 TEGRA234_MAIN_GPIO_PORT( I, 4, 2, 7),1169 TEGRA234_MAIN_GPIO_PORT( J, 5, 0, 6),1170 TEGRA234_MAIN_GPIO_PORT( K, 3, 0, 8),1171 TEGRA234_MAIN_GPIO_PORT( L, 3, 1, 4),1172 TEGRA234_MAIN_GPIO_PORT( M, 2, 0, 8),1173 TEGRA234_MAIN_GPIO_PORT( N, 2, 1, 8),1174 TEGRA234_MAIN_GPIO_PORT( P, 2, 2, 8),1175 TEGRA234_MAIN_GPIO_PORT( Q, 2, 3, 8),1176 TEGRA234_MAIN_GPIO_PORT( R, 2, 4, 6),1177 TEGRA234_MAIN_GPIO_PORT( X, 1, 0, 8),1178 TEGRA234_MAIN_GPIO_PORT( Y, 1, 1, 8),1179 TEGRA234_MAIN_GPIO_PORT( Z, 1, 2, 8),1180 TEGRA234_MAIN_GPIO_PORT(AC, 0, 1, 8),1181 TEGRA234_MAIN_GPIO_PORT(AD, 0, 2, 4),1182 TEGRA234_MAIN_GPIO_PORT(AE, 3, 3, 2),1183 TEGRA234_MAIN_GPIO_PORT(AF, 3, 4, 4),1184 TEGRA234_MAIN_GPIO_PORT(AG, 3, 2, 8),1185};1186 1187static const struct tegra_gpio_soc tegra234_main_soc = {1188 .num_ports = ARRAY_SIZE(tegra234_main_ports),1189 .ports = tegra234_main_ports,1190 .name = "tegra234-gpio",1191 .instance = 0,1192 .num_irqs_per_bank = 8,1193 .has_vm_support = true,1194};1195 1196#define TEGRA234_AON_GPIO_PORT(_name, _bank, _port, _pins) \1197 [TEGRA234_AON_GPIO_PORT_##_name] = { \1198 .name = #_name, \1199 .bank = _bank, \1200 .port = _port, \1201 .pins = _pins, \1202 }1203 1204static const struct tegra_gpio_port tegra234_aon_ports[] = {1205 TEGRA234_AON_GPIO_PORT(AA, 0, 4, 8),1206 TEGRA234_AON_GPIO_PORT(BB, 0, 5, 4),1207 TEGRA234_AON_GPIO_PORT(CC, 0, 2, 8),1208 TEGRA234_AON_GPIO_PORT(DD, 0, 3, 3),1209 TEGRA234_AON_GPIO_PORT(EE, 0, 0, 8),1210 TEGRA234_AON_GPIO_PORT(GG, 0, 1, 1),1211};1212 1213static const struct tegra_gpio_soc tegra234_aon_soc = {1214 .num_ports = ARRAY_SIZE(tegra234_aon_ports),1215 .ports = tegra234_aon_ports,1216 .name = "tegra234-gpio-aon",1217 .instance = 1,1218 .num_irqs_per_bank = 8,1219 .has_gte = true,1220 .has_vm_support = false,1221};1222 1223#define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \1224 [TEGRA241_MAIN_GPIO_PORT_##_name] = { \1225 .name = #_name, \1226 .bank = _bank, \1227 .port = _port, \1228 .pins = _pins, \1229 }1230 1231static const struct tegra_gpio_port tegra241_main_ports[] = {1232 TEGRA241_MAIN_GPIO_PORT(A, 0, 0, 8),1233 TEGRA241_MAIN_GPIO_PORT(B, 0, 1, 8),1234 TEGRA241_MAIN_GPIO_PORT(C, 0, 2, 2),1235 TEGRA241_MAIN_GPIO_PORT(D, 0, 3, 6),1236 TEGRA241_MAIN_GPIO_PORT(E, 0, 4, 8),1237 TEGRA241_MAIN_GPIO_PORT(F, 1, 0, 8),1238 TEGRA241_MAIN_GPIO_PORT(G, 1, 1, 8),1239 TEGRA241_MAIN_GPIO_PORT(H, 1, 2, 8),1240 TEGRA241_MAIN_GPIO_PORT(J, 1, 3, 8),1241 TEGRA241_MAIN_GPIO_PORT(K, 1, 4, 4),1242 TEGRA241_MAIN_GPIO_PORT(L, 1, 5, 6),1243};1244 1245static const struct tegra_gpio_soc tegra241_main_soc = {1246 .num_ports = ARRAY_SIZE(tegra241_main_ports),1247 .ports = tegra241_main_ports,1248 .name = "tegra241-gpio",1249 .instance = 0,1250 .num_irqs_per_bank = 8,1251 .has_vm_support = false,1252};1253 1254#define TEGRA241_AON_GPIO_PORT(_name, _bank, _port, _pins) \1255 [TEGRA241_AON_GPIO_PORT_##_name] = { \1256 .name = #_name, \1257 .bank = _bank, \1258 .port = _port, \1259 .pins = _pins, \1260 }1261 1262static const struct tegra_gpio_port tegra241_aon_ports[] = {1263 TEGRA241_AON_GPIO_PORT(AA, 0, 0, 8),1264 TEGRA241_AON_GPIO_PORT(BB, 0, 0, 4),1265};1266 1267static const struct tegra_gpio_soc tegra241_aon_soc = {1268 .num_ports = ARRAY_SIZE(tegra241_aon_ports),1269 .ports = tegra241_aon_ports,1270 .name = "tegra241-gpio-aon",1271 .instance = 1,1272 .num_irqs_per_bank = 8,1273 .has_vm_support = false,1274};1275 1276static const struct of_device_id tegra186_gpio_of_match[] = {1277 {1278 .compatible = "nvidia,tegra186-gpio",1279 .data = &tegra186_main_soc1280 }, {1281 .compatible = "nvidia,tegra186-gpio-aon",1282 .data = &tegra186_aon_soc1283 }, {1284 .compatible = "nvidia,tegra194-gpio",1285 .data = &tegra194_main_soc1286 }, {1287 .compatible = "nvidia,tegra194-gpio-aon",1288 .data = &tegra194_aon_soc1289 }, {1290 .compatible = "nvidia,tegra234-gpio",1291 .data = &tegra234_main_soc1292 }, {1293 .compatible = "nvidia,tegra234-gpio-aon",1294 .data = &tegra234_aon_soc1295 }, {1296 /* sentinel */1297 }1298};1299MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match);1300 1301static const struct acpi_device_id tegra186_gpio_acpi_match[] = {1302 { .id = "NVDA0108", .driver_data = (kernel_ulong_t)&tegra186_main_soc },1303 { .id = "NVDA0208", .driver_data = (kernel_ulong_t)&tegra186_aon_soc },1304 { .id = "NVDA0308", .driver_data = (kernel_ulong_t)&tegra194_main_soc },1305 { .id = "NVDA0408", .driver_data = (kernel_ulong_t)&tegra194_aon_soc },1306 { .id = "NVDA0508", .driver_data = (kernel_ulong_t)&tegra241_main_soc },1307 { .id = "NVDA0608", .driver_data = (kernel_ulong_t)&tegra241_aon_soc },1308 {}1309};1310MODULE_DEVICE_TABLE(acpi, tegra186_gpio_acpi_match);1311 1312static struct platform_driver tegra186_gpio_driver = {1313 .driver = {1314 .name = "tegra186-gpio",1315 .of_match_table = tegra186_gpio_of_match,1316 .acpi_match_table = tegra186_gpio_acpi_match,1317 },1318 .probe = tegra186_gpio_probe,1319};1320module_platform_driver(tegra186_gpio_driver);1321 1322MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver");1323MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");1324MODULE_LICENSE("GPL v2");1325