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1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * Xilinx Zynq GPIO device driver4 *5 * Copyright (C) 2009 - 2014 Xilinx, Inc.6 */7 8#include <linux/bitops.h>9#include <linux/clk.h>10#include <linux/gpio/driver.h>11#include <linux/init.h>12#include <linux/interrupt.h>13#include <linux/spinlock.h>14#include <linux/io.h>15#include <linux/module.h>16#include <linux/platform_device.h>17#include <linux/pm_runtime.h>18#include <linux/of.h>19 20#define DRIVER_NAME "zynq-gpio"21 22/* Maximum banks */23#define ZYNQ_GPIO_MAX_BANK 424#define ZYNQMP_GPIO_MAX_BANK 625#define VERSAL_GPIO_MAX_BANK 426#define PMC_GPIO_MAX_BANK 527#define VERSAL_UNUSED_BANKS 228 29#define ZYNQ_GPIO_BANK0_NGPIO 3230#define ZYNQ_GPIO_BANK1_NGPIO 2231#define ZYNQ_GPIO_BANK2_NGPIO 3232#define ZYNQ_GPIO_BANK3_NGPIO 3233 34#define ZYNQMP_GPIO_BANK0_NGPIO 2635#define ZYNQMP_GPIO_BANK1_NGPIO 2636#define ZYNQMP_GPIO_BANK2_NGPIO 2637#define ZYNQMP_GPIO_BANK3_NGPIO 3238#define ZYNQMP_GPIO_BANK4_NGPIO 3239#define ZYNQMP_GPIO_BANK5_NGPIO 3240 41#define ZYNQ_GPIO_NR_GPIOS 11842#define ZYNQMP_GPIO_NR_GPIOS 17443 44#define ZYNQ_GPIO_BANK0_PIN_MIN(str) 045#define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)47#define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)48#define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)50#define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)51#define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)53#define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)54#define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)56#define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)57#define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)59#define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)60#define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)62 63/* Register offsets for the GPIO device */64/* LSW Mask & Data -WO */65#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))66/* MSW Mask & Data -WO */67#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))68/* Data Register-RW */69#define ZYNQ_GPIO_DATA_OFFSET(BANK) (0x040 + (4 * BANK))70#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))71/* Direction mode reg-RW */72#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))73/* Output enable reg-RW */74#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))75/* Interrupt mask reg-RO */76#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))77/* Interrupt enable reg-WO */78#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))79/* Interrupt disable reg-WO */80#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))81/* Interrupt status reg-RO */82#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))83/* Interrupt type reg-RW */84#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))85/* Interrupt polarity reg-RW */86#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))87/* Interrupt on any, reg-RW */88#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))89 90/* Disable all interrupts mask */91#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF92 93/* Mid pin number of a bank */94#define ZYNQ_GPIO_MID_PIN_NUM 1695 96/* GPIO upper 16 bit mask */97#define ZYNQ_GPIO_UPPER_MASK 0xFFFF000098 99/* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */100#define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0)101#define GPIO_QUIRK_DATA_RO_BUG BIT(1)102#define GPIO_QUIRK_VERSAL BIT(2)103 104struct gpio_regs {105 u32 datamsw[ZYNQMP_GPIO_MAX_BANK];106 u32 datalsw[ZYNQMP_GPIO_MAX_BANK];107 u32 dirm[ZYNQMP_GPIO_MAX_BANK];108 u32 outen[ZYNQMP_GPIO_MAX_BANK];109 u32 int_en[ZYNQMP_GPIO_MAX_BANK];110 u32 int_dis[ZYNQMP_GPIO_MAX_BANK];111 u32 int_type[ZYNQMP_GPIO_MAX_BANK];112 u32 int_polarity[ZYNQMP_GPIO_MAX_BANK];113 u32 int_any[ZYNQMP_GPIO_MAX_BANK];114};115 116/**117 * struct zynq_gpio - gpio device private data structure118 * @chip: instance of the gpio_chip119 * @base_addr: base address of the GPIO device120 * @clk: clock resource for this controller121 * @irq: interrupt for the GPIO device122 * @p_data: pointer to platform data123 * @context: context registers124 * @dirlock: lock used for direction in/out synchronization125 */126struct zynq_gpio {127 struct gpio_chip chip;128 void __iomem *base_addr;129 struct clk *clk;130 int irq;131 const struct zynq_platform_data *p_data;132 struct gpio_regs context;133 spinlock_t dirlock; /* lock */134};135 136/**137 * struct zynq_platform_data - zynq gpio platform data structure138 * @label: string to store in gpio->label139 * @quirks: Flags is used to identify the platform140 * @ngpio: max number of gpio pins141 * @max_bank: maximum number of gpio banks142 * @bank_min: this array represents bank's min pin143 * @bank_max: this array represents bank's max pin144 */145struct zynq_platform_data {146 const char *label;147 u32 quirks;148 u16 ngpio;149 int max_bank;150 int bank_min[ZYNQMP_GPIO_MAX_BANK];151 int bank_max[ZYNQMP_GPIO_MAX_BANK];152};153 154static const struct irq_chip zynq_gpio_level_irqchip;155static const struct irq_chip zynq_gpio_edge_irqchip;156 157/**158 * zynq_gpio_is_zynq - test if HW is zynq or zynqmp159 * @gpio: Pointer to driver data struct160 *161 * Return: 0 if zynqmp, 1 if zynq.162 */163static int zynq_gpio_is_zynq(struct zynq_gpio *gpio)164{165 return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ);166}167 168/**169 * gpio_data_ro_bug - test if HW bug exists or not170 * @gpio: Pointer to driver data struct171 *172 * Return: 0 if bug doesnot exist, 1 if bug exists.173 */174static int gpio_data_ro_bug(struct zynq_gpio *gpio)175{176 return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG);177}178 179/**180 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank181 * for a given pin in the GPIO device182 * @pin_num: gpio pin number within the device183 * @bank_num: an output parameter used to return the bank number of the gpio184 * pin185 * @bank_pin_num: an output parameter used to return pin number within a bank186 * for the given gpio pin187 * @gpio: gpio device data structure188 *189 * Returns the bank number and pin offset within the bank.190 */191static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,192 unsigned int *bank_num,193 unsigned int *bank_pin_num,194 struct zynq_gpio *gpio)195{196 int bank;197 198 for (bank = 0; bank < gpio->p_data->max_bank; bank++) {199 if ((pin_num >= gpio->p_data->bank_min[bank]) &&200 (pin_num <= gpio->p_data->bank_max[bank])) {201 *bank_num = bank;202 *bank_pin_num = pin_num -203 gpio->p_data->bank_min[bank];204 return;205 }206 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)207 bank = bank + VERSAL_UNUSED_BANKS;208 }209 210 /* default */211 WARN(true, "invalid GPIO pin number: %u", pin_num);212 *bank_num = 0;213 *bank_pin_num = 0;214}215 216/**217 * zynq_gpio_get_value - Get the state of the specified pin of GPIO device218 * @chip: gpio_chip instance to be worked on219 * @pin: gpio pin number within the device220 *221 * This function reads the state of the specified pin of the GPIO device.222 *223 * Return: 0 if the pin is low, 1 if pin is high.224 */225static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin)226{227 u32 data;228 unsigned int bank_num, bank_pin_num;229 struct zynq_gpio *gpio = gpiochip_get_data(chip);230 231 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);232 233 if (gpio_data_ro_bug(gpio)) {234 if (zynq_gpio_is_zynq(gpio)) {235 if (bank_num <= 1) {236 data = readl_relaxed(gpio->base_addr +237 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));238 } else {239 data = readl_relaxed(gpio->base_addr +240 ZYNQ_GPIO_DATA_OFFSET(bank_num));241 }242 } else {243 if (bank_num <= 2) {244 data = readl_relaxed(gpio->base_addr +245 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));246 } else {247 data = readl_relaxed(gpio->base_addr +248 ZYNQ_GPIO_DATA_OFFSET(bank_num));249 }250 }251 } else {252 data = readl_relaxed(gpio->base_addr +253 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));254 }255 return (data >> bank_pin_num) & 1;256}257 258/**259 * zynq_gpio_set_value - Modify the state of the pin with specified value260 * @chip: gpio_chip instance to be worked on261 * @pin: gpio pin number within the device262 * @state: value used to modify the state of the specified pin263 *264 * This function calculates the register offset (i.e to lower 16 bits or265 * upper 16 bits) based on the given pin number and sets the state of a266 * gpio pin to the specified value. The state is either 0 or non-zero.267 */268static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,269 int state)270{271 unsigned int reg_offset, bank_num, bank_pin_num;272 struct zynq_gpio *gpio = gpiochip_get_data(chip);273 274 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);275 276 if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {277 /* only 16 data bits in bit maskable reg */278 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;279 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);280 } else {281 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);282 }283 284 /*285 * get the 32 bit value to be written to the mask/data register where286 * the upper 16 bits is the mask and lower 16 bits is the data287 */288 state = !!state;289 state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &290 ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);291 292 writel_relaxed(state, gpio->base_addr + reg_offset);293}294 295/**296 * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input297 * @chip: gpio_chip instance to be worked on298 * @pin: gpio pin number within the device299 *300 * This function uses the read-modify-write sequence to set the direction of301 * the gpio pin as input.302 *303 * Return: 0 always304 */305static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)306{307 u32 reg;308 unsigned int bank_num, bank_pin_num;309 unsigned long flags;310 struct zynq_gpio *gpio = gpiochip_get_data(chip);311 312 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);313 314 /*315 * On zynq bank 0 pins 7 and 8 are special and cannot be used316 * as inputs.317 */318 if (zynq_gpio_is_zynq(gpio) && bank_num == 0 &&319 (bank_pin_num == 7 || bank_pin_num == 8))320 return -EINVAL;321 322 /* clear the bit in direction mode reg to set the pin as input */323 spin_lock_irqsave(&gpio->dirlock, flags);324 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));325 reg &= ~BIT(bank_pin_num);326 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));327 spin_unlock_irqrestore(&gpio->dirlock, flags);328 329 return 0;330}331 332/**333 * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output334 * @chip: gpio_chip instance to be worked on335 * @pin: gpio pin number within the device336 * @state: value to be written to specified pin337 *338 * This function sets the direction of specified GPIO pin as output, configures339 * the Output Enable register for the pin and uses zynq_gpio_set to set340 * the state of the pin to the value specified.341 *342 * Return: 0 always343 */344static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,345 int state)346{347 u32 reg;348 unsigned int bank_num, bank_pin_num;349 unsigned long flags;350 struct zynq_gpio *gpio = gpiochip_get_data(chip);351 352 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);353 354 /* set the GPIO pin as output */355 spin_lock_irqsave(&gpio->dirlock, flags);356 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));357 reg |= BIT(bank_pin_num);358 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));359 360 /* configure the output enable reg for the pin */361 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));362 reg |= BIT(bank_pin_num);363 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));364 spin_unlock_irqrestore(&gpio->dirlock, flags);365 366 /* set the state of the pin */367 zynq_gpio_set_value(chip, pin, state);368 return 0;369}370 371/**372 * zynq_gpio_get_direction - Read the direction of the specified GPIO pin373 * @chip: gpio_chip instance to be worked on374 * @pin: gpio pin number within the device375 *376 * This function returns the direction of the specified GPIO.377 *378 * Return: GPIO_LINE_DIRECTION_OUT or GPIO_LINE_DIRECTION_IN379 */380static int zynq_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)381{382 u32 reg;383 unsigned int bank_num, bank_pin_num;384 struct zynq_gpio *gpio = gpiochip_get_data(chip);385 386 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);387 388 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));389 390 if (reg & BIT(bank_pin_num))391 return GPIO_LINE_DIRECTION_OUT;392 393 return GPIO_LINE_DIRECTION_IN;394}395 396/**397 * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin398 * @irq_data: per irq and chip data passed down to chip functions399 *400 * This function calculates gpio pin number from irq number and sets the401 * bit in the Interrupt Disable register of the corresponding bank to disable402 * interrupts for that pin.403 */404static void zynq_gpio_irq_mask(struct irq_data *irq_data)405{406 unsigned int device_pin_num, bank_num, bank_pin_num;407 const unsigned long offset = irqd_to_hwirq(irq_data);408 struct gpio_chip *chip = irq_data_get_irq_chip_data(irq_data);409 struct zynq_gpio *gpio =410 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));411 412 gpiochip_disable_irq(chip, offset);413 device_pin_num = irq_data->hwirq;414 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);415 writel_relaxed(BIT(bank_pin_num),416 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));417}418 419/**420 * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin421 * @irq_data: irq data containing irq number of gpio pin for the interrupt422 * to enable423 *424 * This function calculates the gpio pin number from irq number and sets the425 * bit in the Interrupt Enable register of the corresponding bank to enable426 * interrupts for that pin.427 */428static void zynq_gpio_irq_unmask(struct irq_data *irq_data)429{430 unsigned int device_pin_num, bank_num, bank_pin_num;431 const unsigned long offset = irqd_to_hwirq(irq_data);432 struct gpio_chip *chip = irq_data_get_irq_chip_data(irq_data);433 struct zynq_gpio *gpio =434 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));435 436 gpiochip_enable_irq(chip, offset);437 device_pin_num = irq_data->hwirq;438 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);439 writel_relaxed(BIT(bank_pin_num),440 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));441}442 443/**444 * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin445 * @irq_data: irq data containing irq number of gpio pin for the interrupt446 * to ack447 *448 * This function calculates gpio pin number from irq number and sets the bit449 * in the Interrupt Status Register of the corresponding bank, to ACK the irq.450 */451static void zynq_gpio_irq_ack(struct irq_data *irq_data)452{453 unsigned int device_pin_num, bank_num, bank_pin_num;454 struct zynq_gpio *gpio =455 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));456 457 device_pin_num = irq_data->hwirq;458 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);459 writel_relaxed(BIT(bank_pin_num),460 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));461}462 463/**464 * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin465 * @irq_data: irq data containing irq number of gpio pin for the interrupt466 * to enable467 *468 * Clears the INTSTS bit and unmasks the given interrupt.469 */470static void zynq_gpio_irq_enable(struct irq_data *irq_data)471{472 /*473 * The Zynq GPIO controller does not disable interrupt detection when474 * the interrupt is masked and only disables the propagation of the475 * interrupt. This means when the controller detects an interrupt476 * condition while the interrupt is logically disabled it will propagate477 * that interrupt event once the interrupt is enabled. This will cause478 * the interrupt consumer to see spurious interrupts to prevent this479 * first make sure that the interrupt is not asserted and then enable480 * it.481 */482 zynq_gpio_irq_ack(irq_data);483 zynq_gpio_irq_unmask(irq_data);484}485 486/**487 * zynq_gpio_set_irq_type - Set the irq type for a gpio pin488 * @irq_data: irq data containing irq number of gpio pin489 * @type: interrupt type that is to be set for the gpio pin490 *491 * This function gets the gpio pin number and its bank from the gpio pin number492 * and configures the INT_TYPE, INT_POLARITY and INT_ANY registers.493 *494 * Return: 0, negative error otherwise.495 * TYPE-EDGE_RISING, INT_TYPE - 1, INT_POLARITY - 1, INT_ANY - 0;496 * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0, INT_ANY - 0;497 * TYPE-EDGE_BOTH, INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1;498 * TYPE-LEVEL_HIGH, INT_TYPE - 0, INT_POLARITY - 1, INT_ANY - NA;499 * TYPE-LEVEL_LOW, INT_TYPE - 0, INT_POLARITY - 0, INT_ANY - NA500 */501static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)502{503 u32 int_type, int_pol, int_any;504 unsigned int device_pin_num, bank_num, bank_pin_num;505 struct zynq_gpio *gpio =506 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));507 508 device_pin_num = irq_data->hwirq;509 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);510 511 int_type = readl_relaxed(gpio->base_addr +512 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));513 int_pol = readl_relaxed(gpio->base_addr +514 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));515 int_any = readl_relaxed(gpio->base_addr +516 ZYNQ_GPIO_INTANY_OFFSET(bank_num));517 518 /*519 * based on the type requested, configure the INT_TYPE, INT_POLARITY520 * and INT_ANY registers521 */522 switch (type) {523 case IRQ_TYPE_EDGE_RISING:524 int_type |= BIT(bank_pin_num);525 int_pol |= BIT(bank_pin_num);526 int_any &= ~BIT(bank_pin_num);527 break;528 case IRQ_TYPE_EDGE_FALLING:529 int_type |= BIT(bank_pin_num);530 int_pol &= ~BIT(bank_pin_num);531 int_any &= ~BIT(bank_pin_num);532 break;533 case IRQ_TYPE_EDGE_BOTH:534 int_type |= BIT(bank_pin_num);535 int_any |= BIT(bank_pin_num);536 break;537 case IRQ_TYPE_LEVEL_HIGH:538 int_type &= ~BIT(bank_pin_num);539 int_pol |= BIT(bank_pin_num);540 break;541 case IRQ_TYPE_LEVEL_LOW:542 int_type &= ~BIT(bank_pin_num);543 int_pol &= ~BIT(bank_pin_num);544 break;545 default:546 return -EINVAL;547 }548 549 writel_relaxed(int_type,550 gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));551 writel_relaxed(int_pol,552 gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));553 writel_relaxed(int_any,554 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));555 556 if (type & IRQ_TYPE_LEVEL_MASK)557 irq_set_chip_handler_name_locked(irq_data,558 &zynq_gpio_level_irqchip,559 handle_fasteoi_irq, NULL);560 else561 irq_set_chip_handler_name_locked(irq_data,562 &zynq_gpio_edge_irqchip,563 handle_level_irq, NULL);564 565 return 0;566}567 568static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on)569{570 struct zynq_gpio *gpio =571 gpiochip_get_data(irq_data_get_irq_chip_data(data));572 573 irq_set_irq_wake(gpio->irq, on);574 575 return 0;576}577 578static int zynq_gpio_irq_reqres(struct irq_data *d)579{580 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);581 int ret;582 583 ret = pm_runtime_resume_and_get(chip->parent);584 if (ret < 0)585 return ret;586 587 return gpiochip_reqres_irq(chip, d->hwirq);588}589 590static void zynq_gpio_irq_relres(struct irq_data *d)591{592 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);593 594 gpiochip_relres_irq(chip, d->hwirq);595 pm_runtime_put(chip->parent);596}597 598/* irq chip descriptor */599static const struct irq_chip zynq_gpio_level_irqchip = {600 .name = DRIVER_NAME,601 .irq_enable = zynq_gpio_irq_enable,602 .irq_eoi = zynq_gpio_irq_ack,603 .irq_mask = zynq_gpio_irq_mask,604 .irq_unmask = zynq_gpio_irq_unmask,605 .irq_set_type = zynq_gpio_set_irq_type,606 .irq_set_wake = zynq_gpio_set_wake,607 .irq_request_resources = zynq_gpio_irq_reqres,608 .irq_release_resources = zynq_gpio_irq_relres,609 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED |610 IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,611};612 613static const struct irq_chip zynq_gpio_edge_irqchip = {614 .name = DRIVER_NAME,615 .irq_enable = zynq_gpio_irq_enable,616 .irq_ack = zynq_gpio_irq_ack,617 .irq_mask = zynq_gpio_irq_mask,618 .irq_unmask = zynq_gpio_irq_unmask,619 .irq_set_type = zynq_gpio_set_irq_type,620 .irq_set_wake = zynq_gpio_set_wake,621 .irq_request_resources = zynq_gpio_irq_reqres,622 .irq_release_resources = zynq_gpio_irq_relres,623 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,624};625 626static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,627 unsigned int bank_num,628 unsigned long pending)629{630 unsigned int bank_offset = gpio->p_data->bank_min[bank_num];631 struct irq_domain *irqdomain = gpio->chip.irq.domain;632 int offset;633 634 if (!pending)635 return;636 637 for_each_set_bit(offset, &pending, 32)638 generic_handle_domain_irq(irqdomain, offset + bank_offset);639}640 641/**642 * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device643 * @desc: irq descriptor instance of the 'irq'644 *645 * This function reads the Interrupt Status Register of each bank to get the646 * gpio pin number which has triggered an interrupt. It then acks the triggered647 * interrupt and calls the pin specific handler set by the higher layer648 * application for that pin.649 * Note: A bug is reported if no handler is set for the gpio pin.650 */651static void zynq_gpio_irqhandler(struct irq_desc *desc)652{653 u32 int_sts, int_enb;654 unsigned int bank_num;655 struct zynq_gpio *gpio =656 gpiochip_get_data(irq_desc_get_handler_data(desc));657 struct irq_chip *irqchip = irq_desc_get_chip(desc);658 659 chained_irq_enter(irqchip, desc);660 661 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {662 int_sts = readl_relaxed(gpio->base_addr +663 ZYNQ_GPIO_INTSTS_OFFSET(bank_num));664 int_enb = readl_relaxed(gpio->base_addr +665 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));666 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);667 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)668 bank_num = bank_num + VERSAL_UNUSED_BANKS;669 }670 671 chained_irq_exit(irqchip, desc);672}673 674static void zynq_gpio_save_context(struct zynq_gpio *gpio)675{676 unsigned int bank_num;677 678 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {679 gpio->context.datalsw[bank_num] =680 readl_relaxed(gpio->base_addr +681 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));682 gpio->context.datamsw[bank_num] =683 readl_relaxed(gpio->base_addr +684 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));685 gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr +686 ZYNQ_GPIO_DIRM_OFFSET(bank_num));687 gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr +688 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));689 gpio->context.int_type[bank_num] =690 readl_relaxed(gpio->base_addr +691 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));692 gpio->context.int_polarity[bank_num] =693 readl_relaxed(gpio->base_addr +694 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));695 gpio->context.int_any[bank_num] =696 readl_relaxed(gpio->base_addr +697 ZYNQ_GPIO_INTANY_OFFSET(bank_num));698 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)699 bank_num = bank_num + VERSAL_UNUSED_BANKS;700 }701}702 703static void zynq_gpio_restore_context(struct zynq_gpio *gpio)704{705 unsigned int bank_num;706 707 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {708 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +709 ZYNQ_GPIO_INTDIS_OFFSET(bank_num));710 writel_relaxed(gpio->context.datalsw[bank_num],711 gpio->base_addr +712 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));713 writel_relaxed(gpio->context.datamsw[bank_num],714 gpio->base_addr +715 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));716 writel_relaxed(gpio->context.dirm[bank_num],717 gpio->base_addr +718 ZYNQ_GPIO_DIRM_OFFSET(bank_num));719 writel_relaxed(gpio->context.int_type[bank_num],720 gpio->base_addr +721 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));722 writel_relaxed(gpio->context.int_polarity[bank_num],723 gpio->base_addr +724 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));725 writel_relaxed(gpio->context.int_any[bank_num],726 gpio->base_addr +727 ZYNQ_GPIO_INTANY_OFFSET(bank_num));728 writel_relaxed(~(gpio->context.int_en[bank_num]),729 gpio->base_addr +730 ZYNQ_GPIO_INTEN_OFFSET(bank_num));731 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)732 bank_num = bank_num + VERSAL_UNUSED_BANKS;733 }734}735 736static int __maybe_unused zynq_gpio_suspend(struct device *dev)737{738 struct zynq_gpio *gpio = dev_get_drvdata(dev);739 struct irq_data *data = irq_get_irq_data(gpio->irq);740 741 if (!data) {742 dev_err(dev, "irq_get_irq_data() failed\n");743 return -EINVAL;744 }745 746 if (!device_may_wakeup(dev))747 disable_irq(gpio->irq);748 749 if (!irqd_is_wakeup_set(data)) {750 zynq_gpio_save_context(gpio);751 return pm_runtime_force_suspend(dev);752 }753 754 return 0;755}756 757static int __maybe_unused zynq_gpio_resume(struct device *dev)758{759 struct zynq_gpio *gpio = dev_get_drvdata(dev);760 struct irq_data *data = irq_get_irq_data(gpio->irq);761 int ret;762 763 if (!data) {764 dev_err(dev, "irq_get_irq_data() failed\n");765 return -EINVAL;766 }767 768 if (!device_may_wakeup(dev))769 enable_irq(gpio->irq);770 771 if (!irqd_is_wakeup_set(data)) {772 ret = pm_runtime_force_resume(dev);773 zynq_gpio_restore_context(gpio);774 return ret;775 }776 777 return 0;778}779 780static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev)781{782 struct zynq_gpio *gpio = dev_get_drvdata(dev);783 784 clk_disable_unprepare(gpio->clk);785 786 return 0;787}788 789static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev)790{791 struct zynq_gpio *gpio = dev_get_drvdata(dev);792 793 return clk_prepare_enable(gpio->clk);794}795 796static int zynq_gpio_request(struct gpio_chip *chip, unsigned int offset)797{798 int ret;799 800 ret = pm_runtime_get_sync(chip->parent);801 802 /*803 * If the device is already active pm_runtime_get() will return 1 on804 * success, but gpio_request still needs to return 0.805 */806 return ret < 0 ? ret : 0;807}808 809static void zynq_gpio_free(struct gpio_chip *chip, unsigned int offset)810{811 pm_runtime_put(chip->parent);812}813 814static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {815 SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)816 SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend,817 zynq_gpio_runtime_resume, NULL)818};819 820static const struct zynq_platform_data versal_gpio_def = {821 .label = "versal_gpio",822 .quirks = GPIO_QUIRK_VERSAL,823 .ngpio = 58,824 .max_bank = VERSAL_GPIO_MAX_BANK,825 .bank_min[0] = 0,826 .bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */827 .bank_min[3] = 26,828 .bank_max[3] = 57, /* Bank 3 is connected to FMIOs (32 pins) */829};830 831static const struct zynq_platform_data pmc_gpio_def = {832 .label = "pmc_gpio",833 .ngpio = 116,834 .max_bank = PMC_GPIO_MAX_BANK,835 .bank_min[0] = 0,836 .bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */837 .bank_min[1] = 26,838 .bank_max[1] = 51, /* Bank 1 are connected to MIOs (26 pins) */839 .bank_min[3] = 52,840 .bank_max[3] = 83, /* Bank 3 is connected to EMIOs (32 pins) */841 .bank_min[4] = 84,842 .bank_max[4] = 115, /* Bank 4 is connected to EMIOs (32 pins) */843};844 845static const struct zynq_platform_data zynqmp_gpio_def = {846 .label = "zynqmp_gpio",847 .quirks = GPIO_QUIRK_DATA_RO_BUG,848 .ngpio = ZYNQMP_GPIO_NR_GPIOS,849 .max_bank = ZYNQMP_GPIO_MAX_BANK,850 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),851 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),852 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),853 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),854 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),855 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),856 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),857 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),858 .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),859 .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),860 .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),861 .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),862};863 864static const struct zynq_platform_data zynq_gpio_def = {865 .label = "zynq_gpio",866 .quirks = ZYNQ_GPIO_QUIRK_IS_ZYNQ | GPIO_QUIRK_DATA_RO_BUG,867 .ngpio = ZYNQ_GPIO_NR_GPIOS,868 .max_bank = ZYNQ_GPIO_MAX_BANK,869 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),870 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),871 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),872 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),873 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),874 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),875 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),876 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),877};878 879static const struct of_device_id zynq_gpio_of_match[] = {880 { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def },881 { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def },882 { .compatible = "xlnx,versal-gpio-1.0", .data = &versal_gpio_def },883 { .compatible = "xlnx,pmc-gpio-1.0", .data = &pmc_gpio_def },884 { /* end of table */ }885};886MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);887 888/**889 * zynq_gpio_probe - Initialization method for a zynq_gpio device890 * @pdev: platform device instance891 *892 * This function allocates memory resources for the gpio device and registers893 * all the banks of the device. It will also set up interrupts for the gpio894 * pins.895 * Note: Interrupts are disabled for all the banks during initialization.896 *897 * Return: 0 on success, negative error otherwise.898 */899static int zynq_gpio_probe(struct platform_device *pdev)900{901 int ret, bank_num;902 struct zynq_gpio *gpio;903 struct gpio_chip *chip;904 struct gpio_irq_chip *girq;905 const struct of_device_id *match;906 907 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);908 if (!gpio)909 return -ENOMEM;910 911 match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node);912 if (!match) {913 dev_err(&pdev->dev, "of_match_node() failed\n");914 return -EINVAL;915 }916 gpio->p_data = match->data;917 platform_set_drvdata(pdev, gpio);918 919 gpio->base_addr = devm_platform_ioremap_resource(pdev, 0);920 if (IS_ERR(gpio->base_addr))921 return PTR_ERR(gpio->base_addr);922 923 gpio->irq = platform_get_irq(pdev, 0);924 if (gpio->irq < 0)925 return gpio->irq;926 927 /* configure the gpio chip */928 chip = &gpio->chip;929 chip->label = gpio->p_data->label;930 chip->owner = THIS_MODULE;931 chip->parent = &pdev->dev;932 chip->get = zynq_gpio_get_value;933 chip->set = zynq_gpio_set_value;934 chip->request = zynq_gpio_request;935 chip->free = zynq_gpio_free;936 chip->direction_input = zynq_gpio_dir_in;937 chip->direction_output = zynq_gpio_dir_out;938 chip->get_direction = zynq_gpio_get_direction;939 chip->base = of_alias_get_id(pdev->dev.of_node, "gpio");940 chip->ngpio = gpio->p_data->ngpio;941 942 /* Retrieve GPIO clock */943 gpio->clk = devm_clk_get_enabled(&pdev->dev, NULL);944 if (IS_ERR(gpio->clk))945 return dev_err_probe(&pdev->dev, PTR_ERR(gpio->clk), "input clock not found.\n");946 947 spin_lock_init(&gpio->dirlock);948 949 pm_runtime_set_active(&pdev->dev);950 pm_runtime_enable(&pdev->dev);951 ret = pm_runtime_resume_and_get(&pdev->dev);952 if (ret < 0)953 goto err_pm_dis;954 955 /* disable interrupts for all banks */956 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {957 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +958 ZYNQ_GPIO_INTDIS_OFFSET(bank_num));959 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)960 bank_num = bank_num + VERSAL_UNUSED_BANKS;961 }962 963 /* Set up the GPIO irqchip */964 girq = &chip->irq;965 gpio_irq_chip_set_chip(girq, &zynq_gpio_edge_irqchip);966 girq->parent_handler = zynq_gpio_irqhandler;967 girq->num_parents = 1;968 girq->parents = devm_kcalloc(&pdev->dev, 1,969 sizeof(*girq->parents),970 GFP_KERNEL);971 if (!girq->parents) {972 ret = -ENOMEM;973 goto err_pm_put;974 }975 girq->parents[0] = gpio->irq;976 girq->default_type = IRQ_TYPE_NONE;977 girq->handler = handle_level_irq;978 979 /* report a bug if gpio chip registration fails */980 ret = gpiochip_add_data(chip, gpio);981 if (ret) {982 dev_err(&pdev->dev, "Failed to add gpio chip\n");983 goto err_pm_put;984 }985 986 irq_set_status_flags(gpio->irq, IRQ_DISABLE_UNLAZY);987 device_init_wakeup(&pdev->dev, 1);988 pm_runtime_put(&pdev->dev);989 990 return 0;991 992err_pm_put:993 pm_runtime_put(&pdev->dev);994err_pm_dis:995 pm_runtime_disable(&pdev->dev);996 997 return ret;998}999 1000/**1001 * zynq_gpio_remove - Driver removal function1002 * @pdev: platform device instance1003 *1004 * Return: 0 always1005 */1006static void zynq_gpio_remove(struct platform_device *pdev)1007{1008 struct zynq_gpio *gpio = platform_get_drvdata(pdev);1009 int ret;1010 1011 ret = pm_runtime_get_sync(&pdev->dev);1012 if (ret < 0)1013 dev_warn(&pdev->dev, "pm_runtime_get_sync() Failed\n");1014 gpiochip_remove(&gpio->chip);1015 device_set_wakeup_capable(&pdev->dev, 0);1016 pm_runtime_disable(&pdev->dev);1017}1018 1019static struct platform_driver zynq_gpio_driver = {1020 .driver = {1021 .name = DRIVER_NAME,1022 .pm = &zynq_gpio_dev_pm_ops,1023 .of_match_table = zynq_gpio_of_match,1024 },1025 .probe = zynq_gpio_probe,1026 .remove_new = zynq_gpio_remove,1027};1028 1029module_platform_driver(zynq_gpio_driver);1030 1031MODULE_AUTHOR("Xilinx Inc.");1032MODULE_DESCRIPTION("Zynq GPIO driver");1033MODULE_LICENSE("GPL");1034