916 lines · c
1/*2 * Copyright 2023 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23 24#include <linux/list.h>25#include "amdgpu.h"26#include "amdgpu_aca.h"27#include "amdgpu_ras.h"28 29#define ACA_BANK_HWID(type, hwid, mcatype) [ACA_HWIP_TYPE_##type] = {hwid, mcatype}30 31typedef int bank_handler_t(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type, void *data);32 33struct aca_banks {34 int nr_banks;35 struct list_head list;36};37 38struct aca_hwip {39 int hwid;40 int mcatype;41};42 43static struct aca_hwip aca_hwid_mcatypes[ACA_HWIP_TYPE_COUNT] = {44 ACA_BANK_HWID(SMU, 0x01, 0x01),45 ACA_BANK_HWID(PCS_XGMI, 0x50, 0x00),46 ACA_BANK_HWID(UMC, 0x96, 0x00),47};48 49static void aca_banks_init(struct aca_banks *banks)50{51 if (!banks)52 return;53 54 memset(banks, 0, sizeof(*banks));55 INIT_LIST_HEAD(&banks->list);56}57 58static int aca_banks_add_bank(struct aca_banks *banks, struct aca_bank *bank)59{60 struct aca_bank_node *node;61 62 if (!bank)63 return -EINVAL;64 65 node = kvzalloc(sizeof(*node), GFP_KERNEL);66 if (!node)67 return -ENOMEM;68 69 memcpy(&node->bank, bank, sizeof(*bank));70 71 INIT_LIST_HEAD(&node->node);72 list_add_tail(&node->node, &banks->list);73 74 banks->nr_banks++;75 76 return 0;77}78 79static void aca_banks_release(struct aca_banks *banks)80{81 struct aca_bank_node *node, *tmp;82 83 if (list_empty(&banks->list))84 return;85 86 list_for_each_entry_safe(node, tmp, &banks->list, node) {87 list_del(&node->node);88 kvfree(node);89 }90}91 92static int aca_smu_get_valid_aca_count(struct amdgpu_device *adev, enum aca_smu_type type, u32 *count)93{94 struct amdgpu_aca *aca = &adev->aca;95 const struct aca_smu_funcs *smu_funcs = aca->smu_funcs;96 97 if (!count)98 return -EINVAL;99 100 if (!smu_funcs || !smu_funcs->get_valid_aca_count)101 return -EOPNOTSUPP;102 103 return smu_funcs->get_valid_aca_count(adev, type, count);104}105 106static struct aca_regs_dump {107 const char *name;108 int reg_idx;109} aca_regs[] = {110 {"CONTROL", ACA_REG_IDX_CTL},111 {"STATUS", ACA_REG_IDX_STATUS},112 {"ADDR", ACA_REG_IDX_ADDR},113 {"MISC", ACA_REG_IDX_MISC0},114 {"CONFIG", ACA_REG_IDX_CONFG},115 {"IPID", ACA_REG_IDX_IPID},116 {"SYND", ACA_REG_IDX_SYND},117 {"DESTAT", ACA_REG_IDX_DESTAT},118 {"DEADDR", ACA_REG_IDX_DEADDR},119 {"CONTROL_MASK", ACA_REG_IDX_CTL_MASK},120};121 122static void aca_smu_bank_dump(struct amdgpu_device *adev, int idx, int total, struct aca_bank *bank,123 struct ras_query_context *qctx)124{125 u64 event_id = qctx ? qctx->evid.event_id : RAS_EVENT_INVALID_ID;126 int i;127 128 RAS_EVENT_LOG(adev, event_id, HW_ERR "Accelerator Check Architecture events logged\n");129 /* plus 1 for output format, e.g: ACA[08/08]: xxxx */130 for (i = 0; i < ARRAY_SIZE(aca_regs); i++)131 RAS_EVENT_LOG(adev, event_id, HW_ERR "ACA[%02d/%02d].%s=0x%016llx\n",132 idx + 1, total, aca_regs[i].name, bank->regs[aca_regs[i].reg_idx]);133}134 135static int aca_smu_get_valid_aca_banks(struct amdgpu_device *adev, enum aca_smu_type type,136 int start, int count,137 struct aca_banks *banks, struct ras_query_context *qctx)138{139 struct amdgpu_aca *aca = &adev->aca;140 const struct aca_smu_funcs *smu_funcs = aca->smu_funcs;141 struct aca_bank bank;142 int i, max_count, ret;143 144 if (!count)145 return 0;146 147 if (!smu_funcs || !smu_funcs->get_valid_aca_bank)148 return -EOPNOTSUPP;149 150 switch (type) {151 case ACA_SMU_TYPE_UE:152 max_count = smu_funcs->max_ue_bank_count;153 break;154 case ACA_SMU_TYPE_CE:155 max_count = smu_funcs->max_ce_bank_count;156 break;157 default:158 return -EINVAL;159 }160 161 if (start + count >= max_count)162 return -EINVAL;163 164 count = min_t(int, count, max_count);165 for (i = 0; i < count; i++) {166 memset(&bank, 0, sizeof(bank));167 ret = smu_funcs->get_valid_aca_bank(adev, type, start + i, &bank);168 if (ret)169 return ret;170 171 bank.type = type;172 173 aca_smu_bank_dump(adev, i, count, &bank, qctx);174 175 ret = aca_banks_add_bank(banks, &bank);176 if (ret)177 return ret;178 }179 180 return 0;181}182 183static bool aca_bank_hwip_is_matched(struct aca_bank *bank, enum aca_hwip_type type)184{185 186 struct aca_hwip *hwip;187 int hwid, mcatype;188 u64 ipid;189 190 if (!bank || type == ACA_HWIP_TYPE_UNKNOW)191 return false;192 193 hwip = &aca_hwid_mcatypes[type];194 if (!hwip->hwid)195 return false;196 197 ipid = bank->regs[ACA_REG_IDX_IPID];198 hwid = ACA_REG__IPID__HARDWAREID(ipid);199 mcatype = ACA_REG__IPID__MCATYPE(ipid);200 201 return hwip->hwid == hwid && hwip->mcatype == mcatype;202}203 204static bool aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type)205{206 const struct aca_bank_ops *bank_ops = handle->bank_ops;207 208 if (!aca_bank_hwip_is_matched(bank, handle->hwip))209 return false;210 211 if (!bank_ops->aca_bank_is_valid)212 return true;213 214 return bank_ops->aca_bank_is_valid(handle, bank, type, handle->data);215}216 217static struct aca_bank_error *new_bank_error(struct aca_error *aerr, struct aca_bank_info *info)218{219 struct aca_bank_error *bank_error;220 221 bank_error = kvzalloc(sizeof(*bank_error), GFP_KERNEL);222 if (!bank_error)223 return NULL;224 225 INIT_LIST_HEAD(&bank_error->node);226 memcpy(&bank_error->info, info, sizeof(*info));227 228 mutex_lock(&aerr->lock);229 list_add_tail(&bank_error->node, &aerr->list);230 mutex_unlock(&aerr->lock);231 232 return bank_error;233}234 235static struct aca_bank_error *find_bank_error(struct aca_error *aerr, struct aca_bank_info *info)236{237 struct aca_bank_error *bank_error = NULL;238 struct aca_bank_info *tmp_info;239 bool found = false;240 241 mutex_lock(&aerr->lock);242 list_for_each_entry(bank_error, &aerr->list, node) {243 tmp_info = &bank_error->info;244 if (tmp_info->socket_id == info->socket_id &&245 tmp_info->die_id == info->die_id) {246 found = true;247 goto out_unlock;248 }249 }250 251out_unlock:252 mutex_unlock(&aerr->lock);253 254 return found ? bank_error : NULL;255}256 257static void aca_bank_error_remove(struct aca_error *aerr, struct aca_bank_error *bank_error)258{259 if (!aerr || !bank_error)260 return;261 262 list_del(&bank_error->node);263 aerr->nr_errors--;264 265 kvfree(bank_error);266}267 268static struct aca_bank_error *get_bank_error(struct aca_error *aerr, struct aca_bank_info *info)269{270 struct aca_bank_error *bank_error;271 272 if (!aerr || !info)273 return NULL;274 275 bank_error = find_bank_error(aerr, info);276 if (bank_error)277 return bank_error;278 279 return new_bank_error(aerr, info);280}281 282int aca_error_cache_log_bank_error(struct aca_handle *handle, struct aca_bank_info *info,283 enum aca_error_type type, u64 count)284{285 struct aca_error_cache *error_cache = &handle->error_cache;286 struct aca_bank_error *bank_error;287 struct aca_error *aerr;288 289 if (!handle || !info || type >= ACA_ERROR_TYPE_COUNT)290 return -EINVAL;291 292 if (!count)293 return 0;294 295 aerr = &error_cache->errors[type];296 bank_error = get_bank_error(aerr, info);297 if (!bank_error)298 return -ENOMEM;299 300 bank_error->count += count;301 302 return 0;303}304 305static int aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type)306{307 const struct aca_bank_ops *bank_ops = handle->bank_ops;308 309 if (!bank)310 return -EINVAL;311 312 if (!bank_ops->aca_bank_parser)313 return -EOPNOTSUPP;314 315 return bank_ops->aca_bank_parser(handle, bank, type,316 handle->data);317}318 319static int handler_aca_log_bank_error(struct aca_handle *handle, struct aca_bank *bank,320 enum aca_smu_type type, void *data)321{322 int ret;323 324 ret = aca_bank_parser(handle, bank, type);325 if (ret)326 return ret;327 328 return 0;329}330 331static int aca_dispatch_bank(struct aca_handle_manager *mgr, struct aca_bank *bank,332 enum aca_smu_type type, bank_handler_t handler, void *data)333{334 struct aca_handle *handle;335 int ret;336 337 if (list_empty(&mgr->list))338 return 0;339 340 list_for_each_entry(handle, &mgr->list, node) {341 if (!aca_bank_is_valid(handle, bank, type))342 continue;343 344 ret = handler(handle, bank, type, data);345 if (ret)346 return ret;347 }348 349 return 0;350}351 352static int aca_dispatch_banks(struct aca_handle_manager *mgr, struct aca_banks *banks,353 enum aca_smu_type type, bank_handler_t handler, void *data)354{355 struct aca_bank_node *node;356 struct aca_bank *bank;357 int ret;358 359 if (!mgr || !banks)360 return -EINVAL;361 362 /* pre check to avoid unnecessary operations */363 if (list_empty(&mgr->list) || list_empty(&banks->list))364 return 0;365 366 list_for_each_entry(node, &banks->list, node) {367 bank = &node->bank;368 369 ret = aca_dispatch_bank(mgr, bank, type, handler, data);370 if (ret)371 return ret;372 }373 374 return 0;375}376 377static bool aca_bank_should_update(struct amdgpu_device *adev, enum aca_smu_type type)378{379 struct amdgpu_aca *aca = &adev->aca;380 bool ret = true;381 382 /*383 * Because the UE Valid MCA count will only be cleared after reset,384 * in order to avoid repeated counting of the error count,385 * the aca bank is only updated once during the gpu recovery stage.386 */387 if (type == ACA_SMU_TYPE_UE) {388 if (amdgpu_ras_intr_triggered())389 ret = atomic_cmpxchg(&aca->ue_update_flag, 0, 1) == 0;390 else391 atomic_set(&aca->ue_update_flag, 0);392 }393 394 return ret;395}396 397static int aca_banks_update(struct amdgpu_device *adev, enum aca_smu_type type,398 bank_handler_t handler, struct ras_query_context *qctx, void *data)399{400 struct amdgpu_aca *aca = &adev->aca;401 struct aca_banks banks;402 u32 count = 0;403 int ret;404 405 if (list_empty(&aca->mgr.list))406 return 0;407 408 if (!aca_bank_should_update(adev, type))409 return 0;410 411 ret = aca_smu_get_valid_aca_count(adev, type, &count);412 if (ret)413 return ret;414 415 if (!count)416 return 0;417 418 aca_banks_init(&banks);419 420 ret = aca_smu_get_valid_aca_banks(adev, type, 0, count, &banks, qctx);421 if (ret)422 goto err_release_banks;423 424 if (list_empty(&banks.list)) {425 ret = 0;426 goto err_release_banks;427 }428 429 ret = aca_dispatch_banks(&aca->mgr, &banks, type,430 handler, data);431 if (ret)432 goto err_release_banks;433 434err_release_banks:435 aca_banks_release(&banks);436 437 return ret;438}439 440static int aca_log_aca_error_data(struct aca_bank_error *bank_error, enum aca_error_type type, struct ras_err_data *err_data)441{442 struct aca_bank_info *info;443 struct amdgpu_smuio_mcm_config_info mcm_info;444 u64 count;445 446 if (type >= ACA_ERROR_TYPE_COUNT)447 return -EINVAL;448 449 count = bank_error->count;450 if (!count)451 return 0;452 453 info = &bank_error->info;454 mcm_info.die_id = info->die_id;455 mcm_info.socket_id = info->socket_id;456 457 switch (type) {458 case ACA_ERROR_TYPE_UE:459 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, count);460 break;461 case ACA_ERROR_TYPE_CE:462 amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, count);463 break;464 case ACA_ERROR_TYPE_DEFERRED:465 amdgpu_ras_error_statistic_de_count(err_data, &mcm_info, count);466 break;467 default:468 break;469 }470 471 return 0;472}473 474static int aca_log_aca_error(struct aca_handle *handle, enum aca_error_type type, struct ras_err_data *err_data)475{476 struct aca_error_cache *error_cache = &handle->error_cache;477 struct aca_error *aerr = &error_cache->errors[type];478 struct aca_bank_error *bank_error, *tmp;479 480 mutex_lock(&aerr->lock);481 482 if (list_empty(&aerr->list))483 goto out_unlock;484 485 list_for_each_entry_safe(bank_error, tmp, &aerr->list, node) {486 aca_log_aca_error_data(bank_error, type, err_data);487 aca_bank_error_remove(aerr, bank_error);488 }489 490out_unlock:491 mutex_unlock(&aerr->lock);492 493 return 0;494}495 496static int __aca_get_error_data(struct amdgpu_device *adev, struct aca_handle *handle, enum aca_error_type type,497 struct ras_err_data *err_data, struct ras_query_context *qctx)498{499 enum aca_smu_type smu_type;500 int ret;501 502 switch (type) {503 case ACA_ERROR_TYPE_UE:504 smu_type = ACA_SMU_TYPE_UE;505 break;506 case ACA_ERROR_TYPE_CE:507 case ACA_ERROR_TYPE_DEFERRED:508 smu_type = ACA_SMU_TYPE_CE;509 break;510 default:511 return -EINVAL;512 }513 514 /* update aca bank to aca source error_cache first */515 ret = aca_banks_update(adev, smu_type, handler_aca_log_bank_error, qctx, NULL);516 if (ret)517 return ret;518 519 return aca_log_aca_error(handle, type, err_data);520}521 522static bool aca_handle_is_valid(struct aca_handle *handle)523{524 if (!handle->mask || !list_empty(&handle->node))525 return false;526 527 return true;528}529 530int amdgpu_aca_get_error_data(struct amdgpu_device *adev, struct aca_handle *handle,531 enum aca_error_type type, struct ras_err_data *err_data,532 struct ras_query_context *qctx)533{534 if (!handle || !err_data)535 return -EINVAL;536 537 if (aca_handle_is_valid(handle))538 return -EOPNOTSUPP;539 540 if ((type < 0) || (!(BIT(type) & handle->mask)))541 return 0;542 543 return __aca_get_error_data(adev, handle, type, err_data, qctx);544}545 546static void aca_error_init(struct aca_error *aerr, enum aca_error_type type)547{548 mutex_init(&aerr->lock);549 INIT_LIST_HEAD(&aerr->list);550 aerr->type = type;551 aerr->nr_errors = 0;552}553 554static void aca_init_error_cache(struct aca_handle *handle)555{556 struct aca_error_cache *error_cache = &handle->error_cache;557 int type;558 559 for (type = ACA_ERROR_TYPE_UE; type < ACA_ERROR_TYPE_COUNT; type++)560 aca_error_init(&error_cache->errors[type], type);561}562 563static void aca_error_fini(struct aca_error *aerr)564{565 struct aca_bank_error *bank_error, *tmp;566 567 mutex_lock(&aerr->lock);568 if (list_empty(&aerr->list))569 goto out_unlock;570 571 list_for_each_entry_safe(bank_error, tmp, &aerr->list, node)572 aca_bank_error_remove(aerr, bank_error);573 574out_unlock:575 mutex_destroy(&aerr->lock);576}577 578static void aca_fini_error_cache(struct aca_handle *handle)579{580 struct aca_error_cache *error_cache = &handle->error_cache;581 int type;582 583 for (type = ACA_ERROR_TYPE_UE; type < ACA_ERROR_TYPE_COUNT; type++)584 aca_error_fini(&error_cache->errors[type]);585}586 587static int add_aca_handle(struct amdgpu_device *adev, struct aca_handle_manager *mgr, struct aca_handle *handle,588 const char *name, const struct aca_info *ras_info, void *data)589{590 memset(handle, 0, sizeof(*handle));591 592 handle->adev = adev;593 handle->mgr = mgr;594 handle->name = name;595 handle->hwip = ras_info->hwip;596 handle->mask = ras_info->mask;597 handle->bank_ops = ras_info->bank_ops;598 handle->data = data;599 aca_init_error_cache(handle);600 601 INIT_LIST_HEAD(&handle->node);602 list_add_tail(&handle->node, &mgr->list);603 mgr->nr_handles++;604 605 return 0;606}607 608static ssize_t aca_sysfs_read(struct device *dev,609 struct device_attribute *attr, char *buf)610{611 struct aca_handle *handle = container_of(attr, struct aca_handle, aca_attr);612 613 /* NOTE: the aca cache will be auto cleared once read,614 * So the driver should unify the query entry point, forward request to ras query interface directly */615 return amdgpu_ras_aca_sysfs_read(dev, attr, handle, buf, handle->data);616}617 618static int add_aca_sysfs(struct amdgpu_device *adev, struct aca_handle *handle)619{620 struct device_attribute *aca_attr = &handle->aca_attr;621 622 snprintf(handle->attr_name, sizeof(handle->attr_name) - 1, "aca_%s", handle->name);623 aca_attr->show = aca_sysfs_read;624 aca_attr->attr.name = handle->attr_name;625 aca_attr->attr.mode = S_IRUGO;626 sysfs_attr_init(&aca_attr->attr);627 628 return sysfs_add_file_to_group(&adev->dev->kobj,629 &aca_attr->attr,630 "ras");631}632 633int amdgpu_aca_add_handle(struct amdgpu_device *adev, struct aca_handle *handle,634 const char *name, const struct aca_info *ras_info, void *data)635{636 struct amdgpu_aca *aca = &adev->aca;637 int ret;638 639 if (!amdgpu_aca_is_enabled(adev))640 return 0;641 642 ret = add_aca_handle(adev, &aca->mgr, handle, name, ras_info, data);643 if (ret)644 return ret;645 646 return add_aca_sysfs(adev, handle);647}648 649static void remove_aca_handle(struct aca_handle *handle)650{651 struct aca_handle_manager *mgr = handle->mgr;652 653 aca_fini_error_cache(handle);654 list_del(&handle->node);655 mgr->nr_handles--;656}657 658static void remove_aca_sysfs(struct aca_handle *handle)659{660 struct amdgpu_device *adev = handle->adev;661 struct device_attribute *aca_attr = &handle->aca_attr;662 663 if (adev->dev->kobj.sd)664 sysfs_remove_file_from_group(&adev->dev->kobj,665 &aca_attr->attr,666 "ras");667}668 669void amdgpu_aca_remove_handle(struct aca_handle *handle)670{671 if (!handle || list_empty(&handle->node))672 return;673 674 remove_aca_sysfs(handle);675 remove_aca_handle(handle);676}677 678static int aca_manager_init(struct aca_handle_manager *mgr)679{680 INIT_LIST_HEAD(&mgr->list);681 mgr->nr_handles = 0;682 683 return 0;684}685 686static void aca_manager_fini(struct aca_handle_manager *mgr)687{688 struct aca_handle *handle, *tmp;689 690 if (list_empty(&mgr->list))691 return;692 693 list_for_each_entry_safe(handle, tmp, &mgr->list, node)694 amdgpu_aca_remove_handle(handle);695}696 697bool amdgpu_aca_is_enabled(struct amdgpu_device *adev)698{699 return (adev->aca.is_enabled ||700 adev->debug_enable_ras_aca);701}702 703int amdgpu_aca_init(struct amdgpu_device *adev)704{705 struct amdgpu_aca *aca = &adev->aca;706 int ret;707 708 atomic_set(&aca->ue_update_flag, 0);709 710 ret = aca_manager_init(&aca->mgr);711 if (ret)712 return ret;713 714 return 0;715}716 717void amdgpu_aca_fini(struct amdgpu_device *adev)718{719 struct amdgpu_aca *aca = &adev->aca;720 721 aca_manager_fini(&aca->mgr);722 723 atomic_set(&aca->ue_update_flag, 0);724}725 726int amdgpu_aca_reset(struct amdgpu_device *adev)727{728 struct amdgpu_aca *aca = &adev->aca;729 730 atomic_set(&aca->ue_update_flag, 0);731 732 return 0;733}734 735void amdgpu_aca_set_smu_funcs(struct amdgpu_device *adev, const struct aca_smu_funcs *smu_funcs)736{737 struct amdgpu_aca *aca = &adev->aca;738 739 WARN_ON(aca->smu_funcs);740 aca->smu_funcs = smu_funcs;741}742 743int aca_bank_info_decode(struct aca_bank *bank, struct aca_bank_info *info)744{745 u64 ipid;746 u32 instidhi, instidlo;747 748 if (!bank || !info)749 return -EINVAL;750 751 ipid = bank->regs[ACA_REG_IDX_IPID];752 info->hwid = ACA_REG__IPID__HARDWAREID(ipid);753 info->mcatype = ACA_REG__IPID__MCATYPE(ipid);754 /*755 * Unfied DieID Format: SAASS. A:AID, S:Socket.756 * Unfied DieID[4:4] = InstanceId[0:0]757 * Unfied DieID[0:3] = InstanceIdHi[0:3]758 */759 instidhi = ACA_REG__IPID__INSTANCEIDHI(ipid);760 instidlo = ACA_REG__IPID__INSTANCEIDLO(ipid);761 info->die_id = ((instidhi >> 2) & 0x03);762 info->socket_id = ((instidlo & 0x1) << 2) | (instidhi & 0x03);763 764 return 0;765}766 767static int aca_bank_get_error_code(struct amdgpu_device *adev, struct aca_bank *bank)768{769 struct amdgpu_aca *aca = &adev->aca;770 const struct aca_smu_funcs *smu_funcs = aca->smu_funcs;771 772 if (!smu_funcs || !smu_funcs->parse_error_code)773 return -EOPNOTSUPP;774 775 return smu_funcs->parse_error_code(adev, bank);776}777 778int aca_bank_check_error_codes(struct amdgpu_device *adev, struct aca_bank *bank, int *err_codes, int size)779{780 int i, error_code;781 782 if (!bank || !err_codes)783 return -EINVAL;784 785 error_code = aca_bank_get_error_code(adev, bank);786 if (error_code < 0)787 return error_code;788 789 for (i = 0; i < size; i++) {790 if (err_codes[i] == error_code)791 return 0;792 }793 794 return -EINVAL;795}796 797int amdgpu_aca_smu_set_debug_mode(struct amdgpu_device *adev, bool en)798{799 struct amdgpu_aca *aca = &adev->aca;800 const struct aca_smu_funcs *smu_funcs = aca->smu_funcs;801 802 if (!smu_funcs || !smu_funcs->set_debug_mode)803 return -EOPNOTSUPP;804 805 return smu_funcs->set_debug_mode(adev, en);806}807 808#if defined(CONFIG_DEBUG_FS)809static int amdgpu_aca_smu_debug_mode_set(void *data, u64 val)810{811 struct amdgpu_device *adev = (struct amdgpu_device *)data;812 int ret;813 814 ret = amdgpu_ras_set_aca_debug_mode(adev, val ? true : false);815 if (ret)816 return ret;817 818 dev_info(adev->dev, "amdgpu set smu aca debug mode %s success\n", val ? "on" : "off");819 820 return 0;821}822 823static void aca_dump_entry(struct seq_file *m, struct aca_bank *bank, enum aca_smu_type type, int idx)824{825 struct aca_bank_info info;826 int i, ret;827 828 ret = aca_bank_info_decode(bank, &info);829 if (ret)830 return;831 832 seq_printf(m, "aca entry[%d].type: %s\n", idx, type == ACA_SMU_TYPE_UE ? "UE" : "CE");833 seq_printf(m, "aca entry[%d].info: socketid:%d aid:%d hwid:0x%03x mcatype:0x%04x\n",834 idx, info.socket_id, info.die_id, info.hwid, info.mcatype);835 836 for (i = 0; i < ARRAY_SIZE(aca_regs); i++)837 seq_printf(m, "aca entry[%d].regs[%d]: 0x%016llx\n", idx, aca_regs[i].reg_idx, bank->regs[aca_regs[i].reg_idx]);838}839 840struct aca_dump_context {841 struct seq_file *m;842 int idx;843};844 845static int handler_aca_bank_dump(struct aca_handle *handle, struct aca_bank *bank,846 enum aca_smu_type type, void *data)847{848 struct aca_dump_context *ctx = (struct aca_dump_context *)data;849 850 aca_dump_entry(ctx->m, bank, type, ctx->idx++);851 852 return handler_aca_log_bank_error(handle, bank, type, NULL);853}854 855static int aca_dump_show(struct seq_file *m, enum aca_smu_type type)856{857 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;858 struct aca_dump_context context = {859 .m = m,860 .idx = 0,861 };862 863 return aca_banks_update(adev, type, handler_aca_bank_dump, NULL, (void *)&context);864}865 866static int aca_dump_ce_show(struct seq_file *m, void *unused)867{868 return aca_dump_show(m, ACA_SMU_TYPE_CE);869}870 871static int aca_dump_ce_open(struct inode *inode, struct file *file)872{873 return single_open(file, aca_dump_ce_show, inode->i_private);874}875 876static const struct file_operations aca_ce_dump_debug_fops = {877 .owner = THIS_MODULE,878 .open = aca_dump_ce_open,879 .read = seq_read,880 .llseek = seq_lseek,881 .release = single_release,882};883 884static int aca_dump_ue_show(struct seq_file *m, void *unused)885{886 return aca_dump_show(m, ACA_SMU_TYPE_UE);887}888 889static int aca_dump_ue_open(struct inode *inode, struct file *file)890{891 return single_open(file, aca_dump_ue_show, inode->i_private);892}893 894static const struct file_operations aca_ue_dump_debug_fops = {895 .owner = THIS_MODULE,896 .open = aca_dump_ue_open,897 .read = seq_read,898 .llseek = seq_lseek,899 .release = single_release,900};901 902DEFINE_DEBUGFS_ATTRIBUTE(aca_debug_mode_fops, NULL, amdgpu_aca_smu_debug_mode_set, "%llu\n");903#endif904 905void amdgpu_aca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root)906{907#if defined(CONFIG_DEBUG_FS)908 if (!root)909 return;910 911 debugfs_create_file("aca_debug_mode", 0200, root, adev, &aca_debug_mode_fops);912 debugfs_create_file("aca_ue_dump", 0400, root, adev, &aca_ue_dump_debug_fops);913 debugfs_create_file("aca_ce_dump", 0400, root, adev, &aca_ce_dump_debug_fops);914#endif915}916