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1/*2 * Copyright 2023 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23 24#ifndef __AMDGPU_ACA_H__25#define __AMDGPU_ACA_H__26 27#include <linux/list.h>28 29struct ras_err_data;30struct ras_query_context;31 32#define ACA_MAX_REGS_COUNT (16)33 34#define ACA_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> l)35#define ACA_REG__STATUS__VAL(x) ACA_REG_FIELD(x, 63, 63)36#define ACA_REG__STATUS__OVERFLOW(x) ACA_REG_FIELD(x, 62, 62)37#define ACA_REG__STATUS__UC(x) ACA_REG_FIELD(x, 61, 61)38#define ACA_REG__STATUS__EN(x) ACA_REG_FIELD(x, 60, 60)39#define ACA_REG__STATUS__MISCV(x) ACA_REG_FIELD(x, 59, 59)40#define ACA_REG__STATUS__ADDRV(x) ACA_REG_FIELD(x, 58, 58)41#define ACA_REG__STATUS__PCC(x) ACA_REG_FIELD(x, 57, 57)42#define ACA_REG__STATUS__ERRCOREIDVAL(x) ACA_REG_FIELD(x, 56, 56)43#define ACA_REG__STATUS__TCC(x) ACA_REG_FIELD(x, 55, 55)44#define ACA_REG__STATUS__SYNDV(x) ACA_REG_FIELD(x, 53, 53)45#define ACA_REG__STATUS__CECC(x) ACA_REG_FIELD(x, 46, 46)46#define ACA_REG__STATUS__UECC(x) ACA_REG_FIELD(x, 45, 45)47#define ACA_REG__STATUS__DEFERRED(x) ACA_REG_FIELD(x, 44, 44)48#define ACA_REG__STATUS__POISON(x) ACA_REG_FIELD(x, 43, 43)49#define ACA_REG__STATUS__SCRUB(x) ACA_REG_FIELD(x, 40, 40)50#define ACA_REG__STATUS__ERRCOREID(x) ACA_REG_FIELD(x, 37, 32)51#define ACA_REG__STATUS__ADDRLSB(x) ACA_REG_FIELD(x, 29, 24)52#define ACA_REG__STATUS__ERRORCODEEXT(x) ACA_REG_FIELD(x, 21, 16)53#define ACA_REG__STATUS__ERRORCODE(x) ACA_REG_FIELD(x, 15, 0)54 55#define ACA_REG__IPID__MCATYPE(x) ACA_REG_FIELD(x, 63, 48)56#define ACA_REG__IPID__INSTANCEIDHI(x) ACA_REG_FIELD(x, 47, 44)57#define ACA_REG__IPID__HARDWAREID(x) ACA_REG_FIELD(x, 43, 32)58#define ACA_REG__IPID__INSTANCEIDLO(x) ACA_REG_FIELD(x, 31, 0)59 60#define ACA_REG__MISC0__VALID(x) ACA_REG_FIELD(x, 63, 63)61#define ACA_REG__MISC0__OVRFLW(x) ACA_REG_FIELD(x, 48, 48)62#define ACA_REG__MISC0__ERRCNT(x) ACA_REG_FIELD(x, 43, 32)63 64#define ACA_REG__SYND__ERRORINFORMATION(x) ACA_REG_FIELD(x, 17, 0)65 66/* NOTE: The following codes refers to the smu header file */67#define ACA_EXTERROR_CODE_CE 0x3a68#define ACA_EXTERROR_CODE_FAULT 0x3b69 70#define ACA_ERROR_UE_MASK BIT_MASK(ACA_ERROR_TYPE_UE)71#define ACA_ERROR_CE_MASK BIT_MASK(ACA_ERROR_TYPE_CE)72#define ACA_ERROR_DEFERRED_MASK BIT_MASK(ACA_ERROR_TYPE_DEFERRED)73 74enum aca_reg_idx {75 ACA_REG_IDX_CTL = 0,76 ACA_REG_IDX_STATUS = 1,77 ACA_REG_IDX_ADDR = 2,78 ACA_REG_IDX_MISC0 = 3,79 ACA_REG_IDX_CONFG = 4,80 ACA_REG_IDX_IPID = 5,81 ACA_REG_IDX_SYND = 6,82 ACA_REG_IDX_DESTAT = 8,83 ACA_REG_IDX_DEADDR = 9,84 ACA_REG_IDX_CTL_MASK = 10,85 ACA_REG_IDX_COUNT = 16,86};87 88enum aca_hwip_type {89 ACA_HWIP_TYPE_UNKNOW = -1,90 ACA_HWIP_TYPE_PSP = 0,91 ACA_HWIP_TYPE_UMC,92 ACA_HWIP_TYPE_SMU,93 ACA_HWIP_TYPE_PCS_XGMI,94 ACA_HWIP_TYPE_COUNT,95};96 97enum aca_error_type {98 ACA_ERROR_TYPE_INVALID = -1,99 ACA_ERROR_TYPE_UE = 0,100 ACA_ERROR_TYPE_CE,101 ACA_ERROR_TYPE_DEFERRED,102 ACA_ERROR_TYPE_COUNT103};104 105enum aca_smu_type {106 ACA_SMU_TYPE_UE = 0,107 ACA_SMU_TYPE_CE,108 ACA_SMU_TYPE_COUNT,109};110 111struct aca_bank {112 enum aca_smu_type type;113 u64 regs[ACA_MAX_REGS_COUNT];114};115 116struct aca_bank_node {117 struct aca_bank bank;118 struct list_head node;119};120 121struct aca_bank_info {122 int die_id;123 int socket_id;124 int hwid;125 int mcatype;126};127 128struct aca_bank_error {129 struct list_head node;130 struct aca_bank_info info;131 u64 count;132};133 134struct aca_error {135 struct list_head list;136 struct mutex lock;137 enum aca_error_type type;138 int nr_errors;139};140 141struct aca_handle_manager {142 struct list_head list;143 int nr_handles;144};145 146struct aca_error_cache {147 struct aca_error errors[ACA_ERROR_TYPE_COUNT];148};149 150struct aca_handle {151 struct list_head node;152 enum aca_hwip_type hwip;153 struct amdgpu_device *adev;154 struct aca_handle_manager *mgr;155 struct aca_error_cache error_cache;156 const struct aca_bank_ops *bank_ops;157 struct device_attribute aca_attr;158 char attr_name[64];159 const char *name;160 u32 mask;161 void *data;162};163 164struct aca_bank_ops {165 int (*aca_bank_parser)(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type, void *data);166 bool (*aca_bank_is_valid)(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type,167 void *data);168};169 170struct aca_smu_funcs {171 int max_ue_bank_count;172 int max_ce_bank_count;173 int (*set_debug_mode)(struct amdgpu_device *adev, bool enable);174 int (*get_valid_aca_count)(struct amdgpu_device *adev, enum aca_smu_type type, u32 *count);175 int (*get_valid_aca_bank)(struct amdgpu_device *adev, enum aca_smu_type type, int idx, struct aca_bank *bank);176 int (*parse_error_code)(struct amdgpu_device *adev, struct aca_bank *bank);177};178 179struct amdgpu_aca {180 struct aca_handle_manager mgr;181 const struct aca_smu_funcs *smu_funcs;182 atomic_t ue_update_flag;183 bool is_enabled;184};185 186struct aca_info {187 enum aca_hwip_type hwip;188 const struct aca_bank_ops *bank_ops;189 u32 mask;190};191 192int amdgpu_aca_init(struct amdgpu_device *adev);193void amdgpu_aca_fini(struct amdgpu_device *adev);194int amdgpu_aca_reset(struct amdgpu_device *adev);195void amdgpu_aca_set_smu_funcs(struct amdgpu_device *adev, const struct aca_smu_funcs *smu_funcs);196bool amdgpu_aca_is_enabled(struct amdgpu_device *adev);197 198int aca_bank_info_decode(struct aca_bank *bank, struct aca_bank_info *info);199int aca_bank_check_error_codes(struct amdgpu_device *adev, struct aca_bank *bank, int *err_codes, int size);200 201int amdgpu_aca_add_handle(struct amdgpu_device *adev, struct aca_handle *handle,202 const char *name, const struct aca_info *aca_info, void *data);203void amdgpu_aca_remove_handle(struct aca_handle *handle);204int amdgpu_aca_get_error_data(struct amdgpu_device *adev, struct aca_handle *handle,205 enum aca_error_type type, struct ras_err_data *err_data,206 struct ras_query_context *qctx);207int amdgpu_aca_smu_set_debug_mode(struct amdgpu_device *adev, bool en);208void amdgpu_aca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root);209int aca_error_cache_log_bank_error(struct aca_handle *handle, struct aca_bank_info *info,210 enum aca_error_type type, u64 count);211#endif212