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1/*2 * Copyright 2023 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 */22 23uint32_t kgd_gfx_v10_enable_debug_trap(struct amdgpu_device *adev,24 bool restore_dbg_registers,25 uint32_t vmid);26uint32_t kgd_gfx_v10_disable_debug_trap(struct amdgpu_device *adev,27 bool keep_trap_enabled,28 uint32_t vmid);29int kgd_gfx_v10_validate_trap_override_request(struct amdgpu_device *adev,30 uint32_t trap_override,31 uint32_t *trap_mask_supported);32uint32_t kgd_gfx_v10_set_wave_launch_trap_override(struct amdgpu_device *adev,33 uint32_t vmid,34 uint32_t trap_override,35 uint32_t trap_mask_bits,36 uint32_t trap_mask_request,37 uint32_t *trap_mask_prev,38 uint32_t kfd_dbg_trap_cntl_prev);39uint32_t kgd_gfx_v10_set_wave_launch_mode(struct amdgpu_device *adev,40 uint8_t wave_launch_mode,41 uint32_t vmid);42uint32_t kgd_gfx_v10_set_address_watch(struct amdgpu_device *adev,43 uint64_t watch_address,44 uint32_t watch_address_mask,45 uint32_t watch_id,46 uint32_t watch_mode,47 uint32_t debug_vmid,48 uint32_t inst);49uint32_t kgd_gfx_v10_clear_address_watch(struct amdgpu_device *adev,50 uint32_t watch_id);51void kgd_gfx_v10_get_iq_wait_times(struct amdgpu_device *adev,52 uint32_t *wait_times,53 uint32_t inst);54void kgd_gfx_v10_build_grace_period_packet_info(struct amdgpu_device *adev,55 uint32_t wait_times,56 uint32_t grace_period,57 uint32_t *reg_offset,58 uint32_t *reg_data);59uint64_t kgd_gfx_v10_hqd_get_pq_addr(struct amdgpu_device *adev,60 uint32_t pipe_id,61 uint32_t queue_id,62 uint32_t inst);63uint64_t kgd_gfx_v10_hqd_reset(struct amdgpu_device *adev,64 uint32_t pipe_id,65 uint32_t queue_id,66 uint32_t inst,67 unsigned int utimeout);68