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1/*2 * Copyright 2020 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23 24#ifndef __AMDGPU_DF_H__25#define __AMDGPU_DF_H__26 27struct amdgpu_df_hash_status {28 bool hash_64k;29 bool hash_2m;30 bool hash_1g;31};32 33struct amdgpu_df_funcs {34 void (*sw_init)(struct amdgpu_device *adev);35 void (*sw_fini)(struct amdgpu_device *adev);36 void (*hw_init)(struct amdgpu_device *adev);37 void (*enable_broadcast_mode)(struct amdgpu_device *adev,38 bool enable);39 u32 (*get_fb_channel_number)(struct amdgpu_device *adev);40 u32 (*get_hbm_channel_number)(struct amdgpu_device *adev);41 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,42 bool enable);43 void (*get_clockgating_state)(struct amdgpu_device *adev,44 u64 *flags);45 void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,46 bool enable);47 int (*pmc_start)(struct amdgpu_device *adev, uint64_t config,48 int counter_idx, int is_add);49 int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config,50 int counter_idx, int is_remove);51 void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config,52 int counter_idx, uint64_t *count);53 uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val);54 void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val,55 uint32_t ficadl_val, uint32_t ficadh_val);56 bool (*query_ras_poison_mode)(struct amdgpu_device *adev);57};58 59struct amdgpu_df {60 struct amdgpu_df_hash_status hash_status;61 const struct amdgpu_df_funcs *funcs;62};63 64#endif /* __AMDGPU_DF_H__ */65