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1/*2 * Copyright 2021 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23 24#include "amdgpu_eeprom.h"25#include "amdgpu.h"26 27/* AT24CM02 and M24M02-R have a 256-byte write page size.28 */29#define EEPROM_PAGE_BITS 830#define EEPROM_PAGE_SIZE (1U << EEPROM_PAGE_BITS)31#define EEPROM_PAGE_MASK (EEPROM_PAGE_SIZE - 1)32 33#define EEPROM_OFFSET_SIZE 234 35/* EEPROM memory addresses are 19-bits long, which can36 * be partitioned into 3, 8, 8 bits, for a total of 19.37 * The upper 3 bits are sent as part of the 7-bit38 * "Device Type Identifier"--an I2C concept, which for EEPROM devices39 * is hard-coded as 1010b, indicating that it is an EEPROM40 * device--this is the wire format, followed by the upper41 * 3 bits of the 19-bit address, followed by the direction,42 * followed by two bytes holding the rest of the 16-bits of43 * the EEPROM memory address. The format on the wire for EEPROM44 * devices is: 1010XYZD, A15:A8, A7:A0,45 * Where D is the direction and sequenced out by the hardware.46 * Bits XYZ are memory address bits 18, 17 and 16.47 * These bits are compared to how pins 1-3 of the part are connected,48 * depending on the size of the part, more on that later.49 *50 * Note that of this wire format, a client is in control51 * of, and needs to specify only XYZ, A15:A8, A7:0, bits,52 * which is exactly the EEPROM memory address, or offset,53 * in order to address up to 8 EEPROM devices on the I2C bus.54 *55 * For instance, a 2-Mbit I2C EEPROM part, addresses all its bytes,56 * using an 18-bit address, bit 17 to 0 and thus would use all but one bit of57 * the 19 bits previously mentioned. The designer would then not connect58 * pins 1 and 2, and pin 3 usually named "A_2" or "E2", would be connected to59 * either Vcc or GND. This would allow for up to two 2-Mbit parts on60 * the same bus, where one would be addressable with bit 18 as 1, and61 * the other with bit 18 of the address as 0.62 *63 * For a 2-Mbit part, bit 18 is usually known as the "Chip Enable" or64 * "Hardware Address Bit". This bit is compared to the load on pin 365 * of the device, described above, and if there is a match, then this66 * device responds to the command. This way, you can connect two67 * 2-Mbit EEPROM devices on the same bus, but see one contiguous68 * memory from 0 to 7FFFFh, where address 0 to 3FFFF is in the device69 * whose pin 3 is connected to GND, and address 40000 to 7FFFFh is in70 * the 2nd device, whose pin 3 is connected to Vcc.71 *72 * This addressing you encode in the 32-bit "eeprom_addr" below,73 * namely the 19-bits "XYZ,A15:A0", as a single 19-bit address. For74 * instance, eeprom_addr = 0x6DA01, is 110_1101_1010_0000_0001, where75 * XYZ=110b, and A15:A0=DA01h. The XYZ bits become part of the device76 * address, and the rest of the address bits are sent as the memory77 * address bytes.78 *79 * That is, for an I2C EEPROM driver everything is controlled by80 * the "eeprom_addr".81 *82 * See also top of amdgpu_ras_eeprom.c.83 *84 * P.S. If you need to write, lock and read the Identification Page,85 * (M24M02-DR device only, which we do not use), change the "7" to86 * "0xF" in the macro below, and let the client set bit 20 to 1 in87 * "eeprom_addr", and set A10 to 0 to write into it, and A10 and A1 to88 * 1 to lock it permanently.89 */90#define MAKE_I2C_ADDR(_aa) ((0xA << 3) | (((_aa) >> 16) & 0xF))91 92static int __amdgpu_eeprom_xfer(struct i2c_adapter *i2c_adap, u32 eeprom_addr,93 u8 *eeprom_buf, u32 buf_size, bool read)94{95 u8 eeprom_offset_buf[EEPROM_OFFSET_SIZE];96 struct i2c_msg msgs[] = {97 {98 .flags = 0,99 .len = EEPROM_OFFSET_SIZE,100 .buf = eeprom_offset_buf,101 },102 {103 .flags = read ? I2C_M_RD : 0,104 },105 };106 const u8 *p = eeprom_buf;107 int r;108 u16 len;109 110 for (r = 0; buf_size > 0;111 buf_size -= len, eeprom_addr += len, eeprom_buf += len) {112 /* Set the EEPROM address we want to write to/read from.113 */114 msgs[0].addr = MAKE_I2C_ADDR(eeprom_addr);115 msgs[1].addr = msgs[0].addr;116 msgs[0].buf[0] = (eeprom_addr >> 8) & 0xff;117 msgs[0].buf[1] = eeprom_addr & 0xff;118 119 if (!read) {120 /* Write the maximum amount of data, without121 * crossing the device's page boundary, as per122 * its spec. Partial page writes are allowed,123 * starting at any location within the page,124 * so long as the page boundary isn't crossed125 * over (actually the page pointer rolls126 * over).127 *128 * As per the AT24CM02 EEPROM spec, after129 * writing into a page, the I2C driver should130 * terminate the transfer, i.e. in131 * "i2c_transfer()" below, with a STOP132 * condition, so that the self-timed write133 * cycle begins. This is implied for the134 * "i2c_transfer()" abstraction.135 */136 len = min(EEPROM_PAGE_SIZE - (eeprom_addr & EEPROM_PAGE_MASK),137 buf_size);138 } else {139 /* Reading from the EEPROM has no limitation140 * on the number of bytes read from the EEPROM141 * device--they are simply sequenced out.142 * Keep in mind that i2c_msg.len is u16 type.143 */144 len = min(U16_MAX, buf_size);145 }146 msgs[1].len = len;147 msgs[1].buf = eeprom_buf;148 149 /* This constitutes a START-STOP transaction.150 */151 r = i2c_transfer(i2c_adap, msgs, ARRAY_SIZE(msgs));152 if (r != ARRAY_SIZE(msgs))153 break;154 155 if (!read) {156 /* According to EEPROM specs the length of the157 * self-writing cycle, tWR (tW), is 10 ms.158 *159 * TODO: Use polling on ACK, aka Acknowledge160 * Polling, to minimize waiting for the161 * internal write cycle to complete, as it is162 * usually smaller than tWR (tW).163 */164 msleep(10);165 }166 }167 168 return r < 0 ? r : eeprom_buf - p;169}170 171/**172 * amdgpu_eeprom_xfer -- Read/write from/to an I2C EEPROM device173 * @i2c_adap: pointer to the I2C adapter to use174 * @eeprom_addr: EEPROM address from which to read/write175 * @eeprom_buf: pointer to data buffer to read into/write from176 * @buf_size: the size of @eeprom_buf177 * @read: True if reading from the EEPROM, false if writing178 *179 * Returns the number of bytes read/written; -errno on error.180 */181static int amdgpu_eeprom_xfer(struct i2c_adapter *i2c_adap, u32 eeprom_addr,182 u8 *eeprom_buf, u32 buf_size, bool read)183{184 const struct i2c_adapter_quirks *quirks = i2c_adap->quirks;185 u16 limit;186 u16 ps; /* Partial size */187 int res = 0, r;188 189 if (!quirks)190 limit = 0;191 else if (read)192 limit = quirks->max_read_len;193 else194 limit = quirks->max_write_len;195 196 if (limit == 0) {197 return __amdgpu_eeprom_xfer(i2c_adap, eeprom_addr,198 eeprom_buf, buf_size, read);199 } else if (limit <= EEPROM_OFFSET_SIZE) {200 dev_err_ratelimited(&i2c_adap->dev,201 "maddr:0x%04X size:0x%02X:quirk max_%s_len must be > %d",202 eeprom_addr, buf_size,203 read ? "read" : "write", EEPROM_OFFSET_SIZE);204 return -EINVAL;205 }206 207 /* The "limit" includes all data bytes sent/received,208 * which would include the EEPROM_OFFSET_SIZE bytes.209 * Account for them here.210 */211 limit -= EEPROM_OFFSET_SIZE;212 for ( ; buf_size > 0;213 buf_size -= ps, eeprom_addr += ps, eeprom_buf += ps) {214 ps = min(limit, buf_size);215 216 r = __amdgpu_eeprom_xfer(i2c_adap, eeprom_addr,217 eeprom_buf, ps, read);218 if (r < 0)219 return r;220 res += r;221 }222 223 return res;224}225 226int amdgpu_eeprom_read(struct i2c_adapter *i2c_adap,227 u32 eeprom_addr, u8 *eeprom_buf,228 u32 bytes)229{230 return amdgpu_eeprom_xfer(i2c_adap, eeprom_addr, eeprom_buf, bytes,231 true);232}233 234int amdgpu_eeprom_write(struct i2c_adapter *i2c_adap,235 u32 eeprom_addr, u8 *eeprom_buf,236 u32 bytes)237{238 return amdgpu_eeprom_xfer(i2c_adap, eeprom_addr, eeprom_buf, bytes,239 false);240}241