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1/*2 * Copyright 2018 Advanced Micro Devices, Inc.3 * All Rights Reserved.4 *5 * Permission is hereby granted, free of charge, to any person obtaining a6 * copy of this software and associated documentation files (the7 * "Software"), to deal in the Software without restriction, including8 * without limitation the rights to use, copy, modify, merge, publish,9 * distribute, sub license, and/or sell copies of the Software, and to10 * permit persons to whom the Software is furnished to do so, subject to11 * the following conditions:12 *13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE19 * USE OR OTHER DEALINGS IN THE SOFTWARE.20 *21 * The above copyright notice and this permission notice (including the22 * next paragraph) shall be included in all copies or substantial portions23 * of the Software.24 *25 */26 27#include <linux/io-64-nonatomic-lo-hi.h>28#ifdef CONFIG_X8629#include <asm/hypervisor.h>30#endif31 32#include "amdgpu.h"33#include "amdgpu_gmc.h"34#include "amdgpu_ras.h"35#include "amdgpu_reset.h"36#include "amdgpu_xgmi.h"37 38#include <drm/drm_drv.h>39#include <drm/ttm/ttm_tt.h>40 41/**42 * amdgpu_gmc_pdb0_alloc - allocate vram for pdb043 *44 * @adev: amdgpu_device pointer45 *46 * Allocate video memory for pdb0 and map it for CPU access47 * Returns 0 for success, error for failure.48 */49int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev)50{51 int r;52 struct amdgpu_bo_param bp;53 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes;54 uint32_t pde0_page_shift = adev->gmc.vmid0_page_table_block_size + 21;55 uint32_t npdes = (vram_size + (1ULL << pde0_page_shift) - 1) >> pde0_page_shift;56 57 memset(&bp, 0, sizeof(bp));58 bp.size = PAGE_ALIGN((npdes + 1) * 8);59 bp.byte_align = PAGE_SIZE;60 bp.domain = AMDGPU_GEM_DOMAIN_VRAM;61 bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |62 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;63 bp.type = ttm_bo_type_kernel;64 bp.resv = NULL;65 bp.bo_ptr_size = sizeof(struct amdgpu_bo);66 67 r = amdgpu_bo_create(adev, &bp, &adev->gmc.pdb0_bo);68 if (r)69 return r;70 71 r = amdgpu_bo_reserve(adev->gmc.pdb0_bo, false);72 if (unlikely(r != 0))73 goto bo_reserve_failure;74 75 r = amdgpu_bo_pin(adev->gmc.pdb0_bo, AMDGPU_GEM_DOMAIN_VRAM);76 if (r)77 goto bo_pin_failure;78 r = amdgpu_bo_kmap(adev->gmc.pdb0_bo, &adev->gmc.ptr_pdb0);79 if (r)80 goto bo_kmap_failure;81 82 amdgpu_bo_unreserve(adev->gmc.pdb0_bo);83 return 0;84 85bo_kmap_failure:86 amdgpu_bo_unpin(adev->gmc.pdb0_bo);87bo_pin_failure:88 amdgpu_bo_unreserve(adev->gmc.pdb0_bo);89bo_reserve_failure:90 amdgpu_bo_unref(&adev->gmc.pdb0_bo);91 return r;92}93 94/**95 * amdgpu_gmc_get_pde_for_bo - get the PDE for a BO96 *97 * @bo: the BO to get the PDE for98 * @level: the level in the PD hirarchy99 * @addr: resulting addr100 * @flags: resulting flags101 *102 * Get the address and flags to be used for a PDE (Page Directory Entry).103 */104void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,105 uint64_t *addr, uint64_t *flags)106{107 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);108 109 switch (bo->tbo.resource->mem_type) {110 case TTM_PL_TT:111 *addr = bo->tbo.ttm->dma_address[0];112 break;113 case TTM_PL_VRAM:114 *addr = amdgpu_bo_gpu_offset(bo);115 break;116 default:117 *addr = 0;118 break;119 }120 *flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, bo->tbo.resource);121 amdgpu_gmc_get_vm_pde(adev, level, addr, flags);122}123 124/*125 * amdgpu_gmc_pd_addr - return the address of the root directory126 */127uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)128{129 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);130 uint64_t pd_addr;131 132 /* TODO: move that into ASIC specific code */133 if (adev->asic_type >= CHIP_VEGA10) {134 uint64_t flags = AMDGPU_PTE_VALID;135 136 amdgpu_gmc_get_pde_for_bo(bo, -1, &pd_addr, &flags);137 pd_addr |= flags;138 } else {139 pd_addr = amdgpu_bo_gpu_offset(bo);140 }141 return pd_addr;142}143 144/**145 * amdgpu_gmc_set_pte_pde - update the page tables using CPU146 *147 * @adev: amdgpu_device pointer148 * @cpu_pt_addr: cpu address of the page table149 * @gpu_page_idx: entry in the page table to update150 * @addr: dst addr to write into pte/pde151 * @flags: access flags152 *153 * Update the page tables using CPU.154 */155int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,156 uint32_t gpu_page_idx, uint64_t addr,157 uint64_t flags)158{159 void __iomem *ptr = (void *)cpu_pt_addr;160 uint64_t value;161 162 /*163 * The following is for PTE only. GART does not have PDEs.164 */165 value = addr & 0x0000FFFFFFFFF000ULL;166 value |= flags;167 writeq(value, ptr + (gpu_page_idx * 8));168 169 return 0;170}171 172/**173 * amdgpu_gmc_agp_addr - return the address in the AGP address space174 *175 * @bo: TTM BO which needs the address, must be in GTT domain176 *177 * Tries to figure out how to access the BO through the AGP aperture. Returns178 * AMDGPU_BO_INVALID_OFFSET if that is not possible.179 */180uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo)181{182 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);183 184 if (!bo->ttm)185 return AMDGPU_BO_INVALID_OFFSET;186 187 if (bo->ttm->num_pages != 1 || bo->ttm->caching == ttm_cached)188 return AMDGPU_BO_INVALID_OFFSET;189 190 if (bo->ttm->dma_address[0] + PAGE_SIZE >= adev->gmc.agp_size)191 return AMDGPU_BO_INVALID_OFFSET;192 193 return adev->gmc.agp_start + bo->ttm->dma_address[0];194}195 196/**197 * amdgpu_gmc_vram_location - try to find VRAM location198 *199 * @adev: amdgpu device structure holding all necessary information200 * @mc: memory controller structure holding memory information201 * @base: base address at which to put VRAM202 *203 * Function will try to place VRAM at base address provided204 * as parameter.205 */206void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,207 u64 base)208{209 uint64_t vis_limit = (uint64_t)amdgpu_vis_vram_limit << 20;210 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;211 212 mc->vram_start = base;213 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;214 if (limit < mc->real_vram_size)215 mc->real_vram_size = limit;216 217 if (vis_limit && vis_limit < mc->visible_vram_size)218 mc->visible_vram_size = vis_limit;219 220 if (mc->real_vram_size < mc->visible_vram_size)221 mc->visible_vram_size = mc->real_vram_size;222 223 if (mc->xgmi.num_physical_nodes == 0) {224 mc->fb_start = mc->vram_start;225 mc->fb_end = mc->vram_end;226 }227 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",228 mc->mc_vram_size >> 20, mc->vram_start,229 mc->vram_end, mc->real_vram_size >> 20);230}231 232/** amdgpu_gmc_sysvm_location - place vram and gart in sysvm aperture233 *234 * @adev: amdgpu device structure holding all necessary information235 * @mc: memory controller structure holding memory information236 *237 * This function is only used if use GART for FB translation. In such238 * case, we use sysvm aperture (vmid0 page tables) for both vram239 * and gart (aka system memory) access.240 *241 * GPUVM (and our organization of vmid0 page tables) require sysvm242 * aperture to be placed at a location aligned with 8 times of native243 * page size. For example, if vm_context0_cntl.page_table_block_size244 * is 12, then native page size is 8G (2M*2^12), sysvm should start245 * with a 64G aligned address. For simplicity, we just put sysvm at246 * address 0. So vram start at address 0 and gart is right after vram.247 */248void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)249{250 u64 hive_vram_start = 0;251 u64 hive_vram_end = mc->xgmi.node_segment_size * mc->xgmi.num_physical_nodes - 1;252 mc->vram_start = mc->xgmi.node_segment_size * mc->xgmi.physical_node_id;253 mc->vram_end = mc->vram_start + mc->xgmi.node_segment_size - 1;254 mc->gart_start = hive_vram_end + 1;255 mc->gart_end = mc->gart_start + mc->gart_size - 1;256 mc->fb_start = hive_vram_start;257 mc->fb_end = hive_vram_end;258 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",259 mc->mc_vram_size >> 20, mc->vram_start,260 mc->vram_end, mc->real_vram_size >> 20);261 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",262 mc->gart_size >> 20, mc->gart_start, mc->gart_end);263}264 265/**266 * amdgpu_gmc_gart_location - try to find GART location267 *268 * @adev: amdgpu device structure holding all necessary information269 * @mc: memory controller structure holding memory information270 * @gart_placement: GART placement policy with respect to VRAM271 *272 * Function will place try to place GART before or after VRAM.273 * If GART size is bigger than space left then we ajust GART size.274 * Thus function will never fails.275 */276void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,277 enum amdgpu_gart_placement gart_placement)278{279 const uint64_t four_gb = 0x100000000ULL;280 u64 size_af, size_bf;281 /*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/282 u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1);283 284 /* VCE doesn't like it when BOs cross a 4GB segment, so align285 * the GART base on a 4GB boundary as well.286 */287 size_bf = mc->fb_start;288 size_af = max_mc_address + 1 - ALIGN(mc->fb_end + 1, four_gb);289 290 if (mc->gart_size > max(size_bf, size_af)) {291 dev_warn(adev->dev, "limiting GART\n");292 mc->gart_size = max(size_bf, size_af);293 }294 295 switch (gart_placement) {296 case AMDGPU_GART_PLACEMENT_HIGH:297 mc->gart_start = max_mc_address - mc->gart_size + 1;298 break;299 case AMDGPU_GART_PLACEMENT_LOW:300 mc->gart_start = 0;301 break;302 case AMDGPU_GART_PLACEMENT_BEST_FIT:303 default:304 if ((size_bf >= mc->gart_size && size_bf < size_af) ||305 (size_af < mc->gart_size))306 mc->gart_start = 0;307 else308 mc->gart_start = max_mc_address - mc->gart_size + 1;309 break;310 }311 312 mc->gart_start &= ~(four_gb - 1);313 mc->gart_end = mc->gart_start + mc->gart_size - 1;314 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",315 mc->gart_size >> 20, mc->gart_start, mc->gart_end);316}317 318/**319 * amdgpu_gmc_agp_location - try to find AGP location320 * @adev: amdgpu device structure holding all necessary information321 * @mc: memory controller structure holding memory information322 *323 * Function will place try to find a place for the AGP BAR in the MC address324 * space.325 *326 * AGP BAR will be assigned the largest available hole in the address space.327 * Should be called after VRAM and GART locations are setup.328 */329void amdgpu_gmc_agp_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)330{331 const uint64_t sixteen_gb = 1ULL << 34;332 const uint64_t sixteen_gb_mask = ~(sixteen_gb - 1);333 u64 size_af, size_bf;334 335 if (mc->fb_start > mc->gart_start) {336 size_bf = (mc->fb_start & sixteen_gb_mask) -337 ALIGN(mc->gart_end + 1, sixteen_gb);338 size_af = mc->mc_mask + 1 - ALIGN(mc->fb_end + 1, sixteen_gb);339 } else {340 size_bf = mc->fb_start & sixteen_gb_mask;341 size_af = (mc->gart_start & sixteen_gb_mask) -342 ALIGN(mc->fb_end + 1, sixteen_gb);343 }344 345 if (size_bf > size_af) {346 mc->agp_start = (mc->fb_start - size_bf) & sixteen_gb_mask;347 mc->agp_size = size_bf;348 } else {349 mc->agp_start = ALIGN(mc->fb_end + 1, sixteen_gb);350 mc->agp_size = size_af;351 }352 353 mc->agp_end = mc->agp_start + mc->agp_size - 1;354 dev_info(adev->dev, "AGP: %lluM 0x%016llX - 0x%016llX\n",355 mc->agp_size >> 20, mc->agp_start, mc->agp_end);356}357 358/**359 * amdgpu_gmc_set_agp_default - Set the default AGP aperture value.360 * @adev: amdgpu device structure holding all necessary information361 * @mc: memory controller structure holding memory information362 *363 * To disable the AGP aperture, you need to set the start to a larger364 * value than the end. This function sets the default value which365 * can then be overridden using amdgpu_gmc_agp_location() if you want366 * to enable the AGP aperture on a specific chip.367 *368 */369void amdgpu_gmc_set_agp_default(struct amdgpu_device *adev,370 struct amdgpu_gmc *mc)371{372 mc->agp_start = 0xffffffffffff;373 mc->agp_end = 0;374 mc->agp_size = 0;375}376 377/**378 * amdgpu_gmc_fault_key - get hask key from vm fault address and pasid379 *380 * @addr: 48 bit physical address, page aligned (36 significant bits)381 * @pasid: 16 bit process address space identifier382 */383static inline uint64_t amdgpu_gmc_fault_key(uint64_t addr, uint16_t pasid)384{385 return addr << 4 | pasid;386}387 388/**389 * amdgpu_gmc_filter_faults - filter VM faults390 *391 * @adev: amdgpu device structure392 * @ih: interrupt ring that the fault received from393 * @addr: address of the VM fault394 * @pasid: PASID of the process causing the fault395 * @timestamp: timestamp of the fault396 *397 * Returns:398 * True if the fault was filtered and should not be processed further.399 * False if the fault is a new one and needs to be handled.400 */401bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev,402 struct amdgpu_ih_ring *ih, uint64_t addr,403 uint16_t pasid, uint64_t timestamp)404{405 struct amdgpu_gmc *gmc = &adev->gmc;406 uint64_t stamp, key = amdgpu_gmc_fault_key(addr, pasid);407 struct amdgpu_gmc_fault *fault;408 uint32_t hash;409 410 /* Stale retry fault if timestamp goes backward */411 if (amdgpu_ih_ts_after(timestamp, ih->processed_timestamp))412 return true;413 414 /* If we don't have space left in the ring buffer return immediately */415 stamp = max(timestamp, AMDGPU_GMC_FAULT_TIMEOUT + 1) -416 AMDGPU_GMC_FAULT_TIMEOUT;417 if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp)418 return true;419 420 /* Try to find the fault in the hash */421 hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER);422 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx];423 while (fault->timestamp >= stamp) {424 uint64_t tmp;425 426 if (atomic64_read(&fault->key) == key) {427 /*428 * if we get a fault which is already present in429 * the fault_ring and the timestamp of430 * the fault is after the expired timestamp,431 * then this is a new fault that needs to be added432 * into the fault ring.433 */434 if (fault->timestamp_expiry != 0 &&435 amdgpu_ih_ts_after(fault->timestamp_expiry,436 timestamp))437 break;438 else439 return true;440 }441 442 tmp = fault->timestamp;443 fault = &gmc->fault_ring[fault->next];444 445 /* Check if the entry was reused */446 if (fault->timestamp >= tmp)447 break;448 }449 450 /* Add the fault to the ring */451 fault = &gmc->fault_ring[gmc->last_fault];452 atomic64_set(&fault->key, key);453 fault->timestamp = timestamp;454 455 /* And update the hash */456 fault->next = gmc->fault_hash[hash].idx;457 gmc->fault_hash[hash].idx = gmc->last_fault++;458 return false;459}460 461/**462 * amdgpu_gmc_filter_faults_remove - remove address from VM faults filter463 *464 * @adev: amdgpu device structure465 * @addr: address of the VM fault466 * @pasid: PASID of the process causing the fault467 *468 * Remove the address from fault filter, then future vm fault on this address469 * will pass to retry fault handler to recover.470 */471void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr,472 uint16_t pasid)473{474 struct amdgpu_gmc *gmc = &adev->gmc;475 uint64_t key = amdgpu_gmc_fault_key(addr, pasid);476 struct amdgpu_ih_ring *ih;477 struct amdgpu_gmc_fault *fault;478 uint32_t last_wptr;479 uint64_t last_ts;480 uint32_t hash;481 uint64_t tmp;482 483 if (adev->irq.retry_cam_enabled)484 return;485 486 ih = &adev->irq.ih1;487 /* Get the WPTR of the last entry in IH ring */488 last_wptr = amdgpu_ih_get_wptr(adev, ih);489 /* Order wptr with ring data. */490 rmb();491 /* Get the timetamp of the last entry in IH ring */492 last_ts = amdgpu_ih_decode_iv_ts(adev, ih, last_wptr, -1);493 494 hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER);495 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx];496 do {497 if (atomic64_read(&fault->key) == key) {498 /*499 * Update the timestamp when this fault500 * expired.501 */502 fault->timestamp_expiry = last_ts;503 break;504 }505 506 tmp = fault->timestamp;507 fault = &gmc->fault_ring[fault->next];508 } while (fault->timestamp < tmp);509}510 511int amdgpu_gmc_ras_sw_init(struct amdgpu_device *adev)512{513 int r;514 515 /* umc ras block */516 r = amdgpu_umc_ras_sw_init(adev);517 if (r)518 return r;519 520 /* mmhub ras block */521 r = amdgpu_mmhub_ras_sw_init(adev);522 if (r)523 return r;524 525 /* hdp ras block */526 r = amdgpu_hdp_ras_sw_init(adev);527 if (r)528 return r;529 530 /* mca.x ras block */531 r = amdgpu_mca_mp0_ras_sw_init(adev);532 if (r)533 return r;534 535 r = amdgpu_mca_mp1_ras_sw_init(adev);536 if (r)537 return r;538 539 r = amdgpu_mca_mpio_ras_sw_init(adev);540 if (r)541 return r;542 543 /* xgmi ras block */544 r = amdgpu_xgmi_ras_sw_init(adev);545 if (r)546 return r;547 548 return 0;549}550 551int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev)552{553 return 0;554}555 556void amdgpu_gmc_ras_fini(struct amdgpu_device *adev)557{558 559}560 561 /*562 * The latest engine allocation on gfx9/10 is:563 * Engine 2, 3: firmware564 * Engine 0, 1, 4~16: amdgpu ring,565 * subject to change when ring number changes566 * Engine 17: Gart flushes567 */568#define AMDGPU_VMHUB_INV_ENG_BITMAP 0x1FFF3569 570int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev)571{572 struct amdgpu_ring *ring;573 unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] = {0};574 unsigned i;575 unsigned vmhub, inv_eng;576 577 /* init the vm inv eng for all vmhubs */578 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {579 vm_inv_engs[i] = AMDGPU_VMHUB_INV_ENG_BITMAP;580 /* reserve engine 5 for firmware */581 if (adev->enable_mes)582 vm_inv_engs[i] &= ~(1 << 5);583 /* reserve mmhub engine 3 for firmware */584 if (adev->enable_umsch_mm)585 vm_inv_engs[i] &= ~(1 << 3);586 }587 588 for (i = 0; i < adev->num_rings; ++i) {589 ring = adev->rings[i];590 vmhub = ring->vm_hub;591 592 if (ring == &adev->mes.ring[0] ||593 ring == &adev->mes.ring[1] ||594 ring == &adev->umsch_mm.ring)595 continue;596 597 inv_eng = ffs(vm_inv_engs[vmhub]);598 if (!inv_eng) {599 dev_err(adev->dev, "no VM inv eng for ring %s\n",600 ring->name);601 return -EINVAL;602 }603 604 ring->vm_inv_eng = inv_eng - 1;605 vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng);606 607 dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n",608 ring->name, ring->vm_inv_eng, ring->vm_hub);609 }610 611 return 0;612}613 614void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,615 uint32_t vmhub, uint32_t flush_type)616{617 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;618 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];619 struct dma_fence *fence;620 struct amdgpu_job *job;621 int r;622 623 if (!hub->sdma_invalidation_workaround || vmid ||624 !adev->mman.buffer_funcs_enabled || !adev->ib_pool_ready ||625 !ring->sched.ready) {626 /*627 * A GPU reset should flush all TLBs anyway, so no need to do628 * this while one is ongoing.629 */630 if (!down_read_trylock(&adev->reset_domain->sem))631 return;632 633 if (adev->gmc.flush_tlb_needs_extra_type_2)634 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, vmid,635 vmhub, 2);636 637 if (adev->gmc.flush_tlb_needs_extra_type_0 && flush_type == 2)638 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, vmid,639 vmhub, 0);640 641 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, vmid, vmhub,642 flush_type);643 up_read(&adev->reset_domain->sem);644 return;645 }646 647 /* The SDMA on Navi 1x has a bug which can theoretically result in memory648 * corruption if an invalidation happens at the same time as an VA649 * translation. Avoid this by doing the invalidation from the SDMA650 * itself at least for GART.651 */652 mutex_lock(&adev->mman.gtt_window_lock);653 r = amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.high_pr,654 AMDGPU_FENCE_OWNER_UNDEFINED,655 16 * 4, AMDGPU_IB_POOL_IMMEDIATE,656 &job);657 if (r)658 goto error_alloc;659 660 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);661 job->vm_needs_flush = true;662 job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop;663 amdgpu_ring_pad_ib(ring, &job->ibs[0]);664 fence = amdgpu_job_submit(job);665 mutex_unlock(&adev->mman.gtt_window_lock);666 667 dma_fence_wait(fence, false);668 dma_fence_put(fence);669 670 return;671 672error_alloc:673 mutex_unlock(&adev->mman.gtt_window_lock);674 dev_err(adev->dev, "Error flushing GPU TLB using the SDMA (%d)!\n", r);675}676 677int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid,678 uint32_t flush_type, bool all_hub,679 uint32_t inst)680{681 u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT :682 adev->usec_timeout;683 struct amdgpu_ring *ring = &adev->gfx.kiq[inst].ring;684 struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst];685 unsigned int ndw;686 int r;687 uint32_t seq;688 689 /*690 * A GPU reset should flush all TLBs anyway, so no need to do691 * this while one is ongoing.692 */693 if (!down_read_trylock(&adev->reset_domain->sem))694 return 0;695 696 if (!adev->gmc.flush_pasid_uses_kiq || !ring->sched.ready) {697 if (adev->gmc.flush_tlb_needs_extra_type_2)698 adev->gmc.gmc_funcs->flush_gpu_tlb_pasid(adev, pasid,699 2, all_hub,700 inst);701 702 if (adev->gmc.flush_tlb_needs_extra_type_0 && flush_type == 2)703 adev->gmc.gmc_funcs->flush_gpu_tlb_pasid(adev, pasid,704 0, all_hub,705 inst);706 707 adev->gmc.gmc_funcs->flush_gpu_tlb_pasid(adev, pasid,708 flush_type, all_hub,709 inst);710 r = 0;711 } else {712 /* 2 dwords flush + 8 dwords fence */713 ndw = kiq->pmf->invalidate_tlbs_size + 8;714 715 if (adev->gmc.flush_tlb_needs_extra_type_2)716 ndw += kiq->pmf->invalidate_tlbs_size;717 718 if (adev->gmc.flush_tlb_needs_extra_type_0)719 ndw += kiq->pmf->invalidate_tlbs_size;720 721 spin_lock(&adev->gfx.kiq[inst].ring_lock);722 r = amdgpu_ring_alloc(ring, ndw);723 if (r) {724 spin_unlock(&adev->gfx.kiq[inst].ring_lock);725 goto error_unlock_reset;726 }727 if (adev->gmc.flush_tlb_needs_extra_type_2)728 kiq->pmf->kiq_invalidate_tlbs(ring, pasid, 2, all_hub);729 730 if (flush_type == 2 && adev->gmc.flush_tlb_needs_extra_type_0)731 kiq->pmf->kiq_invalidate_tlbs(ring, pasid, 0, all_hub);732 733 kiq->pmf->kiq_invalidate_tlbs(ring, pasid, flush_type, all_hub);734 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);735 if (r) {736 amdgpu_ring_undo(ring);737 spin_unlock(&adev->gfx.kiq[inst].ring_lock);738 goto error_unlock_reset;739 }740 741 amdgpu_ring_commit(ring);742 spin_unlock(&adev->gfx.kiq[inst].ring_lock);743 if (amdgpu_fence_wait_polling(ring, seq, usec_timeout) < 1) {744 dev_err(adev->dev, "timeout waiting for kiq fence\n");745 r = -ETIME;746 }747 }748 749error_unlock_reset:750 up_read(&adev->reset_domain->sem);751 return r;752}753 754void amdgpu_gmc_fw_reg_write_reg_wait(struct amdgpu_device *adev,755 uint32_t reg0, uint32_t reg1,756 uint32_t ref, uint32_t mask,757 uint32_t xcc_inst)758{759 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_inst];760 struct amdgpu_ring *ring = &kiq->ring;761 signed long r, cnt = 0;762 unsigned long flags;763 uint32_t seq;764 765 if (adev->mes.ring[0].sched.ready) {766 amdgpu_mes_reg_write_reg_wait(adev, reg0, reg1,767 ref, mask);768 return;769 }770 771 spin_lock_irqsave(&kiq->ring_lock, flags);772 amdgpu_ring_alloc(ring, 32);773 amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1,774 ref, mask);775 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);776 if (r)777 goto failed_undo;778 779 amdgpu_ring_commit(ring);780 spin_unlock_irqrestore(&kiq->ring_lock, flags);781 782 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);783 784 /* don't wait anymore for IRQ context */785 if (r < 1 && in_interrupt())786 goto failed_kiq;787 788 might_sleep();789 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY &&790 !amdgpu_reset_pending(adev->reset_domain)) {791 792 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);793 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);794 }795 796 if (cnt > MAX_KIQ_REG_TRY)797 goto failed_kiq;798 799 return;800 801failed_undo:802 amdgpu_ring_undo(ring);803 spin_unlock_irqrestore(&kiq->ring_lock, flags);804failed_kiq:805 dev_err(adev->dev, "failed to write reg %x wait reg %x\n", reg0, reg1);806}807 808/**809 * amdgpu_gmc_tmz_set -- check and set if a device supports TMZ810 * @adev: amdgpu_device pointer811 *812 * Check and set if an the device @adev supports Trusted Memory813 * Zones (TMZ).814 */815void amdgpu_gmc_tmz_set(struct amdgpu_device *adev)816{817 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {818 /* RAVEN */819 case IP_VERSION(9, 2, 2):820 case IP_VERSION(9, 1, 0):821 /* RENOIR looks like RAVEN */822 case IP_VERSION(9, 3, 0):823 /* GC 10.3.7 */824 case IP_VERSION(10, 3, 7):825 /* GC 11.0.1 */826 case IP_VERSION(11, 0, 1):827 if (amdgpu_tmz == 0) {828 adev->gmc.tmz_enabled = false;829 dev_info(adev->dev,830 "Trusted Memory Zone (TMZ) feature disabled (cmd line)\n");831 } else {832 adev->gmc.tmz_enabled = true;833 dev_info(adev->dev,834 "Trusted Memory Zone (TMZ) feature enabled\n");835 }836 break;837 case IP_VERSION(10, 1, 10):838 case IP_VERSION(10, 1, 1):839 case IP_VERSION(10, 1, 2):840 case IP_VERSION(10, 1, 3):841 case IP_VERSION(10, 3, 0):842 case IP_VERSION(10, 3, 2):843 case IP_VERSION(10, 3, 4):844 case IP_VERSION(10, 3, 5):845 case IP_VERSION(10, 3, 6):846 /* VANGOGH */847 case IP_VERSION(10, 3, 1):848 /* YELLOW_CARP*/849 case IP_VERSION(10, 3, 3):850 case IP_VERSION(11, 0, 4):851 case IP_VERSION(11, 5, 0):852 case IP_VERSION(11, 5, 1):853 case IP_VERSION(11, 5, 2):854 /* Don't enable it by default yet.855 */856 if (amdgpu_tmz < 1) {857 adev->gmc.tmz_enabled = false;858 dev_info(adev->dev,859 "Trusted Memory Zone (TMZ) feature disabled as experimental (default)\n");860 } else {861 adev->gmc.tmz_enabled = true;862 dev_info(adev->dev,863 "Trusted Memory Zone (TMZ) feature enabled as experimental (cmd line)\n");864 }865 break;866 default:867 adev->gmc.tmz_enabled = false;868 dev_info(adev->dev,869 "Trusted Memory Zone (TMZ) feature not supported\n");870 break;871 }872}873 874/**875 * amdgpu_gmc_noretry_set -- set per asic noretry defaults876 * @adev: amdgpu_device pointer877 *878 * Set a per asic default for the no-retry parameter.879 *880 */881void amdgpu_gmc_noretry_set(struct amdgpu_device *adev)882{883 struct amdgpu_gmc *gmc = &adev->gmc;884 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);885 bool noretry_default = (gc_ver == IP_VERSION(9, 0, 1) ||886 gc_ver == IP_VERSION(9, 4, 0) ||887 gc_ver == IP_VERSION(9, 4, 1) ||888 gc_ver == IP_VERSION(9, 4, 2) ||889 gc_ver == IP_VERSION(9, 4, 3) ||890 gc_ver == IP_VERSION(9, 4, 4) ||891 gc_ver >= IP_VERSION(10, 3, 0));892 893 if (!amdgpu_sriov_xnack_support(adev))894 gmc->noretry = 1;895 else896 gmc->noretry = (amdgpu_noretry == -1) ? noretry_default : amdgpu_noretry;897}898 899void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type,900 bool enable)901{902 struct amdgpu_vmhub *hub;903 u32 tmp, reg, i;904 905 hub = &adev->vmhub[hub_type];906 for (i = 0; i < 16; i++) {907 reg = hub->vm_context0_cntl + hub->ctx_distance * i;908 909 tmp = (hub_type == AMDGPU_GFXHUB(0)) ?910 RREG32_SOC15_IP(GC, reg) :911 RREG32_SOC15_IP(MMHUB, reg);912 913 if (enable)914 tmp |= hub->vm_cntx_cntl_vm_fault;915 else916 tmp &= ~hub->vm_cntx_cntl_vm_fault;917 918 (hub_type == AMDGPU_GFXHUB(0)) ?919 WREG32_SOC15_IP(GC, reg, tmp) :920 WREG32_SOC15_IP(MMHUB, reg, tmp);921 }922}923 924void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev)925{926 unsigned size;927 928 /*929 * Some ASICs need to reserve a region of video memory to avoid access930 * from driver931 */932 adev->mman.stolen_reserved_offset = 0;933 adev->mman.stolen_reserved_size = 0;934 935 /*936 * TODO:937 * Currently there is a bug where some memory client outside938 * of the driver writes to first 8M of VRAM on S3 resume,939 * this overrides GART which by default gets placed in first 8M and940 * causes VM_FAULTS once GTT is accessed.941 * Keep the stolen memory reservation until the while this is not solved.942 */943 switch (adev->asic_type) {944 case CHIP_VEGA10:945 adev->mman.keep_stolen_vga_memory = true;946 /*947 * VEGA10 SRIOV VF with MS_HYPERV host needs some firmware reserved area.948 */949#ifdef CONFIG_X86950 if (amdgpu_sriov_vf(adev) && hypervisor_is_type(X86_HYPER_MS_HYPERV)) {951 adev->mman.stolen_reserved_offset = 0x500000;952 adev->mman.stolen_reserved_size = 0x200000;953 }954#endif955 break;956 case CHIP_RAVEN:957 case CHIP_RENOIR:958 adev->mman.keep_stolen_vga_memory = true;959 break;960 default:961 adev->mman.keep_stolen_vga_memory = false;962 break;963 }964 965 if (amdgpu_sriov_vf(adev) ||966 !amdgpu_device_has_display_hardware(adev)) {967 size = 0;968 } else {969 size = amdgpu_gmc_get_vbios_fb_size(adev);970 971 if (adev->mman.keep_stolen_vga_memory)972 size = max(size, (unsigned)AMDGPU_VBIOS_VGA_ALLOCATION);973 }974 975 /* set to 0 if the pre-OS buffer uses up most of vram */976 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))977 size = 0;978 979 if (size > AMDGPU_VBIOS_VGA_ALLOCATION) {980 adev->mman.stolen_vga_size = AMDGPU_VBIOS_VGA_ALLOCATION;981 adev->mman.stolen_extended_size = size - adev->mman.stolen_vga_size;982 } else {983 adev->mman.stolen_vga_size = size;984 adev->mman.stolen_extended_size = 0;985 }986}987 988/**989 * amdgpu_gmc_init_pdb0 - initialize PDB0990 *991 * @adev: amdgpu_device pointer992 *993 * This function is only used when GART page table is used994 * for FB address translatioin. In such a case, we construct995 * a 2-level system VM page table: PDB0->PTB, to cover both996 * VRAM of the hive and system memory.997 *998 * PDB0 is static, initialized once on driver initialization.999 * The first n entries of PDB0 are used as PTE by setting1000 * P bit to 1, pointing to VRAM. The n+1'th entry points1001 * to a big PTB covering system memory.1002 *1003 */1004void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev)1005{1006 int i;1007 uint64_t flags = adev->gart.gart_pte_flags; //TODO it is UC. explore NC/RW?1008 /* Each PDE0 (used as PTE) covers (2^vmid0_page_table_block_size)*2M1009 */1010 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes;1011 u64 pde0_page_size = (1ULL<<adev->gmc.vmid0_page_table_block_size)<<21;1012 u64 vram_addr = adev->vm_manager.vram_base_offset -1013 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;1014 u64 vram_end = vram_addr + vram_size;1015 u64 gart_ptb_gpu_pa = amdgpu_gmc_vram_pa(adev, adev->gart.bo);1016 int idx;1017 1018 if (!drm_dev_enter(adev_to_drm(adev), &idx))1019 return;1020 1021 flags |= AMDGPU_PTE_VALID | AMDGPU_PTE_READABLE;1022 flags |= AMDGPU_PTE_WRITEABLE;1023 flags |= AMDGPU_PTE_SNOOPED;1024 flags |= AMDGPU_PTE_FRAG((adev->gmc.vmid0_page_table_block_size + 9*1));1025 flags |= AMDGPU_PDE_PTE_FLAG(adev);1026 1027 /* The first n PDE0 entries are used as PTE,1028 * pointing to vram1029 */1030 for (i = 0; vram_addr < vram_end; i++, vram_addr += pde0_page_size)1031 amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, vram_addr, flags);1032 1033 /* The n+1'th PDE0 entry points to a huge1034 * PTB who has more than 512 entries each1035 * pointing to a 4K system page1036 */1037 flags = AMDGPU_PTE_VALID;1038 flags |= AMDGPU_PTE_SNOOPED | AMDGPU_PDE_BFS_FLAG(adev, 0);1039 /* Requires gart_ptb_gpu_pa to be 4K aligned */1040 amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, gart_ptb_gpu_pa, flags);1041 drm_dev_exit(idx);1042}1043 1044/**1045 * amdgpu_gmc_vram_mc2pa - calculate vram buffer's physical address from MC1046 * address1047 *1048 * @adev: amdgpu_device pointer1049 * @mc_addr: MC address of buffer1050 */1051uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr)1052{1053 return mc_addr - adev->gmc.vram_start + adev->vm_manager.vram_base_offset;1054}1055 1056/**1057 * amdgpu_gmc_vram_pa - calculate vram buffer object's physical address from1058 * GPU's view1059 *1060 * @adev: amdgpu_device pointer1061 * @bo: amdgpu buffer object1062 */1063uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo)1064{1065 return amdgpu_gmc_vram_mc2pa(adev, amdgpu_bo_gpu_offset(bo));1066}1067 1068/**1069 * amdgpu_gmc_vram_cpu_pa - calculate vram buffer object's physical address1070 * from CPU's view1071 *1072 * @adev: amdgpu_device pointer1073 * @bo: amdgpu buffer object1074 */1075uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo)1076{1077 return amdgpu_bo_gpu_offset(bo) - adev->gmc.vram_start + adev->gmc.aper_base;1078}1079 1080int amdgpu_gmc_vram_checking(struct amdgpu_device *adev)1081{1082 struct amdgpu_bo *vram_bo = NULL;1083 uint64_t vram_gpu = 0;1084 void *vram_ptr = NULL;1085 1086 int ret, size = 0x100000;1087 uint8_t cptr[10];1088 1089 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,1090 AMDGPU_GEM_DOMAIN_VRAM,1091 &vram_bo,1092 &vram_gpu,1093 &vram_ptr);1094 if (ret)1095 return ret;1096 1097 memset(vram_ptr, 0x86, size);1098 memset(cptr, 0x86, 10);1099 1100 /**1101 * Check the start, the mid, and the end of the memory if the content of1102 * each byte is the pattern "0x86". If yes, we suppose the vram bo is1103 * workable.1104 *1105 * Note: If check the each byte of whole 1M bo, it will cost too many1106 * seconds, so here, we just pick up three parts for emulation.1107 */1108 ret = memcmp(vram_ptr, cptr, 10);1109 if (ret) {1110 ret = -EIO;1111 goto release_buffer;1112 }1113 1114 ret = memcmp(vram_ptr + (size / 2), cptr, 10);1115 if (ret) {1116 ret = -EIO;1117 goto release_buffer;1118 }1119 1120 ret = memcmp(vram_ptr + size - 10, cptr, 10);1121 if (ret) {1122 ret = -EIO;1123 goto release_buffer;1124 }1125 1126release_buffer:1127 amdgpu_bo_free_kernel(&vram_bo, &vram_gpu,1128 &vram_ptr);1129 1130 return ret;1131}1132 1133static ssize_t current_memory_partition_show(1134 struct device *dev, struct device_attribute *addr, char *buf)1135{1136 struct drm_device *ddev = dev_get_drvdata(dev);1137 struct amdgpu_device *adev = drm_to_adev(ddev);1138 enum amdgpu_memory_partition mode;1139 1140 mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev);1141 switch (mode) {1142 case AMDGPU_NPS1_PARTITION_MODE:1143 return sysfs_emit(buf, "NPS1\n");1144 case AMDGPU_NPS2_PARTITION_MODE:1145 return sysfs_emit(buf, "NPS2\n");1146 case AMDGPU_NPS3_PARTITION_MODE:1147 return sysfs_emit(buf, "NPS3\n");1148 case AMDGPU_NPS4_PARTITION_MODE:1149 return sysfs_emit(buf, "NPS4\n");1150 case AMDGPU_NPS6_PARTITION_MODE:1151 return sysfs_emit(buf, "NPS6\n");1152 case AMDGPU_NPS8_PARTITION_MODE:1153 return sysfs_emit(buf, "NPS8\n");1154 default:1155 return sysfs_emit(buf, "UNKNOWN\n");1156 }1157}1158 1159static DEVICE_ATTR_RO(current_memory_partition);1160 1161int amdgpu_gmc_sysfs_init(struct amdgpu_device *adev)1162{1163 if (!adev->gmc.gmc_funcs->query_mem_partition_mode)1164 return 0;1165 1166 return device_create_file(adev->dev,1167 &dev_attr_current_memory_partition);1168}1169 1170void amdgpu_gmc_sysfs_fini(struct amdgpu_device *adev)1171{1172 device_remove_file(adev->dev, &dev_attr_current_memory_partition);1173}1174 1175int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev,1176 struct amdgpu_mem_partition_info *mem_ranges,1177 int exp_ranges)1178{1179 struct amdgpu_gmc_memrange *ranges;1180 int range_cnt, ret, i, j;1181 uint32_t nps_type;1182 1183 if (!mem_ranges)1184 return -EINVAL;1185 1186 ret = amdgpu_discovery_get_nps_info(adev, &nps_type, &ranges,1187 &range_cnt);1188 1189 if (ret)1190 return ret;1191 1192 /* TODO: For now, expect ranges and partition count to be the same.1193 * Adjust if there are holes expected in any NPS domain.1194 */1195 if (range_cnt != exp_ranges) {1196 dev_warn(1197 adev->dev,1198 "NPS config mismatch - expected ranges: %d discovery - nps mode: %d, nps ranges: %d",1199 exp_ranges, nps_type, range_cnt);1200 ret = -EINVAL;1201 goto err;1202 }1203 1204 for (i = 0; i < exp_ranges; ++i) {1205 if (ranges[i].base_address >= ranges[i].limit_address) {1206 dev_warn(1207 adev->dev,1208 "Invalid NPS range - nps mode: %d, range[%d]: base: %llx limit: %llx",1209 nps_type, i, ranges[i].base_address,1210 ranges[i].limit_address);1211 ret = -EINVAL;1212 goto err;1213 }1214 1215 /* Check for overlaps, not expecting any now */1216 for (j = i - 1; j >= 0; j--) {1217 if (max(ranges[j].base_address,1218 ranges[i].base_address) <=1219 min(ranges[j].limit_address,1220 ranges[i].limit_address)) {1221 dev_warn(1222 adev->dev,1223 "overlapping ranges detected [ %llx - %llx ] | [%llx - %llx]",1224 ranges[j].base_address,1225 ranges[j].limit_address,1226 ranges[i].base_address,1227 ranges[i].limit_address);1228 ret = -EINVAL;1229 goto err;1230 }1231 }1232 1233 mem_ranges[i].range.fpfn =1234 (ranges[i].base_address -1235 adev->vm_manager.vram_base_offset) >>1236 AMDGPU_GPU_PAGE_SHIFT;1237 mem_ranges[i].range.lpfn =1238 (ranges[i].limit_address -1239 adev->vm_manager.vram_base_offset) >>1240 AMDGPU_GPU_PAGE_SHIFT;1241 mem_ranges[i].size =1242 ranges[i].limit_address - ranges[i].base_address + 1;1243 }1244 1245err:1246 kfree(ranges);1247 1248 return ret;1249}1250