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1/*2 * Copyright 2008 Advanced Micro Devices, Inc.3 * Copyright 2008 Red Hat Inc.4 * Copyright 2009 Jerome Glisse.5 *6 * Permission is hereby granted, free of charge, to any person obtaining a7 * copy of this software and associated documentation files (the "Software"),8 * to deal in the Software without restriction, including without limitation9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,10 * and/or sell copies of the Software, and to permit persons to whom the11 * Software is furnished to do so, subject to the following conditions:12 *13 * The above copyright notice and this permission notice shall be included in14 * all copies or substantial portions of the Software.15 *16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR22 * OTHER DEALINGS IN THE SOFTWARE.23 *24 * Authors: Dave Airlie25 * Alex Deucher26 * Jerome Glisse27 */28 29/**30 * DOC: Interrupt Handling31 *32 * Interrupts generated within GPU hardware raise interrupt requests that are33 * passed to amdgpu IRQ handler which is responsible for detecting source and34 * type of the interrupt and dispatching matching handlers. If handling an35 * interrupt requires calling kernel functions that may sleep processing is36 * dispatched to work handlers.37 *38 * If MSI functionality is not disabled by module parameter then MSI39 * support will be enabled.40 *41 * For GPU interrupt sources that may be driven by another driver, IRQ domain42 * support is used (with mapping between virtual and hardware IRQs).43 */44 45#include <linux/irq.h>46#include <linux/pci.h>47 48#include <drm/drm_vblank.h>49#include <drm/amdgpu_drm.h>50#include <drm/drm_drv.h>51#include "amdgpu.h"52#include "amdgpu_ih.h"53#include "atom.h"54#include "amdgpu_connectors.h"55#include "amdgpu_trace.h"56#include "amdgpu_amdkfd.h"57#include "amdgpu_ras.h"58 59#include <linux/pm_runtime.h>60 61#ifdef CONFIG_DRM_AMD_DC62#include "amdgpu_dm_irq.h"63#endif64 65#define AMDGPU_WAIT_IDLE_TIMEOUT 20066 67const char *soc15_ih_clientid_name[] = {68 "IH",69 "SDMA2 or ACP",70 "ATHUB",71 "BIF",72 "SDMA3 or DCE",73 "SDMA4 or ISP",74 "VMC1 or PCIE0",75 "RLC",76 "SDMA0",77 "SDMA1",78 "SE0SH",79 "SE1SH",80 "SE2SH",81 "SE3SH",82 "VCN1 or UVD1",83 "THM",84 "VCN or UVD",85 "SDMA5 or VCE0",86 "VMC",87 "SDMA6 or XDMA",88 "GRBM_CP",89 "ATS",90 "ROM_SMUIO",91 "DF",92 "SDMA7 or VCE1",93 "PWR",94 "reserved",95 "UTCL2",96 "EA",97 "UTCL2LOG",98 "MP0",99 "MP1"100};101 102const int node_id_to_phys_map[NODEID_MAX] = {103 [AID0_NODEID] = 0,104 [XCD0_NODEID] = 0,105 [XCD1_NODEID] = 1,106 [AID1_NODEID] = 1,107 [XCD2_NODEID] = 2,108 [XCD3_NODEID] = 3,109 [AID2_NODEID] = 2,110 [XCD4_NODEID] = 4,111 [XCD5_NODEID] = 5,112 [AID3_NODEID] = 3,113 [XCD6_NODEID] = 6,114 [XCD7_NODEID] = 7,115};116 117/**118 * amdgpu_irq_disable_all - disable *all* interrupts119 *120 * @adev: amdgpu device pointer121 *122 * Disable all types of interrupts from all sources.123 */124void amdgpu_irq_disable_all(struct amdgpu_device *adev)125{126 unsigned long irqflags;127 unsigned int i, j, k;128 int r;129 130 spin_lock_irqsave(&adev->irq.lock, irqflags);131 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {132 if (!adev->irq.client[i].sources)133 continue;134 135 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {136 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];137 138 if (!src || !src->funcs->set || !src->num_types)139 continue;140 141 for (k = 0; k < src->num_types; ++k) {142 r = src->funcs->set(adev, src, k,143 AMDGPU_IRQ_STATE_DISABLE);144 if (r)145 DRM_ERROR("error disabling interrupt (%d)\n",146 r);147 }148 }149 }150 spin_unlock_irqrestore(&adev->irq.lock, irqflags);151}152 153/**154 * amdgpu_irq_handler - IRQ handler155 *156 * @irq: IRQ number (unused)157 * @arg: pointer to DRM device158 *159 * IRQ handler for amdgpu driver (all ASICs).160 *161 * Returns:162 * result of handling the IRQ, as defined by &irqreturn_t163 */164static irqreturn_t amdgpu_irq_handler(int irq, void *arg)165{166 struct drm_device *dev = (struct drm_device *) arg;167 struct amdgpu_device *adev = drm_to_adev(dev);168 irqreturn_t ret;169 170 ret = amdgpu_ih_process(adev, &adev->irq.ih);171 if (ret == IRQ_HANDLED)172 pm_runtime_mark_last_busy(dev->dev);173 174 amdgpu_ras_interrupt_fatal_error_handler(adev);175 176 return ret;177}178 179/**180 * amdgpu_irq_handle_ih1 - kick of processing for IH1181 *182 * @work: work structure in struct amdgpu_irq183 *184 * Kick of processing IH ring 1.185 */186static void amdgpu_irq_handle_ih1(struct work_struct *work)187{188 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,189 irq.ih1_work);190 191 amdgpu_ih_process(adev, &adev->irq.ih1);192}193 194/**195 * amdgpu_irq_handle_ih2 - kick of processing for IH2196 *197 * @work: work structure in struct amdgpu_irq198 *199 * Kick of processing IH ring 2.200 */201static void amdgpu_irq_handle_ih2(struct work_struct *work)202{203 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,204 irq.ih2_work);205 206 amdgpu_ih_process(adev, &adev->irq.ih2);207}208 209/**210 * amdgpu_irq_handle_ih_soft - kick of processing for ih_soft211 *212 * @work: work structure in struct amdgpu_irq213 *214 * Kick of processing IH soft ring.215 */216static void amdgpu_irq_handle_ih_soft(struct work_struct *work)217{218 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,219 irq.ih_soft_work);220 221 amdgpu_ih_process(adev, &adev->irq.ih_soft);222}223 224/**225 * amdgpu_msi_ok - check whether MSI functionality is enabled226 *227 * @adev: amdgpu device pointer (unused)228 *229 * Checks whether MSI functionality has been disabled via module parameter230 * (all ASICs).231 *232 * Returns:233 * *true* if MSIs are allowed to be enabled or *false* otherwise234 */235static bool amdgpu_msi_ok(struct amdgpu_device *adev)236{237 if (amdgpu_msi == 1)238 return true;239 else if (amdgpu_msi == 0)240 return false;241 242 return true;243}244 245static void amdgpu_restore_msix(struct amdgpu_device *adev)246{247 u16 ctrl;248 249 pci_read_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);250 if (!(ctrl & PCI_MSIX_FLAGS_ENABLE))251 return;252 253 /* VF FLR */254 ctrl &= ~PCI_MSIX_FLAGS_ENABLE;255 pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl);256 ctrl |= PCI_MSIX_FLAGS_ENABLE;257 pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl);258}259 260/**261 * amdgpu_irq_init - initialize interrupt handling262 *263 * @adev: amdgpu device pointer264 *265 * Sets up work functions for hotplug and reset interrupts, enables MSI266 * functionality, initializes vblank, hotplug and reset interrupt handling.267 *268 * Returns:269 * 0 on success or error code on failure270 */271int amdgpu_irq_init(struct amdgpu_device *adev)272{273 unsigned int irq, flags;274 int r;275 276 spin_lock_init(&adev->irq.lock);277 278 /* Enable MSI if not disabled by module parameter */279 adev->irq.msi_enabled = false;280 281 if (!amdgpu_msi_ok(adev))282 flags = PCI_IRQ_INTX;283 else284 flags = PCI_IRQ_ALL_TYPES;285 286 /* we only need one vector */287 r = pci_alloc_irq_vectors(adev->pdev, 1, 1, flags);288 if (r < 0) {289 dev_err(adev->dev, "Failed to alloc msi vectors\n");290 return r;291 }292 293 if (amdgpu_msi_ok(adev)) {294 adev->irq.msi_enabled = true;295 dev_dbg(adev->dev, "using MSI/MSI-X.\n");296 }297 298 INIT_WORK(&adev->irq.ih1_work, amdgpu_irq_handle_ih1);299 INIT_WORK(&adev->irq.ih2_work, amdgpu_irq_handle_ih2);300 INIT_WORK(&adev->irq.ih_soft_work, amdgpu_irq_handle_ih_soft);301 302 /* Use vector 0 for MSI-X. */303 r = pci_irq_vector(adev->pdev, 0);304 if (r < 0)305 goto free_vectors;306 irq = r;307 308 /* PCI devices require shared interrupts. */309 r = request_irq(irq, amdgpu_irq_handler, IRQF_SHARED, adev_to_drm(adev)->driver->name,310 adev_to_drm(adev));311 if (r)312 goto free_vectors;313 314 adev->irq.installed = true;315 adev->irq.irq = irq;316 adev_to_drm(adev)->max_vblank_count = 0x00ffffff;317 318 DRM_DEBUG("amdgpu: irq initialized.\n");319 return 0;320 321free_vectors:322 if (adev->irq.msi_enabled)323 pci_free_irq_vectors(adev->pdev);324 325 adev->irq.msi_enabled = false;326 return r;327}328 329void amdgpu_irq_fini_hw(struct amdgpu_device *adev)330{331 if (adev->irq.installed) {332 free_irq(adev->irq.irq, adev_to_drm(adev));333 adev->irq.installed = false;334 if (adev->irq.msi_enabled)335 pci_free_irq_vectors(adev->pdev);336 }337 338 amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft);339 amdgpu_ih_ring_fini(adev, &adev->irq.ih);340 amdgpu_ih_ring_fini(adev, &adev->irq.ih1);341 amdgpu_ih_ring_fini(adev, &adev->irq.ih2);342}343 344/**345 * amdgpu_irq_fini_sw - shut down interrupt handling346 *347 * @adev: amdgpu device pointer348 *349 * Tears down work functions for hotplug and reset interrupts, disables MSI350 * functionality, shuts down vblank, hotplug and reset interrupt handling,351 * turns off interrupts from all sources (all ASICs).352 */353void amdgpu_irq_fini_sw(struct amdgpu_device *adev)354{355 unsigned int i, j;356 357 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {358 if (!adev->irq.client[i].sources)359 continue;360 361 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {362 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];363 364 if (!src)365 continue;366 367 kfree(src->enabled_types);368 src->enabled_types = NULL;369 }370 kfree(adev->irq.client[i].sources);371 adev->irq.client[i].sources = NULL;372 }373}374 375/**376 * amdgpu_irq_add_id - register IRQ source377 *378 * @adev: amdgpu device pointer379 * @client_id: client id380 * @src_id: source id381 * @source: IRQ source pointer382 *383 * Registers IRQ source on a client.384 *385 * Returns:386 * 0 on success or error code otherwise387 */388int amdgpu_irq_add_id(struct amdgpu_device *adev,389 unsigned int client_id, unsigned int src_id,390 struct amdgpu_irq_src *source)391{392 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX)393 return -EINVAL;394 395 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)396 return -EINVAL;397 398 if (!source->funcs)399 return -EINVAL;400 401 if (!adev->irq.client[client_id].sources) {402 adev->irq.client[client_id].sources =403 kcalloc(AMDGPU_MAX_IRQ_SRC_ID,404 sizeof(struct amdgpu_irq_src *),405 GFP_KERNEL);406 if (!adev->irq.client[client_id].sources)407 return -ENOMEM;408 }409 410 if (adev->irq.client[client_id].sources[src_id] != NULL)411 return -EINVAL;412 413 if (source->num_types && !source->enabled_types) {414 atomic_t *types;415 416 types = kcalloc(source->num_types, sizeof(atomic_t),417 GFP_KERNEL);418 if (!types)419 return -ENOMEM;420 421 source->enabled_types = types;422 }423 424 adev->irq.client[client_id].sources[src_id] = source;425 return 0;426}427 428/**429 * amdgpu_irq_dispatch - dispatch IRQ to IP blocks430 *431 * @adev: amdgpu device pointer432 * @ih: interrupt ring instance433 *434 * Dispatches IRQ to IP blocks.435 */436void amdgpu_irq_dispatch(struct amdgpu_device *adev,437 struct amdgpu_ih_ring *ih)438{439 u32 ring_index = ih->rptr >> 2;440 struct amdgpu_iv_entry entry;441 unsigned int client_id, src_id;442 struct amdgpu_irq_src *src;443 bool handled = false;444 int r;445 446 entry.ih = ih;447 entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];448 449 /*450 * timestamp is not supported on some legacy SOCs (cik, cz, iceland,451 * si and tonga), so initialize timestamp and timestamp_src to 0452 */453 entry.timestamp = 0;454 entry.timestamp_src = 0;455 456 amdgpu_ih_decode_iv(adev, &entry);457 458 trace_amdgpu_iv(ih - &adev->irq.ih, &entry);459 460 client_id = entry.client_id;461 src_id = entry.src_id;462 463 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) {464 DRM_DEBUG("Invalid client_id in IV: %d\n", client_id);465 466 } else if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) {467 DRM_DEBUG("Invalid src_id in IV: %d\n", src_id);468 469 } else if (((client_id == AMDGPU_IRQ_CLIENTID_LEGACY) ||470 (client_id == SOC15_IH_CLIENTID_ISP)) &&471 adev->irq.virq[src_id]) {472 generic_handle_domain_irq(adev->irq.domain, src_id);473 474 } else if (!adev->irq.client[client_id].sources) {475 DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n",476 client_id, src_id);477 478 } else if ((src = adev->irq.client[client_id].sources[src_id])) {479 r = src->funcs->process(adev, src, &entry);480 if (r < 0)481 DRM_ERROR("error processing interrupt (%d)\n", r);482 else if (r)483 handled = true;484 485 } else {486 DRM_DEBUG("Unregistered interrupt src_id: %d of client_id:%d\n",487 src_id, client_id);488 }489 490 /* Send it to amdkfd as well if it isn't already handled */491 if (!handled)492 amdgpu_amdkfd_interrupt(adev, entry.iv_entry);493 494 if (amdgpu_ih_ts_after(ih->processed_timestamp, entry.timestamp))495 ih->processed_timestamp = entry.timestamp;496}497 498/**499 * amdgpu_irq_delegate - delegate IV to soft IH ring500 *501 * @adev: amdgpu device pointer502 * @entry: IV entry503 * @num_dw: size of IV504 *505 * Delegate the IV to the soft IH ring and schedule processing of it. Used506 * if the hardware delegation to IH1 or IH2 doesn't work for some reason.507 */508void amdgpu_irq_delegate(struct amdgpu_device *adev,509 struct amdgpu_iv_entry *entry,510 unsigned int num_dw)511{512 amdgpu_ih_ring_write(adev, &adev->irq.ih_soft, entry->iv_entry, num_dw);513 schedule_work(&adev->irq.ih_soft_work);514}515 516/**517 * amdgpu_irq_update - update hardware interrupt state518 *519 * @adev: amdgpu device pointer520 * @src: interrupt source pointer521 * @type: type of interrupt522 *523 * Updates interrupt state for the specific source (all ASICs).524 */525int amdgpu_irq_update(struct amdgpu_device *adev,526 struct amdgpu_irq_src *src, unsigned int type)527{528 unsigned long irqflags;529 enum amdgpu_interrupt_state state;530 int r;531 532 spin_lock_irqsave(&adev->irq.lock, irqflags);533 534 /* We need to determine after taking the lock, otherwise535 * we might disable just enabled interrupts again536 */537 if (amdgpu_irq_enabled(adev, src, type))538 state = AMDGPU_IRQ_STATE_ENABLE;539 else540 state = AMDGPU_IRQ_STATE_DISABLE;541 542 r = src->funcs->set(adev, src, type, state);543 spin_unlock_irqrestore(&adev->irq.lock, irqflags);544 return r;545}546 547/**548 * amdgpu_irq_gpu_reset_resume_helper - update interrupt states on all sources549 *550 * @adev: amdgpu device pointer551 *552 * Updates state of all types of interrupts on all sources on resume after553 * reset.554 */555void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)556{557 int i, j, k;558 559 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))560 amdgpu_restore_msix(adev);561 562 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {563 if (!adev->irq.client[i].sources)564 continue;565 566 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {567 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];568 569 if (!src || !src->funcs || !src->funcs->set)570 continue;571 for (k = 0; k < src->num_types; k++)572 amdgpu_irq_update(adev, src, k);573 }574 }575}576 577/**578 * amdgpu_irq_get - enable interrupt579 *580 * @adev: amdgpu device pointer581 * @src: interrupt source pointer582 * @type: type of interrupt583 *584 * Enables specified type of interrupt on the specified source (all ASICs).585 *586 * Returns:587 * 0 on success or error code otherwise588 */589int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,590 unsigned int type)591{592 if (!adev->irq.installed)593 return -ENOENT;594 595 if (type >= src->num_types)596 return -EINVAL;597 598 if (!src->enabled_types || !src->funcs->set)599 return -EINVAL;600 601 if (atomic_inc_return(&src->enabled_types[type]) == 1)602 return amdgpu_irq_update(adev, src, type);603 604 return 0;605}606 607/**608 * amdgpu_irq_put - disable interrupt609 *610 * @adev: amdgpu device pointer611 * @src: interrupt source pointer612 * @type: type of interrupt613 *614 * Enables specified type of interrupt on the specified source (all ASICs).615 *616 * Returns:617 * 0 on success or error code otherwise618 */619int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,620 unsigned int type)621{622 if (!adev->irq.installed)623 return -ENOENT;624 625 if (type >= src->num_types)626 return -EINVAL;627 628 if (!src->enabled_types || !src->funcs->set)629 return -EINVAL;630 631 if (WARN_ON(!amdgpu_irq_enabled(adev, src, type)))632 return -EINVAL;633 634 if (atomic_dec_and_test(&src->enabled_types[type]))635 return amdgpu_irq_update(adev, src, type);636 637 return 0;638}639 640/**641 * amdgpu_irq_enabled - check whether interrupt is enabled or not642 *643 * @adev: amdgpu device pointer644 * @src: interrupt source pointer645 * @type: type of interrupt646 *647 * Checks whether the given type of interrupt is enabled on the given source.648 *649 * Returns:650 * *true* if interrupt is enabled, *false* if interrupt is disabled or on651 * invalid parameters652 */653bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,654 unsigned int type)655{656 if (!adev->irq.installed)657 return false;658 659 if (type >= src->num_types)660 return false;661 662 if (!src->enabled_types || !src->funcs->set)663 return false;664 665 return !!atomic_read(&src->enabled_types[type]);666}667 668/* XXX: Generic IRQ handling */669static void amdgpu_irq_mask(struct irq_data *irqd)670{671 /* XXX */672}673 674static void amdgpu_irq_unmask(struct irq_data *irqd)675{676 /* XXX */677}678 679/* amdgpu hardware interrupt chip descriptor */680static struct irq_chip amdgpu_irq_chip = {681 .name = "amdgpu-ih",682 .irq_mask = amdgpu_irq_mask,683 .irq_unmask = amdgpu_irq_unmask,684};685 686/**687 * amdgpu_irqdomain_map - create mapping between virtual and hardware IRQ numbers688 *689 * @d: amdgpu IRQ domain pointer (unused)690 * @irq: virtual IRQ number691 * @hwirq: hardware irq number692 *693 * Current implementation assigns simple interrupt handler to the given virtual694 * IRQ.695 *696 * Returns:697 * 0 on success or error code otherwise698 */699static int amdgpu_irqdomain_map(struct irq_domain *d,700 unsigned int irq, irq_hw_number_t hwirq)701{702 if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID)703 return -EPERM;704 705 irq_set_chip_and_handler(irq,706 &amdgpu_irq_chip, handle_simple_irq);707 return 0;708}709 710/* Implementation of methods for amdgpu IRQ domain */711static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = {712 .map = amdgpu_irqdomain_map,713};714 715/**716 * amdgpu_irq_add_domain - create a linear IRQ domain717 *718 * @adev: amdgpu device pointer719 *720 * Creates an IRQ domain for GPU interrupt sources721 * that may be driven by another driver (e.g., ACP).722 *723 * Returns:724 * 0 on success or error code otherwise725 */726int amdgpu_irq_add_domain(struct amdgpu_device *adev)727{728 adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID,729 &amdgpu_hw_irqdomain_ops, adev);730 if (!adev->irq.domain) {731 DRM_ERROR("GPU irq add domain failed\n");732 return -ENODEV;733 }734 735 return 0;736}737 738/**739 * amdgpu_irq_remove_domain - remove the IRQ domain740 *741 * @adev: amdgpu device pointer742 *743 * Removes the IRQ domain for GPU interrupt sources744 * that may be driven by another driver (e.g., ACP).745 */746void amdgpu_irq_remove_domain(struct amdgpu_device *adev)747{748 if (adev->irq.domain) {749 irq_domain_remove(adev->irq.domain);750 adev->irq.domain = NULL;751 }752}753 754/**755 * amdgpu_irq_create_mapping - create mapping between domain Linux IRQs756 *757 * @adev: amdgpu device pointer758 * @src_id: IH source id759 *760 * Creates mapping between a domain IRQ (GPU IH src id) and a Linux IRQ761 * Use this for components that generate a GPU interrupt, but are driven762 * by a different driver (e.g., ACP).763 *764 * Returns:765 * Linux IRQ766 */767unsigned int amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned int src_id)768{769 adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id);770 771 return adev->irq.virq[src_id];772}773