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1/*2 * Copyright 2019 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23 24#ifndef __AMDGPU_JPEG_H__25#define __AMDGPU_JPEG_H__26 27#include "amdgpu_ras.h"28 29#define AMDGPU_MAX_JPEG_INSTANCES 430#define AMDGPU_MAX_JPEG_RINGS 831 32#define AMDGPU_JPEG_HARVEST_JPEG0 (1 << 0)33#define AMDGPU_JPEG_HARVEST_JPEG1 (1 << 1)34 35#define WREG32_SOC15_JPEG_DPG_MODE(inst_idx, offset, value, indirect) \36 do { \37 if (!indirect) { \38 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \39 mmUVD_DPG_LMA_DATA, value); \40 WREG32_SOC15( \41 JPEG, GET_INST(JPEG, inst_idx), \42 mmUVD_DPG_LMA_CTL, \43 (UVD_DPG_LMA_CTL__READ_WRITE_MASK | \44 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT | \45 indirect << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \46 } else { \47 *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = \48 offset; \49 *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = \50 value; \51 } \52 } while (0)53 54#define RREG32_SOC15_JPEG_DPG_MODE(inst_idx, offset, mask_en) \55 ({ \56 WREG32_SOC15(JPEG, inst_idx, mmUVD_DPG_LMA_CTL, \57 (0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \58 mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \59 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \60 RREG32_SOC15(JPEG, inst_idx, mmUVD_DPG_LMA_DATA); \61 })62 63#define WREG32_SOC24_JPEG_DPG_MODE(inst_idx, offset, value, indirect) \64 do { \65 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \66 regUVD_DPG_LMA_DATA, value); \67 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \68 regUVD_DPG_LMA_MASK, 0xFFFFFFFF); \69 WREG32_SOC15( \70 JPEG, GET_INST(JPEG, inst_idx), \71 regUVD_DPG_LMA_CTL, \72 (UVD_DPG_LMA_CTL__READ_WRITE_MASK | \73 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT | \74 indirect << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \75 } while (0)76 77#define RREG32_SOC24_JPEG_DPG_MODE(inst_idx, offset, mask_en) \78 do { \79 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \80 regUVD_DPG_LMA_MASK, 0xFFFFFFFF); \81 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \82 regUVD_DPG_LMA_CTL, \83 (UVD_DPG_LMA_CTL__MASK_EN_MASK | \84 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \85 RREG32_SOC15(JPEG, inst_idx, regUVD_DPG_LMA_DATA); \86 } while (0)87 88#define ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, offset, value, indirect) \89 do { \90 *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = offset; \91 *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = value; \92 } while (0)93 94struct amdgpu_jpeg_reg{95 unsigned jpeg_pitch[AMDGPU_MAX_JPEG_RINGS];96};97 98struct amdgpu_jpeg_inst {99 struct amdgpu_ring ring_dec[AMDGPU_MAX_JPEG_RINGS];100 struct amdgpu_irq_src irq;101 struct amdgpu_irq_src ras_poison_irq;102 struct amdgpu_jpeg_reg external;103 struct amdgpu_bo *dpg_sram_bo;104 struct dpg_pause_state pause_state;105 void *dpg_sram_cpu_addr;106 uint64_t dpg_sram_gpu_addr;107 uint32_t *dpg_sram_curr_addr;108 uint8_t aid_id;109};110 111struct amdgpu_jpeg_ras {112 struct amdgpu_ras_block_object ras_block;113};114 115struct amdgpu_jpeg {116 uint8_t num_jpeg_inst;117 struct amdgpu_jpeg_inst inst[AMDGPU_MAX_JPEG_INSTANCES];118 unsigned num_jpeg_rings;119 struct amdgpu_jpeg_reg internal;120 unsigned harvest_config;121 struct delayed_work idle_work;122 enum amd_powergating_state cur_state;123 struct mutex jpeg_pg_lock;124 atomic_t total_submission_cnt;125 struct ras_common_if *ras_if;126 struct amdgpu_jpeg_ras *ras;127 128 uint16_t inst_mask;129 uint8_t num_inst_per_aid;130 bool indirect_sram;131};132 133int amdgpu_jpeg_sw_init(struct amdgpu_device *adev);134int amdgpu_jpeg_sw_fini(struct amdgpu_device *adev);135int amdgpu_jpeg_suspend(struct amdgpu_device *adev);136int amdgpu_jpeg_resume(struct amdgpu_device *adev);137 138void amdgpu_jpeg_ring_begin_use(struct amdgpu_ring *ring);139void amdgpu_jpeg_ring_end_use(struct amdgpu_ring *ring);140 141int amdgpu_jpeg_dec_ring_test_ring(struct amdgpu_ring *ring);142int amdgpu_jpeg_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);143 144int amdgpu_jpeg_process_poison_irq(struct amdgpu_device *adev,145 struct amdgpu_irq_src *source,146 struct amdgpu_iv_entry *entry);147int amdgpu_jpeg_ras_late_init(struct amdgpu_device *adev,148 struct ras_common_if *ras_block);149int amdgpu_jpeg_ras_sw_init(struct amdgpu_device *adev);150int amdgpu_jpeg_psp_update_sram(struct amdgpu_device *adev, int inst_idx,151 enum AMDGPU_UCODE_ID ucode_id);152 153#endif /*__AMDGPU_JPEG_H__*/154